include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17  */
  18
  19 #ifndef __ASM_ARM_KVM_VGIC_H
  20 #define __ASM_ARM_KVM_VGIC_H
  21
  22 #include <linux/kernel.h>
  23 #include <linux/kvm.h>
  24 #include <linux/irqreturn.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27
  28 #define VGIC_NR_IRQS_LEGACY     256
  29 #define VGIC_NR_SGIS            16
  30 #define VGIC_NR_PPIS            16
  31 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  32
  33 #define VGIC_V2_MAX_LRS         (1 << 6)
  34 #define VGIC_V3_MAX_LRS         16
  35 #define VGIC_MAX_IRQS           1024
  36
  37 /* Sanity checks... */
  38 #if (KVM_MAX_VCPUS > 8)
  39 #error  Invalid number of CPU interfaces
  40 #endif
  41
  42 #if (VGIC_NR_IRQS_LEGACY & 31)
  43 #error "VGIC_NR_IRQS must be a multiple of 32"
  44 #endif
  45
  46 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
  47 #error "VGIC_NR_IRQS must be <= 1024"
  48 #endif
  49
  50 /*
  51  * The GIC distributor registers describing interrupts have two parts:
  52  * - 32 per-CPU interrupts (SGI + PPI)
  53  * - a bunch of shared interrupts (SPI)
  54  */
  55 struct vgic_bitmap {
  56         /*
  57          * - One UL per VCPU for private interrupts (assumes UL is at
  58          *   least 32 bits)
  59          * - As many UL as necessary for shared interrupts.
  60          *
  61          * The private interrupts are accessed via the "private"
  62          * field, one UL per vcpu (the state for vcpu n is in
  63          * private[n]). The shared interrupts are accessed via the
  64          * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
  65          */
  66         unsigned long *private;
  67         unsigned long *shared;
  68 };
  69
  70 struct vgic_bytemap {
  71         /*
  72          * - 8 u32 per VCPU for private interrupts
  73          * - As many u32 as necessary for shared interrupts.
  74          *
  75          * The private interrupts are accessed via the "private"
  76          * field, (the state for vcpu n is in private[n*8] to
  77          * private[n*8 + 7]). The shared interrupts are accessed via
  78          * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
  79          * shared[(n-32)/4] word).
  80          */
  81         u32 *private;
  82         u32 *shared;
  83 };
  84
  85 struct kvm_vcpu;
  86
  87 enum vgic_type {
  88         VGIC_V2,                /* Good ol' GICv2 */
  89         VGIC_V3,                /* New fancy GICv3 */
  90 };
  91
  92 #define LR_STATE_PENDING        (1 << 0)
  93 #define LR_STATE_ACTIVE         (1 << 1)
  94 #define LR_STATE_MASK           (3 << 0)
  95 #define LR_EOI_INT              (1 << 2)
  96
  97 struct vgic_lr {
  98         u16     irq;
  99         u8      source;
 100         u8      state;
 101 };
 102
 103 struct vgic_vmcr {
 104         u32     ctlr;
 105         u32     abpr;
 106         u32     bpr;
 107         u32     pmr;
 108 };
 109
 110 struct vgic_ops {
 111         struct vgic_lr  (*get_lr)(const struct kvm_vcpu *, int);
 112         void    (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
 113         void    (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
 114         u64     (*get_elrsr)(const struct kvm_vcpu *vcpu);
 115         u64     (*get_eisr)(const struct kvm_vcpu *vcpu);
 116         u32     (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
 117         void    (*enable_underflow)(struct kvm_vcpu *vcpu);
 118         void    (*disable_underflow)(struct kvm_vcpu *vcpu);
 119         void    (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 120         void    (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 121         void    (*enable)(struct kvm_vcpu *vcpu);
 122 };
 123
 124 struct vgic_params {
 125         /* vgic type */
 126         enum vgic_type  type;
 127         /* Physical address of vgic virtual cpu interface */
 128         phys_addr_t     vcpu_base;
 129         /* Number of list registers */
 130         u32             nr_lr;
 131         /* Interrupt number */
 132         unsigned int    maint_irq;
 133         /* Virtual control interface base address */
 134         void __iomem    *vctrl_base;
 135 };
 136
 137 struct vgic_dist {
 138 #ifdef CONFIG_KVM_ARM_VGIC
 139         spinlock_t              lock;
 140         bool                    in_kernel;
 141         bool                    ready;
 142
 143         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 144         u32                     vgic_model;
 145
 146         int                     nr_cpus;
 147         int                     nr_irqs;
 148
 149         /* Virtual control interface mapping */
 150         void __iomem            *vctrl_base;
 151
 152         /* Distributor and vcpu interface mapping in the guest */
 153         phys_addr_t             vgic_dist_base;
 154         phys_addr_t             vgic_cpu_base;
 155
 156         /* Distributor enabled */
 157         u32                     enabled;
 158
 159         /* Interrupt enabled (one bit per IRQ) */
 160         struct vgic_bitmap      irq_enabled;
 161
 162         /* Level-triggered interrupt external input is asserted */
 163         struct vgic_bitmap      irq_level;
 164
 165         /*
 166          * Interrupt state is pending on the distributor
 167          */
 168         struct vgic_bitmap      irq_pending;
 169
 170         /*
 171          * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
 172          * interrupts.  Essentially holds the state of the flip-flop in
 173          * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
 174          * Once set, it is only cleared for level-triggered interrupts on
 175          * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
 176          */
 177         struct vgic_bitmap      irq_soft_pend;
 178
 179         /* Level-triggered interrupt queued on VCPU interface */
 180         struct vgic_bitmap      irq_queued;
 181
 182         /* Interrupt priority. Not used yet. */
 183         struct vgic_bytemap     irq_priority;
 184
 185         /* Level/edge triggered */
 186         struct vgic_bitmap      irq_cfg;
 187
 188         /*
 189          * Source CPU per SGI and target CPU:
 190          *
 191          * Each byte represent a SGI observable on a VCPU, each bit of
 192          * this byte indicating if the corresponding VCPU has
 193          * generated this interrupt. This is a GICv2 feature only.
 194          *
 195          * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
 196          * the SGIs observable on VCPUn.
 197          */
 198         u8                      *irq_sgi_sources;
 199
 200         /*
 201          * Target CPU for each SPI:
 202          *
 203          * Array of available SPI, each byte indicating the target
 204          * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
 205          */
 206         u8                      *irq_spi_cpu;
 207
 208         /*
 209          * Reverse lookup of irq_spi_cpu for faster compute pending:
 210          *
 211          * Array of bitmaps, one per VCPU, describing if IRQn is
 212          * routed to a particular VCPU.
 213          */
 214         struct vgic_bitmap      *irq_spi_target;
 215
 216         /* Bitmap indicating which CPU has something pending */
 217         unsigned long           *irq_pending_on_cpu;
 218 #endif
 219 };
 220
 221 struct vgic_v2_cpu_if {
 222         u32             vgic_hcr;
 223         u32             vgic_vmcr;
 224         u32             vgic_misr;      /* Saved only */
 225         u64             vgic_eisr;      /* Saved only */
 226         u64             vgic_elrsr;     /* Saved only */
 227         u32             vgic_apr;
 228         u32             vgic_lr[VGIC_V2_MAX_LRS];
 229 };
 230
 231 struct vgic_v3_cpu_if {
 232 #ifdef CONFIG_ARM_GIC_V3
 233         u32             vgic_hcr;
 234         u32             vgic_vmcr;
 235         u32             vgic_misr;      /* Saved only */
 236         u32             vgic_eisr;      /* Saved only */
 237         u32             vgic_elrsr;     /* Saved only */
 238         u32             vgic_ap0r[4];
 239         u32             vgic_ap1r[4];
 240         u64             vgic_lr[VGIC_V3_MAX_LRS];
 241 #endif
 242 };
 243
 244 struct vgic_cpu {
 245 #ifdef CONFIG_KVM_ARM_VGIC
 246         /* per IRQ to LR mapping */
 247         u8              *vgic_irq_lr_map;
 248
 249         /* Pending interrupts on this VCPU */
 250         DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
 251         unsigned long   *pending_shared;
 252
 253         /* Bitmap of used/free list registers */
 254         DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
 255
 256         /* Number of list registers on this CPU */
 257         int             nr_lr;
 258
 259         /* CPU vif control registers for world switch */
 260         union {
 261                 struct vgic_v2_cpu_if   vgic_v2;
 262                 struct vgic_v3_cpu_if   vgic_v3;
 263         };
 264 #endif
 265 };
 266
 267 #define LR_EMPTY        0xff
 268
 269 #define INT_STATUS_EOI          (1 << 0)
 270 #define INT_STATUS_UNDERFLOW    (1 << 1)
 271
 272 struct kvm;
 273 struct kvm_vcpu;
 274 struct kvm_run;
 275 struct kvm_exit_mmio;
 276
 277 #ifdef CONFIG_KVM_ARM_VGIC
 278 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 279 int kvm_vgic_hyp_init(void);
 280 int kvm_vgic_map_resources(struct kvm *kvm);
 281 int kvm_vgic_create(struct kvm *kvm, u32 type);
 282 void kvm_vgic_destroy(struct kvm *kvm);
 283 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 284 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 285 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 286 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
 287                         bool level);
 288 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 289 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 290                       struct kvm_exit_mmio *mmio);
 291
 292 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 293 #define vgic_initialized(k)     (!!((k)->arch.vgic.nr_cpus))
 294 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 295
 296 int vgic_v2_probe(struct device_node *vgic_node,
 297                   const struct vgic_ops **ops,
 298                   const struct vgic_params **params);
 299 #ifdef CONFIG_ARM_GIC_V3
 300 int vgic_v3_probe(struct device_node *vgic_node,
 301                   const struct vgic_ops **ops,
 302                   const struct vgic_params **params);
 303 #else
 304 static inline int vgic_v3_probe(struct device_node *vgic_node,
 305                                 const struct vgic_ops **ops,
 306                                 const struct vgic_params **params)
 307 {
 308         return -ENODEV;
 309 }
 310 #endif
 311
 312 #else
 313 static inline int kvm_vgic_hyp_init(void)
 314 {
 315         return 0;
 316 }
 317
 318 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
 319 {
 320         return 0;
 321 }
 322
 323 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
 324 {
 325         return -ENXIO;
 326 }
 327
 328 static inline int kvm_vgic_map_resources(struct kvm *kvm)
 329 {
 330         return 0;
 331 }
 332
 333 static inline int kvm_vgic_create(struct kvm *kvm, u32 type)
 334 {
 335         return 0;
 336 }
 337
 338 static inline void kvm_vgic_destroy(struct kvm *kvm)
 339 {
 340 }
 341
 342 static inline void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
 343 {
 344 }
 345
 346 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
 347 {
 348         return 0;
 349 }
 350
 351 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
 352 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
 353
 354 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
 355                                       unsigned int irq_num, bool level)
 356 {
 357         return 0;
 358 }
 359
 360 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
 361 {
 362         return 0;
 363 }
 364
 365 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
 366                                     struct kvm_exit_mmio *mmio)
 367 {
 368         return false;
 369 }
 370
 371 static inline int irqchip_in_kernel(struct kvm *kvm)
 372 {
 373         return 0;
 374 }
 375
 376 static inline bool vgic_initialized(struct kvm *kvm)
 377 {
 378         return true;
 379 }
 380
 381 static inline bool vgic_ready(struct kvm *kvm)
 382 {
 383         return true;
 384 }
 385 #endif
 386
 387 #endif