include/linux/amba/pl08x.h

   1 /*
   2  * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
   3  *
   4  * Copyright (C) 2005 ARM Ltd
   5  * Copyright (C) 2010 ST-Ericsson SA
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * pl08x information required by platform code
  12  *
  13  * Please credit ARM.com
  14  * Documentation: ARM DDI 0196D
  15  */
  16
  17 #ifndef AMBA_PL08X_H
  18 #define AMBA_PL08X_H
  19
  20 /* We need sizes of structs from this header */
  21 #include <linux/dmaengine.h>
  22 #include <linux/interrupt.h>
  23
  24 struct pl08x_lli;
  25 struct pl08x_driver_data;
  26
  27 /* Bitmasks for selecting AHB ports for DMA transfers */
  28 enum {
  29         PL08X_AHB1 = (1 << 0),
  30         PL08X_AHB2 = (1 << 1)
  31 };
  32
  33 /**
  34  * struct pl08x_channel_data - data structure to pass info between
  35  * platform and PL08x driver regarding channel configuration
  36  * @bus_id: name of this device channel, not just a device name since
  37  * devices may have more than one channel e.g. "foo_tx"
  38  * @min_signal: the minimum DMA signal number to be muxed in for this
  39  * channel (for platforms supporting muxed signals). If you have
  40  * static assignments, make sure this is set to the assigned signal
  41  * number, PL08x have 16 possible signals in number 0 thru 15 so
  42  * when these are not enough they often get muxed (in hardware)
  43  * disabling simultaneous use of the same channel for two devices.
  44  * @max_signal: the maximum DMA signal number to be muxed in for
  45  * the channel. Set to the same as min_signal for
  46  * devices with static assignments
  47  * @muxval: a number usually used to poke into some mux regiser to
  48  * mux in the signal to this channel
  49  * @cctl_opt: default options for the channel control register
  50  * @addr: source/target address in physical memory for this DMA channel,
  51  * can be the address of a FIFO register for burst requests for example.
  52  * This can be left undefined if the PrimeCell API is used for configuring
  53  * this.
  54  * @circular_buffer: whether the buffer passed in is circular and
  55  * shall simply be looped round round (like a record baby round
  56  * round round round)
  57  * @single: the device connected to this channel will request single DMA
  58  * transfers, not bursts. (Bursts are default.)
  59  * @periph_buses: the device connected to this channel is accessible via
  60  * these buses (use PL08X_AHB1 | PL08X_AHB2).
  61  */
  62 struct pl08x_channel_data {
  63         char *bus_id;
  64         int min_signal;
  65         int max_signal;
  66         u32 muxval;
  67         u32 cctl;
  68         dma_addr_t addr;
  69         bool circular_buffer;
  70         bool single;
  71         u8 periph_buses;
  72 };
  73
  74 /**
  75  * Struct pl08x_bus_data - information of source or destination
  76  * busses for a transfer
  77  * @addr: current address
  78  * @maxwidth: the maximum width of a transfer on this bus
  79  * @buswidth: the width of this bus in bytes: 1, 2 or 4
  80  */
  81 struct pl08x_bus_data {
  82         dma_addr_t addr;
  83         u8 maxwidth;
  84         u8 buswidth;
  85 };
  86
  87 /**
  88  * struct pl08x_phy_chan - holder for the physical channels
  89  * @id: physical index to this channel
  90  * @lock: a lock to use when altering an instance of this struct
  91  * @signal: the physical signal (aka channel) serving this physical channel
  92  * right now
  93  * @serving: the virtual channel currently being served by this physical
  94  * channel
  95  */
  96 struct pl08x_phy_chan {
  97         unsigned int id;
  98         void __iomem *base;
  99         spinlock_t lock;
 100         int signal;
 101         struct pl08x_dma_chan *serving;
 102 };
 103
 104 /**
 105  * struct pl08x_sg - structure containing data per sg
 106  * @src_addr: src address of sg
 107  * @dst_addr: dst address of sg
 108  * @len: transfer len in bytes
 109  * @node: node for txd's dsg_list
 110  */
 111 struct pl08x_sg {
 112         dma_addr_t src_addr;
 113         dma_addr_t dst_addr;
 114         size_t len;
 115         struct list_head node;
 116 };
 117
 118 /**
 119  * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
 120  * @tx: async tx descriptor
 121  * @node: node for txd list for channels
 122  * @dsg_list: list of children sg's
 123  * @direction: direction of transfer
 124  * @llis_bus: DMA memory address (physical) start for the LLIs
 125  * @llis_va: virtual memory address start for the LLIs
 126  * @cctl: control reg values for current txd
 127  * @ccfg: config reg values for current txd
 128  */
 129 struct pl08x_txd {
 130         struct dma_async_tx_descriptor tx;
 131         struct list_head node;
 132         struct list_head dsg_list;
 133         enum dma_transfer_direction direction;
 134         dma_addr_t llis_bus;
 135         struct pl08x_lli *llis_va;
 136         /* Default cctl value for LLIs */
 137         u32 cctl;
 138         /*
 139          * Settings to be put into the physical channel when we
 140          * trigger this txd.  Other registers are in llis_va[0].
 141          */
 142         u32 ccfg;
 143 };
 144
 145 /**
 146  * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
 147  * states
 148  * @PL08X_CHAN_IDLE: the channel is idle
 149  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
 150  * channel and is running a transfer on it
 151  * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
 152  * channel, but the transfer is currently paused
 153  * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
 154  * channel to become available (only pertains to memcpy channels)
 155  */
 156 enum pl08x_dma_chan_state {
 157         PL08X_CHAN_IDLE,
 158         PL08X_CHAN_RUNNING,
 159         PL08X_CHAN_PAUSED,
 160         PL08X_CHAN_WAITING,
 161 };
 162
 163 /**
 164  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
 165  * @chan: wrappped abstract channel
 166  * @phychan: the physical channel utilized by this channel, if there is one
 167  * @phychan_hold: if non-zero, hold on to the physical channel even if we
 168  * have no pending entries
 169  * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
 170  * @name: name of channel
 171  * @cd: channel platform data
 172  * @runtime_addr: address for RX/TX according to the runtime config
 173  * @runtime_direction: current direction of this channel according to
 174  * runtime config
 175  * @pend_list: queued transactions pending on this channel
 176  * @at: active transaction on this channel
 177  * @lock: a lock for this channel data
 178  * @host: a pointer to the host (internal use)
 179  * @state: whether the channel is idle, paused, running etc
 180  * @slave: whether this channel is a device (slave) or for memcpy
 181  * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
 182  * channels. Fill with 'true' if peripheral should be flow controller. Direction
 183  * will be selected at Runtime.
 184  * @waiting: a TX descriptor on this channel which is waiting for a physical
 185  * channel to become available
 186  */
 187 struct pl08x_dma_chan {
 188         struct dma_chan chan;
 189         struct pl08x_phy_chan *phychan;
 190         int phychan_hold;
 191         struct tasklet_struct tasklet;
 192         char *name;
 193         const struct pl08x_channel_data *cd;
 194         dma_addr_t src_addr;
 195         dma_addr_t dst_addr;
 196         u32 src_cctl;
 197         u32 dst_cctl;
 198         enum dma_transfer_direction runtime_direction;
 199         struct list_head pend_list;
 200         struct pl08x_txd *at;
 201         spinlock_t lock;
 202         struct pl08x_driver_data *host;
 203         enum pl08x_dma_chan_state state;
 204         bool slave;
 205         bool device_fc;
 206         struct pl08x_txd *waiting;
 207 };
 208
 209 /**
 210  * struct pl08x_platform_data - the platform configuration for the PL08x
 211  * PrimeCells.
 212  * @slave_channels: the channels defined for the different devices on the
 213  * platform, all inclusive, including multiplexed channels. The available
 214  * physical channels will be multiplexed around these signals as they are
 215  * requested, just enumerate all possible channels.
 216  * @get_signal: request a physical signal to be used for a DMA transfer
 217  * immediately: if there is some multiplexing or similar blocking the use
 218  * of the channel the transfer can be denied by returning less than zero,
 219  * else it returns the allocated signal number
 220  * @put_signal: indicate to the platform that this physical signal is not
 221  * running any DMA transfer and multiplexing can be recycled
 222  * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
 223  * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
 224  */
 225 struct pl08x_platform_data {
 226         const struct pl08x_channel_data *slave_channels;
 227         unsigned int num_slave_channels;
 228         struct pl08x_channel_data memcpy_channel;
 229         int (*get_signal)(struct pl08x_dma_chan *);
 230         void (*put_signal)(struct pl08x_dma_chan *);
 231         u8 lli_buses;
 232         u8 mem_buses;
 233 };
 234
 235 #ifdef CONFIG_AMBA_PL08X
 236 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
 237 #else
 238 static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 239 {
 240         return false;
 241 }
 242 #endif
 243
 244 #endif  /* AMBA_PL08X_H */