include/linux/brcmphy.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _LINUX_BRCMPHY_H
   3 #define _LINUX_BRCMPHY_H
   4
   5 #include <linux/phy.h>
   6
   7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
   8  * to configure the switch internal registers via MDIO accesses.
   9  */
  10 #define BRCM_PSEUDO_PHY_ADDR           30
  11
  12 #define PHY_ID_BCM50610                 0x0143bd60
  13 #define PHY_ID_BCM50610M                0x0143bd70
  14 #define PHY_ID_BCM5241                  0x0143bc30
  15 #define PHY_ID_BCMAC131                 0x0143bc70
  16 #define PHY_ID_BCM5481                  0x0143bca0
  17 #define PHY_ID_BCM54810                 0x03625d00
  18 #define PHY_ID_BCM5482                  0x0143bcb0
  19 #define PHY_ID_BCM5411                  0x00206070
  20 #define PHY_ID_BCM5421                  0x002060e0
  21 #define PHY_ID_BCM54210E                0x600d84a0
  22 #define PHY_ID_BCM5464                  0x002060b0
  23 #define PHY_ID_BCM5461                  0x002060c0
  24 #define PHY_ID_BCM54612E                0x03625e60
  25 #define PHY_ID_BCM54616S                0x03625d10
  26 #define PHY_ID_BCM57780                 0x03625d90
  27
  28 #define PHY_ID_BCM7250                  0xae025280
  29 #define PHY_ID_BCM7260                  0xae025190
  30 #define PHY_ID_BCM7268                  0xae025090
  31 #define PHY_ID_BCM7271                  0xae0253b0
  32 #define PHY_ID_BCM7278                  0xae0251a0
  33 #define PHY_ID_BCM7364                  0xae025260
  34 #define PHY_ID_BCM7366                  0x600d8490
  35 #define PHY_ID_BCM7346                  0x600d8650
  36 #define PHY_ID_BCM7362                  0x600d84b0
  37 #define PHY_ID_BCM7425                  0x600d86b0
  38 #define PHY_ID_BCM7429                  0x600d8730
  39 #define PHY_ID_BCM7435                  0x600d8750
  40 #define PHY_ID_BCM74371                 0xae0252e0
  41 #define PHY_ID_BCM7439                  0x600d8480
  42 #define PHY_ID_BCM7439_2                0xae025080
  43 #define PHY_ID_BCM7445                  0x600d8510
  44
  45 #define PHY_ID_BCM_CYGNUS               0xae025200
  46
  47 #define PHY_BCM_OUI_MASK                0xfffffc00
  48 #define PHY_BCM_OUI_1                   0x00206000
  49 #define PHY_BCM_OUI_2                   0x0143bc00
  50 #define PHY_BCM_OUI_3                   0x03625c00
  51 #define PHY_BCM_OUI_4                   0x600d8400
  52 #define PHY_BCM_OUI_5                   0x03625e00
  53 #define PHY_BCM_OUI_6                   0xae025000
  54
  55 #define PHY_BCM_FLAGS_MODE_COPPER       0x00000001
  56 #define PHY_BCM_FLAGS_MODE_1000BX       0x00000002
  57 #define PHY_BCM_FLAGS_INTF_SGMII        0x00000010
  58 #define PHY_BCM_FLAGS_INTF_XAUI         0x00000020
  59 #define PHY_BRCM_WIRESPEED_ENABLE       0x00000100
  60 #define PHY_BRCM_AUTO_PWRDWN_ENABLE     0x00000200
  61 #define PHY_BRCM_RX_REFCLK_UNUSED       0x00000400
  62 #define PHY_BRCM_STD_IBND_DISABLE       0x00000800
  63 #define PHY_BRCM_EXT_IBND_RX_ENABLE     0x00001000
  64 #define PHY_BRCM_EXT_IBND_TX_ENABLE     0x00002000
  65 #define PHY_BRCM_CLEAR_RGMII_MODE       0x00004000
  66 #define PHY_BRCM_DIS_TXCRXC_NOENRGY     0x00008000
  67 #define PHY_BRCM_EN_MASTER_MODE         0x00010000
  68
  69 /* Broadcom BCM7xxx specific workarounds */
  70 #define PHY_BRCM_7XXX_REV(x)            (((x) >> 8) & 0xff)
  71 #define PHY_BRCM_7XXX_PATCH(x)          ((x) & 0xff)
  72 #define PHY_BCM_FLAGS_VALID             0x80000000
  73
  74 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
  75 #define MII_BCM54XX_ECR         0x10    /* BCM54xx extended control register */
  76 #define MII_BCM54XX_ECR_IM      0x1000  /* Interrupt mask */
  77 #define MII_BCM54XX_ECR_IF      0x0800  /* Interrupt force */
  78
  79 #define MII_BCM54XX_ESR         0x11    /* BCM54xx extended status register */
  80 #define MII_BCM54XX_ESR_IS      0x1000  /* Interrupt status */
  81
  82 #define MII_BCM54XX_EXP_DATA    0x15    /* Expansion register data */
  83 #define MII_BCM54XX_EXP_SEL     0x17    /* Expansion register select */
  84 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00  /* Secondary SerDes select */
  85 #define MII_BCM54XX_EXP_SEL_ER  0x0f00  /* Expansion register select */
  86
  87 #define MII_BCM54XX_AUX_CTL     0x18    /* Auxiliary control register */
  88 #define MII_BCM54XX_ISR         0x1a    /* BCM54xx interrupt status register */
  89 #define MII_BCM54XX_IMR         0x1b    /* BCM54xx interrupt mask register */
  90 #define MII_BCM54XX_INT_CRCERR  0x0001  /* CRC error */
  91 #define MII_BCM54XX_INT_LINK    0x0002  /* Link status changed */
  92 #define MII_BCM54XX_INT_SPEED   0x0004  /* Link speed change */
  93 #define MII_BCM54XX_INT_DUPLEX  0x0008  /* Duplex mode changed */
  94 #define MII_BCM54XX_INT_LRS     0x0010  /* Local receiver status changed */
  95 #define MII_BCM54XX_INT_RRS     0x0020  /* Remote receiver status changed */
  96 #define MII_BCM54XX_INT_SSERR   0x0040  /* Scrambler synchronization error */
  97 #define MII_BCM54XX_INT_UHCD    0x0080  /* Unsupported HCD negotiated */
  98 #define MII_BCM54XX_INT_NHCD    0x0100  /* No HCD */
  99 #define MII_BCM54XX_INT_NHCDL   0x0200  /* No HCD link */
 100 #define MII_BCM54XX_INT_ANPR    0x0400  /* Auto-negotiation page received */
 101 #define MII_BCM54XX_INT_LC      0x0800  /* All counters below 128 */
 102 #define MII_BCM54XX_INT_HC      0x1000  /* Counter above 32768 */
 103 #define MII_BCM54XX_INT_MDIX    0x2000  /* MDIX status change */
 104 #define MII_BCM54XX_INT_PSERR   0x4000  /* Pair swap error */
 105
 106 #define MII_BCM54XX_SHD         0x1c    /* 0x1c shadow registers */
 107 #define MII_BCM54XX_SHD_WRITE   0x8000
 108 #define MII_BCM54XX_SHD_VAL(x)  ((x & 0x1f) << 10)
 109 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
 110
 111 /*
 112  * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
 113  */
 114 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x00
 115 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB          0x0400
 116 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA       0x0800
 117
 118 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC                 0x07
 119 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN    0x0010
 120 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN   0x0100
 121 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX             0x0200
 122 #define MII_BCM54XX_AUXCTL_MISC_WREN                    0x8000
 123
 124 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT   12
 125 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
 126
 127 /*
 128  * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
 129  * BCM5482, and possibly some others.
 130  */
 131 #define BCM_LED_SRC_LINKSPD1    0x0
 132 #define BCM_LED_SRC_LINKSPD2    0x1
 133 #define BCM_LED_SRC_XMITLED     0x2
 134 #define BCM_LED_SRC_ACTIVITYLED 0x3
 135 #define BCM_LED_SRC_FDXLED      0x4
 136 #define BCM_LED_SRC_SLAVE       0x5
 137 #define BCM_LED_SRC_INTR        0x6
 138 #define BCM_LED_SRC_QUALITY     0x7
 139 #define BCM_LED_SRC_RCVLED      0x8
 140 #define BCM_LED_SRC_WIRESPEED   0x9
 141 #define BCM_LED_SRC_MULTICOLOR1 0xa
 142 #define BCM_LED_SRC_OPENSHORT   0xb
 143 #define BCM_LED_SRC_OFF         0xe     /* Tied high */
 144 #define BCM_LED_SRC_ON          0xf     /* Tied low */
 145
 146
 147 /*
 148  * BCM5482: Shadow registers
 149  * Shadow values go into bits [14:10] of register 0x1c to select a shadow
 150  * register to access.
 151  */
 152
 153 /* 00100: Reserved control register 2 */
 154 #define BCM54XX_SHD_SCR2                0x04
 155 #define  BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
 156 #define  BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT   2
 157 #define  BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET  2
 158 #define  BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK    0x7
 159
 160 /* 00101: Spare Control Register 3 */
 161 #define BCM54XX_SHD_SCR3                0x05
 162 #define  BCM54XX_SHD_SCR3_DEF_CLK125    0x0001
 163 #define  BCM54XX_SHD_SCR3_DLLAPD_DIS    0x0002
 164 #define  BCM54XX_SHD_SCR3_TRDDAPD       0x0004
 165
 166 /* 01010: Auto Power-Down */
 167 #define BCM54XX_SHD_APD                 0x0a
 168 #define  BCM_APD_CLR_MASK               0xFE9F /* clear bits 5, 6 & 8 */
 169 #define  BCM54XX_SHD_APD_EN             0x0020
 170 #define  BCM_NO_ANEG_APD_EN             0x0060 /* bits 5 & 6 */
 171 #define  BCM_APD_SINGLELP_EN    0x0100 /* Bit 8 */
 172
 173 #define BCM5482_SHD_LEDS1       0x0d    /* 01101: LED Selector 1 */
 174                                         /* LED3 / ~LINKSPD[2] selector */
 175 #define BCM5482_SHD_LEDS1_LED3(src)     ((src & 0xf) << 4)
 176                                         /* LED1 / ~LINKSPD[1] selector */
 177 #define BCM5482_SHD_LEDS1_LED1(src)     ((src & 0xf) << 0)
 178 #define BCM54XX_SHD_RGMII_MODE  0x0b    /* 01011: RGMII Mode Selector */
 179 #define BCM5482_SHD_SSD         0x14    /* 10100: Secondary SerDes control */
 180 #define BCM5482_SHD_SSD_LEDM    0x0008  /* SSD LED Mode enable */
 181 #define BCM5482_SHD_SSD_EN      0x0001  /* SSD enable */
 182 #define BCM5482_SHD_MODE        0x1f    /* 11111: Mode Control Register */
 183 #define BCM5482_SHD_MODE_1000BX 0x0001  /* Enable 1000BASE-X registers */
 184
 185
 186 /*
 187  * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
 188  */
 189 #define MII_BCM54XX_EXP_AADJ1CH0                0x001f
 190 #define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN  0x0200
 191 #define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF    0x0100
 192 #define MII_BCM54XX_EXP_AADJ1CH3                0x601f
 193 #define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ      0x0002
 194 #define MII_BCM54XX_EXP_EXP08                   0x0F08
 195 #define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ        0x0001
 196 #define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE   0x0200
 197 #define MII_BCM54XX_EXP_EXP75                   0x0f75
 198 #define  MII_BCM54XX_EXP_EXP75_VDACCTRL         0x003c
 199 #define  MII_BCM54XX_EXP_EXP75_CM_OSC           0x0001
 200 #define MII_BCM54XX_EXP_EXP96                   0x0f96
 201 #define  MII_BCM54XX_EXP_EXP96_MYST             0x0010
 202 #define MII_BCM54XX_EXP_EXP97                   0x0f97
 203 #define  MII_BCM54XX_EXP_EXP97_MYST             0x0c0c
 204
 205 /*
 206  * BCM5482: Secondary SerDes registers
 207  */
 208 #define BCM5482_SSD_1000BX_CTL          0x00    /* 1000BASE-X Control */
 209 #define BCM5482_SSD_1000BX_CTL_PWRDOWN  0x0800  /* Power-down SSD */
 210 #define BCM5482_SSD_SGMII_SLAVE         0x15    /* SGMII Slave Register */
 211 #define BCM5482_SSD_SGMII_SLAVE_EN      0x0002  /* Slave mode enable */
 212 #define BCM5482_SSD_SGMII_SLAVE_AD      0x0001  /* Slave auto-detection */
 213
 214 /* BCM54810 Registers */
 215 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL    (MII_BCM54XX_EXP_SEL_ER + 0x90)
 216 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
 217 #define BCM54810_SHD_CLK_CTL                    0x3
 218 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN          (1 << 9)
 219
 220
 221 /*****************************************************************************/
 222 /* Fast Ethernet Transceiver definitions. */
 223 /*****************************************************************************/
 224
 225 #define MII_BRCM_FET_INTREG             0x1a    /* Interrupt register */
 226 #define MII_BRCM_FET_IR_MASK            0x0100  /* Mask all interrupts */
 227 #define MII_BRCM_FET_IR_LINK_EN         0x0200  /* Link status change enable */
 228 #define MII_BRCM_FET_IR_SPEED_EN        0x0400  /* Link speed change enable */
 229 #define MII_BRCM_FET_IR_DUPLEX_EN       0x0800  /* Duplex mode change enable */
 230 #define MII_BRCM_FET_IR_ENABLE          0x4000  /* Interrupt enable */
 231
 232 #define MII_BRCM_FET_BRCMTEST           0x1f    /* Brcm test register */
 233 #define MII_BRCM_FET_BT_SRE             0x0080  /* Shadow register enable */
 234
 235
 236 /*** Shadow register definitions ***/
 237
 238 #define MII_BRCM_FET_SHDW_MISCCTRL      0x10    /* Shadow misc ctrl */
 239 #define MII_BRCM_FET_SHDW_MC_FAME       0x4000  /* Force Auto MDIX enable */
 240
 241 #define MII_BRCM_FET_SHDW_AUXMODE4      0x1a    /* Auxiliary mode 4 */
 242 #define MII_BRCM_FET_SHDW_AM4_LED_MASK  0x0003
 243 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
 244
 245 #define MII_BRCM_FET_SHDW_AUXSTAT2      0x1b    /* Auxiliary status 2 */
 246 #define MII_BRCM_FET_SHDW_AS2_APDE      0x0020  /* Auto power down enable */
 247
 248 #define BRCM_CL45VEN_EEE_CONTROL        0x803d
 249 #define LPI_FEATURE_EN                  0x8000
 250 #define LPI_FEATURE_EN_DIG1000X         0x4000
 251
 252 /* Core register definitions*/
 253 #define MII_BRCM_CORE_BASE12    0x12
 254 #define MII_BRCM_CORE_BASE13    0x13
 255 #define MII_BRCM_CORE_BASE14    0x14
 256 #define MII_BRCM_CORE_BASE1E    0x1E
 257 #define MII_BRCM_CORE_EXPB0     0xB0
 258 #define MII_BRCM_CORE_EXPB1     0xB1
 259
 260 #endif /* _LINUX_BRCMPHY_H */