include/linux/broadcom/bcm2835_smi.h

   1 /**
   2  * Declarations and definitions for Broadcom's Secondary Memory Interface
   3  *
   4  * Written by Luke Wren <luke@raspberrypi.org>
   5  * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
   6  * Copyright (c) 2010-2012 Broadcom. All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions, and the following disclaimer,
  13  *    without modification.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The names of the above-listed copyright holders may not be used
  18  *    to endorse or promote products derived from this software without
  19  *    specific prior written permission.
  20  *
  21  * ALTERNATIVELY, this software may be distributed under the terms of the
  22  * GNU General Public License ("GPL") version 2, as published by the Free
  23  * Software Foundation.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef BCM2835_SMI_H
  39 #define BCM2835_SMI_H
  40
  41 #include <linux/ioctl.h>
  42
  43 #ifndef __KERNEL__
  44 #include <stdint.h>
  45 #include <stdbool.h>
  46 #endif
  47
  48 #define BCM2835_SMI_IOC_MAGIC 0x1
  49 #define BCM2835_SMI_INVALID_HANDLE (~0)
  50
  51 /* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
  52 #define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)
  53 #define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)
  54 #define BCM2835_SMI_IOC_ADDRESS  _IO(BCM2835_SMI_IOC_MAGIC, 2)
  55 #define BCM2835_SMI_IOC_MAX          2
  56
  57 #define SMI_WIDTH_8BIT 0
  58 #define SMI_WIDTH_16BIT 1
  59 #define SMI_WIDTH_9BIT 2
  60 #define SMI_WIDTH_18BIT 3
  61
  62 /* max number of bytes where DMA will not be used */
  63 #define DMA_THRESHOLD_BYTES 128
  64 #define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
  65 #define DMA_BOUNCE_BUFFER_COUNT 3
  66
  67
  68 struct smi_settings {
  69         int data_width;
  70         /* Whether or not to pack multiple SMI transfers into a
  71            single 32 bit FIFO word */
  72         bool pack_data;
  73
  74         /* Timing for reads (writes the same but for WE)
  75          *
  76          * OE ----------+          +--------------------
  77          *              |          |
  78          *              +----------+
  79          * SD -<==============================>-----------
  80          * SA -<=========================================>-
  81          *    <-setup->  <-strobe ->  <-hold ->  <- pace ->
  82          */
  83
  84         int read_setup_time;
  85         int read_hold_time;
  86         int read_pace_time;
  87         int read_strobe_time;
  88
  89         int write_setup_time;
  90         int write_hold_time;
  91         int write_pace_time;
  92         int write_strobe_time;
  93
  94         bool dma_enable;                /* DREQs */
  95         bool dma_passthrough_enable;    /* External DREQs */
  96         int dma_read_thresh;
  97         int dma_write_thresh;
  98         int dma_panic_read_thresh;
  99         int dma_panic_write_thresh;
 100 };
 101
 102 /****************************************************************************
 103 *
 104 *   Declare exported SMI functions
 105 *
 106 ***************************************************************************/
 107
 108 #ifdef __KERNEL__
 109
 110 #include <linux/dmaengine.h> /* for enum dma_transfer_direction */
 111 #include <linux/of.h>
 112 #include <linux/semaphore.h>
 113
 114 struct bcm2835_smi_instance;
 115
 116 struct bcm2835_smi_bounce_info {
 117         struct semaphore callback_sem;
 118         void *buffer[DMA_BOUNCE_BUFFER_COUNT];
 119         dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
 120         struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
 121 };
 122
 123
 124 void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
 125
 126 struct smi_settings *bcm2835_smi_get_settings_from_regs(
 127         struct bcm2835_smi_instance *inst);
 128
 129 void bcm2835_smi_write_buf(
 130         struct bcm2835_smi_instance *inst,
 131         const void *buf,
 132         size_t n_bytes);
 133
 134 void bcm2835_smi_read_buf(
 135         struct bcm2835_smi_instance *inst,
 136         void *buf,
 137         size_t n_bytes);
 138
 139 void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
 140         unsigned int address);
 141
 142 ssize_t bcm2835_smi_user_dma(
 143         struct bcm2835_smi_instance *inst,
 144         enum dma_transfer_direction dma_dir,
 145         char __user *user_ptr,
 146         size_t count,
 147         struct bcm2835_smi_bounce_info **bounce);
 148
 149 struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
 150
 151 #endif /* __KERNEL__ */
 152
 153 /****************************************************************
 154 *
 155 *       Implementation-only declarations
 156 *
 157 ****************************************************************/
 158
 159 #ifdef BCM2835_SMI_IMPLEMENTATION
 160
 161 /* Clock manager registers for SMI clock: */
 162 #define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
 163 /* Clock manager "password" to protect registers from spurious writes */
 164 #define CM_PWD (0x5a << 24)
 165
 166 #define CM_SMI_CTL      0x00
 167 #define CM_SMI_DIV      0x04
 168
 169 #define CM_SMI_CTL_FLIP (1 << 8)
 170 #define CM_SMI_CTL_BUSY (1 << 7)
 171 #define CM_SMI_CTL_KILL (1 << 5)
 172 #define CM_SMI_CTL_ENAB (1 << 4)
 173 #define CM_SMI_CTL_SRC_MASK (0xf)
 174 #define CM_SMI_CTL_SRC_OFFS (0)
 175
 176 #define CM_SMI_DIV_DIVI_MASK (0xf <<  12)
 177 #define CM_SMI_DIV_DIVI_OFFS (12)
 178 #define CM_SMI_DIV_DIVF_MASK (0xff << 4)
 179 #define CM_SMI_DIV_DIVF_OFFS (4)
 180
 181 /* SMI register mapping:*/
 182 #define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
 183
 184 #define SMICS   0x00    /* control + status register            */
 185 #define SMIL    0x04    /* length/count (n external txfers)     */
 186 #define SMIA    0x08    /* address register                     */
 187 #define SMID    0x0c    /* data register                        */
 188 #define SMIDSR0 0x10    /* device 0 read settings               */
 189 #define SMIDSW0 0x14    /* device 0 write settings              */
 190 #define SMIDSR1 0x18    /* device 1 read settings               */
 191 #define SMIDSW1 0x1c    /* device 1 write settings              */
 192 #define SMIDSR2 0x20    /* device 2 read settings               */
 193 #define SMIDSW2 0x24    /* device 2 write settings              */
 194 #define SMIDSR3 0x28    /* device 3 read settings               */
 195 #define SMIDSW3 0x2c    /* device 3 write settings              */
 196 #define SMIDC   0x30    /* DMA control registers                */
 197 #define SMIDCS  0x34    /* direct control/status register       */
 198 #define SMIDA   0x38    /* direct address register              */
 199 #define SMIDD   0x3c    /* direct data registers                */
 200 #define SMIFD   0x40    /* FIFO debug register                  */
 201
 202
 203
 204 /* Control and Status register bits:
 205  * SMICS_RXF    : RX fifo full: 1 when RX fifo is full
 206  * SMICS_TXE    : TX fifo empty: 1 when empty.
 207  * SMICS_RXD    : RX fifo contains data: 1 when there is data.
 208  * SMICS_TXD    : TX fifo can accept data: 1 when true.
 209  * SMICS_RXR    : RX fifo needs reading: 1 when fifo more than 3/4 full, or
 210  *                when "DONE" and fifo not emptied.
 211  * SMICS_TXW    : TX fifo needs writing: 1 when less than 1/4 full.
 212  * SMICS_AFERR  : AXI FIFO error: 1 when fifo read when empty or written
 213  *                when full. Write 1 to clear.
 214  * SMICS_EDREQ  : 1 when external DREQ received.
 215  * SMICS_PXLDAT :  Pixel data:  write 1 to enable pixel transfer modes.
 216  * SMICS_SETERR : 1 if there was an error writing to setup regs (e.g.
 217  *                tx was in progress). Write 1 to clear.
 218  * SMICS_PVMODE : Set to 1 to enable pixel valve mode.
 219  * SMICS_INTR   : Set to 1 to enable interrupt on RX.
 220  * SMICS_INTT   : Set to 1 to enable interrupt on TX.
 221  * SMICS_INTD   : Set to 1 to enable interrupt on DONE condition.
 222  * SMICS_TEEN   : Tear effect mode enabled: Programmed transfers will wait
 223  *                for a TE trigger before writing.
 224  * SMICS_PAD1   : Padding settings for external transfers. For writes: the
 225  *                number of bytes initially written to  the TX fifo that
 226  * SMICS_PAD0   : should be ignored. For reads: the number of bytes that will
 227  *                be read before the data, and should be dropped.
 228  * SMICS_WRITE  : Transfer direction: 1 = write to external device, 0 = read
 229  * SMICS_CLEAR  : Write 1 to clear the FIFOs.
 230  * SMICS_START  : Write 1 to start the programmed transfer.
 231  * SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway.
 232  * SMICS_DONE   : Reads as 1 when transfer finished. For RX, not set until
 233  *                FIFO emptied.
 234  * SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable.
 235  */
 236
 237 #define SMICS_RXF       (1 << 31)
 238 #define SMICS_TXE       (1 << 30)
 239 #define SMICS_RXD       (1 << 29)
 240 #define SMICS_TXD       (1 << 28)
 241 #define SMICS_RXR       (1 << 27)
 242 #define SMICS_TXW       (1 << 26)
 243 #define SMICS_AFERR     (1 << 25)
 244 #define SMICS_EDREQ     (1 << 15)
 245 #define SMICS_PXLDAT    (1 << 14)
 246 #define SMICS_SETERR    (1 << 13)
 247 #define SMICS_PVMODE    (1 << 12)
 248 #define SMICS_INTR      (1 << 11)
 249 #define SMICS_INTT      (1 << 10)
 250 #define SMICS_INTD      (1 << 9)
 251 #define SMICS_TEEN      (1 << 8)
 252 #define SMICS_PAD1      (1 << 7)
 253 #define SMICS_PAD0      (1 << 6)
 254 #define SMICS_WRITE     (1 << 5)
 255 #define SMICS_CLEAR     (1 << 4)
 256 #define SMICS_START     (1 << 3)
 257 #define SMICS_ACTIVE    (1 << 2)
 258 #define SMICS_DONE      (1 << 1)
 259 #define SMICS_ENABLE    (1 << 0)
 260
 261 /* Address register bits: */
 262
 263 #define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
 264 #define SMIA_DEVICE_OFFS (8)
 265 #define SMIA_ADDR_MASK (0x3f)   /* bits 5 -> 0 */
 266 #define SMIA_ADDR_OFFS (0)
 267
 268 /* DMA control register bits:
 269  * SMIDC_DMAEN  : DMA enable: set 1: DMA requests will be issued.
 270  * SMIDC_DMAP   : DMA passthrough: when set to 0, top two data pins are used by
 271  *                SMI as usual. When set to 1, the top two pins are used for
 272  *                external DREQs: pin 16 read request, 17 write.
 273  * SMIDC_PANIC* : Threshold at which DMA will panic during read/write.
 274  * SMIDC_REQ*   : Threshold at which DMA will generate a DREQ.
 275  */
 276
 277 #define SMIDC_DMAEN             (1 << 28)
 278 #define SMIDC_DMAP              (1 << 24)
 279 #define SMIDC_PANICR_MASK       (0x3f << 18)
 280 #define SMIDC_PANICR_OFFS       (18)
 281 #define SMIDC_PANICW_MASK       (0x3f << 12)
 282 #define SMIDC_PANICW_OFFS       (12)
 283 #define SMIDC_REQR_MASK         (0x3f << 6)
 284 #define SMIDC_REQR_OFFS         (6)
 285 #define SMIDC_REQW_MASK         (0x3f)
 286 #define SMIDC_REQW_OFFS         (0)
 287
 288 /* Device settings register bits: same for all 4 (or 3?) device register sets.
 289  * Device read settings:
 290  * SMIDSR_RWIDTH        : Read transfer width. 00 = 8bit, 01 = 16bit,
 291  *                        10 = 18bit, 11 = 9bit.
 292  * SMIDSR_RSETUP        : Read setup time: number of core cycles between chip
 293  *                        select/address and read strobe. Min 1, max 64.
 294  * SMIDSR_MODE68        : 1 for System 68 mode (i.e. enable + direction pins,
 295  *                        rather than OE + WE pin)
 296  * SMIDSR_FSETUP        : If set to 1, setup time only applies to first
 297  *                        transfer after address change.
 298  * SMIDSR_RHOLD         : Number of core cycles between read strobe going
 299  *                        inactive and CS/address going inactive. Min 1, max 64
 300  * SMIDSR_RPACEALL      : When set to 1, this device's RPACE value will always
 301  *                        be used for the next transaction, even if it is not
 302  *                        to this device.
 303  * SMIDSR_RPACE         : Number of core cycles spent waiting between CS
 304  *                        deassert and start of next transfer. Min 1, max 128
 305  * SMIDSR_RDREQ         : 1 = use external DMA request on SD16 to pace reads
 306  *                        from device. Must also set DMAP in SMICS.
 307  * SMIDSR_RSTROBE       : Number of cycles to assert the read strobe.
 308  *                        min 1, max 128.
 309  */
 310 #define SMIDSR_RWIDTH_MASK      ((1<<31)|(1<<30))
 311 #define SMIDSR_RWIDTH_OFFS      (30)
 312 #define SMIDSR_RSETUP_MASK      (0x3f << 24)
 313 #define SMIDSR_RSETUP_OFFS      (24)
 314 #define SMIDSR_MODE68           (1 << 23)
 315 #define SMIDSR_FSETUP           (1 << 22)
 316 #define SMIDSR_RHOLD_MASK       (0x3f << 16)
 317 #define SMIDSR_RHOLD_OFFS       (16)
 318 #define SMIDSR_RPACEALL         (1 << 15)
 319 #define SMIDSR_RPACE_MASK       (0x7f << 8)
 320 #define SMIDSR_RPACE_OFFS       (8)
 321 #define SMIDSR_RDREQ            (1 << 7)
 322 #define SMIDSR_RSTROBE_MASK     (0x7f)
 323 #define SMIDSR_RSTROBE_OFFS     (0)
 324
 325 /* Device write settings:
 326  * SMIDSW_WWIDTH        : Write transfer width. 00 = 8bit, 01 = 16bit,
 327  *                        10= 18bit, 11 = 9bit.
 328  * SMIDSW_WSETUP        : Number of cycles between CS assert and write strobe.
 329  *                        Min 1, max 64.
 330  * SMIDSW_WFORMAT       : Pixel format of input. 0 = 16bit RGB 565,
 331  *                        1 = 32bit RGBA 8888
 332  * SMIDSW_WSWAP         : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
 333  * SMIDSW_WHOLD         : Time between WE deassert and CS deassert. 1 to 64
 334  * SMIDSW_WPACEALL      : 1: this device's WPACE will be used for the next
 335  *                        transfer, regardless of that transfer's device.
 336  * SMIDSW_WPACE         : Cycles between CS deassert and next CS assert.
 337  *                        Min 1, max 128
 338  * SMIDSW_WDREQ         : Use external DREQ on pin 17 to pace writes. DMAP must
 339  *                        be set in SMICS.
 340  * SMIDSW_WSTROBE       : Number of cycles to assert the write strobe.
 341  *                        Min 1, max 128
 342  */
 343 #define SMIDSW_WWIDTH_MASK       ((1<<31)|(1<<30))
 344 #define SMIDSW_WWIDTH_OFFS      (30)
 345 #define SMIDSW_WSETUP_MASK      (0x3f << 24)
 346 #define SMIDSW_WSETUP_OFFS      (24)
 347 #define SMIDSW_WFORMAT          (1 << 23)
 348 #define SMIDSW_WSWAP            (1 << 22)
 349 #define SMIDSW_WHOLD_MASK       (0x3f << 16)
 350 #define SMIDSW_WHOLD_OFFS       (16)
 351 #define SMIDSW_WPACEALL         (1 << 15)
 352 #define SMIDSW_WPACE_MASK       (0x7f << 8)
 353 #define SMIDSW_WPACE_OFFS       (8)
 354 #define SMIDSW_WDREQ            (1 << 7)
 355 #define SMIDSW_WSTROBE_MASK      (0x7f)
 356 #define SMIDSW_WSTROBE_OFFS      (0)
 357
 358 /* Direct transfer control + status register
 359  * SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read
 360  * SMIDCS_DONE  : 1 when a transfer has finished. Write 1 to clear.
 361  * SMIDCS_START : Write 1 to start a transfer, if one is not already underway.
 362  * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
 363  */
 364
 365 #define SMIDCS_WRITE            (1 << 3)
 366 #define SMIDCS_DONE             (1 << 2)
 367 #define SMIDCS_START            (1 << 1)
 368 #define SMIDCS_ENABLE           (1 << 0)
 369
 370 /* Direct transfer address register
 371  * SMIDA_DEVICE : Indicates which of the device settings banks should be used.
 372  * SMIDA_ADDR   : The value to be asserted on the address pins.
 373  */
 374
 375 #define SMIDA_DEVICE_MASK       ((1<<9)|(1<<8))
 376 #define SMIDA_DEVICE_OFFS       (8)
 377 #define SMIDA_ADDR_MASK         (0x3f)
 378 #define SMIDA_ADDR_OFFS         (0)
 379
 380 /* FIFO debug register
 381  * SMIFD_FLVL   : The high-tide mark of FIFO count during the most recent txfer
 382  * SMIFD_FCNT   : The current FIFO count.
 383  */
 384 #define SMIFD_FLVL_MASK         (0x3f << 8)
 385 #define SMIFD_FLVL_OFFS         (8)
 386 #define SMIFD_FCNT_MASK         (0x3f)
 387 #define SMIFD_FCNT_OFFS         (0)
 388
 389 #endif /* BCM2835_SMI_IMPLEMENTATION */
 390
 391 #endif /* BCM2835_SMI_H */