2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
14 #include <linux/clk.h>
16 #ifdef CONFIG_COMMON_CLK
19 * flags used across common struct clk. these flags should only affect the
20 * top-level framework. custom flags for dealing with hardware specifics
21 * belong in struct clk_foo
23 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
24 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
26 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
27 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
28 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
29 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
34 * struct clk_ops - Callback operations for hardware clocks; these are to
35 * be provided by the clock implementation, and will be called by drivers
36 * through the clk_* api.
38 * @prepare: Prepare the clock for enabling. This must not return until
39 * the clock is fully prepared, and it's safe to call clk_enable.
40 * This callback is intended to allow clock implementations to
41 * do any initialisation that may sleep. Called with
44 * @unprepare: Release the clock from its prepared state. This will typically
45 * undo any work done in the @prepare callback. Called with
48 * @enable: Enable the clock atomically. This must not return until the
49 * clock is generating a valid clock signal, usable by consumer
50 * devices. Called with enable_lock held. This function must not
53 * @disable: Disable the clock atomically. Called with enable_lock held.
54 * This function must not sleep.
56 * @is_enabled: Queries the hardware to determine if the clock is enabled.
57 * This function must not sleep. Optional, if this op is not
58 * set then the enable count will be used.
60 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
61 * parent rate is an input parameter. It is up to the caller to
62 * ensure that the prepare_mutex is held across this call.
63 * Returns the calculated rate. Optional, but recommended - if
64 * this op is not set then clock rate will be initialized to 0.
66 * @round_rate: Given a target rate as input, returns the closest rate actually
67 * supported by the clock.
69 * @get_parent: Queries the hardware to determine the parent of a clock. The
70 * return value is a u8 which specifies the index corresponding to
71 * the parent clock. This index can be applied to either the
72 * .parent_names or .parents arrays. In short, this function
73 * translates the parent value read from hardware into an array
74 * index. Currently only called when the clock is initialized by
75 * __clk_init. This callback is mandatory for clocks with
76 * multiple parents. It is optional (and unnecessary) for clocks
77 * with 0 or 1 parents.
79 * @set_parent: Change the input source of this clock; for clocks with multiple
80 * possible parents specify a new parent by passing in the index
81 * as a u8 corresponding to the parent in either the .parent_names
82 * or .parents arrays. This function in affect translates an
83 * array index into the value programmed into the hardware.
84 * Returns 0 on success, -EERROR otherwise.
86 * @set_rate: Change the rate of this clock. The requested rate is specified
87 * by the second argument, which should typically be the return
88 * of .round_rate call. The third argument gives the parent rate
89 * which is likely helpful for most .set_rate implementation.
90 * Returns 0 on success, -EERROR otherwise.
92 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
93 * implementations to split any work between atomic (enable) and sleepable
94 * (prepare) contexts. If enabling a clock requires code that might sleep,
95 * this must be done in clk_prepare. Clock enable code that will never be
96 * called in a sleepable context may be implemented in clk_enable.
98 * Typically, drivers will call clk_prepare when a clock may be needed later
99 * (eg. when a device is opened), and clk_enable when the clock is actually
100 * required (eg. from an interrupt). Note that clk_prepare MUST have been
101 * called before clk_enable.
104 int (*prepare
)(struct clk_hw
*hw
);
105 void (*unprepare
)(struct clk_hw
*hw
);
106 int (*enable
)(struct clk_hw
*hw
);
107 void (*disable
)(struct clk_hw
*hw
);
108 int (*is_enabled
)(struct clk_hw
*hw
);
109 unsigned long (*recalc_rate
)(struct clk_hw
*hw
,
110 unsigned long parent_rate
);
111 long (*round_rate
)(struct clk_hw
*hw
, unsigned long,
113 int (*set_parent
)(struct clk_hw
*hw
, u8 index
);
114 u8 (*get_parent
)(struct clk_hw
*hw
);
115 int (*set_rate
)(struct clk_hw
*hw
, unsigned long,
117 void (*init
)(struct clk_hw
*hw
);
121 * struct clk_init_data - holds init data that's common to all clocks and is
122 * shared between the clock provider and the common clock framework.
125 * @ops: operations this clock supports
126 * @parent_names: array of string names for all possible parents
127 * @num_parents: number of possible parents
128 * @flags: framework-level hints and quirks
130 struct clk_init_data
{
132 const struct clk_ops
*ops
;
133 const char **parent_names
;
139 * struct clk_hw - handle for traversing from a struct clk to its corresponding
140 * hardware-specific structure. struct clk_hw should be declared within struct
141 * clk_foo and then referenced by the struct clk instance that uses struct
144 * @clk: pointer to the struct clk instance that points back to this struct
147 * @init: pointer to struct clk_init_data that contains the init data shared
148 * with the common clock framework.
152 const struct clk_init_data
*init
;
156 * DOC: Basic clock implementations common to many platforms
158 * Each basic clock hardware type is comprised of a structure describing the
159 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
160 * unique flags for that hardware type, a registration function and an
161 * alternative macro for static initialization
165 * struct clk_fixed_rate - fixed-rate clock
166 * @hw: handle between common and hardware-specific interfaces
167 * @fixed_rate: constant frequency of clock
169 struct clk_fixed_rate
{
171 unsigned long fixed_rate
;
175 extern const struct clk_ops clk_fixed_rate_ops
;
176 struct clk
*clk_register_fixed_rate(struct device
*dev
, const char *name
,
177 const char *parent_name
, unsigned long flags
,
178 unsigned long fixed_rate
);
180 void of_fixed_clk_setup(struct device_node
*np
);
183 * struct clk_gate - gating clock
185 * @hw: handle between common and hardware-specific interfaces
186 * @reg: register controlling gate
187 * @bit_idx: single bit controlling gate
188 * @flags: hardware-specific flags
189 * @lock: register lock
191 * Clock which can gate its output. Implements .enable & .disable
194 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
195 * enable the clock. Setting this flag does the opposite: setting the bit
196 * disable the clock and clearing it enables the clock
206 #define CLK_GATE_SET_TO_DISABLE BIT(0)
208 extern const struct clk_ops clk_gate_ops
;
209 struct clk
*clk_register_gate(struct device
*dev
, const char *name
,
210 const char *parent_name
, unsigned long flags
,
211 void __iomem
*reg
, u8 bit_idx
,
212 u8 clk_gate_flags
, spinlock_t
*lock
);
214 struct clk_div_table
{
220 * struct clk_divider - adjustable divider clock
222 * @hw: handle between common and hardware-specific interfaces
223 * @reg: register containing the divider
224 * @shift: shift to the divider bit field
225 * @width: width of the divider bit field
226 * @table: array of value/divider pairs, last entry should have div = 0
227 * @lock: register lock
229 * Clock with an adjustable divider affecting its output frequency. Implements
230 * .recalc_rate, .set_rate and .round_rate
233 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
234 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
235 * the raw value read from the register, with the value of zero considered
237 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
238 * the hardware register
246 const struct clk_div_table
*table
;
250 #define CLK_DIVIDER_ONE_BASED BIT(0)
251 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
253 extern const struct clk_ops clk_divider_ops
;
254 struct clk
*clk_register_divider(struct device
*dev
, const char *name
,
255 const char *parent_name
, unsigned long flags
,
256 void __iomem
*reg
, u8 shift
, u8 width
,
257 u8 clk_divider_flags
, spinlock_t
*lock
);
258 struct clk
*clk_register_divider_table(struct device
*dev
, const char *name
,
259 const char *parent_name
, unsigned long flags
,
260 void __iomem
*reg
, u8 shift
, u8 width
,
261 u8 clk_divider_flags
, const struct clk_div_table
*table
,
265 * struct clk_mux - multiplexer clock
267 * @hw: handle between common and hardware-specific interfaces
268 * @reg: register controlling multiplexer
269 * @shift: shift to multiplexer bit field
270 * @width: width of mutliplexer bit field
271 * @num_clks: number of parent clocks
272 * @lock: register lock
274 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
278 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
279 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
290 #define CLK_MUX_INDEX_ONE BIT(0)
291 #define CLK_MUX_INDEX_BIT BIT(1)
293 extern const struct clk_ops clk_mux_ops
;
294 struct clk
*clk_register_mux(struct device
*dev
, const char *name
,
295 const char **parent_names
, u8 num_parents
, unsigned long flags
,
296 void __iomem
*reg
, u8 shift
, u8 width
,
297 u8 clk_mux_flags
, spinlock_t
*lock
);
300 * struct clk_fixed_factor - fixed multiplier and divider clock
302 * @hw: handle between common and hardware-specific interfaces
306 * Clock with a fixed multiplier and divider. The output frequency is the
307 * parent clock rate divided by div and multiplied by mult.
308 * Implements .recalc_rate, .set_rate and .round_rate
311 struct clk_fixed_factor
{
317 extern struct clk_ops clk_fixed_factor_ops
;
318 struct clk
*clk_register_fixed_factor(struct device
*dev
, const char *name
,
319 const char *parent_name
, unsigned long flags
,
320 unsigned int mult
, unsigned int div
);
323 * clk_register - allocate a new clock, register it and return an opaque cookie
324 * @dev: device that is registering this clock
325 * @hw: link to hardware-specific clock data
327 * clk_register is the primary interface for populating the clock tree with new
328 * clock nodes. It returns a pointer to the newly allocated struct clk which
329 * cannot be dereferenced by driver code but may be used in conjuction with the
330 * rest of the clock API. In the event of an error clk_register will return an
331 * error code; drivers must test for an error code after calling clk_register.
333 struct clk
*clk_register(struct device
*dev
, struct clk_hw
*hw
);
335 void clk_unregister(struct clk
*clk
);
337 /* helper functions */
338 const char *__clk_get_name(struct clk
*clk
);
339 struct clk_hw
*__clk_get_hw(struct clk
*clk
);
340 u8
__clk_get_num_parents(struct clk
*clk
);
341 struct clk
*__clk_get_parent(struct clk
*clk
);
342 inline int __clk_get_enable_count(struct clk
*clk
);
343 inline int __clk_get_prepare_count(struct clk
*clk
);
344 unsigned long __clk_get_rate(struct clk
*clk
);
345 unsigned long __clk_get_flags(struct clk
*clk
);
346 int __clk_is_enabled(struct clk
*clk
);
347 struct clk
*__clk_lookup(const char *name
);
350 * FIXME clock api without lock protection
352 int __clk_prepare(struct clk
*clk
);
353 void __clk_unprepare(struct clk
*clk
);
354 void __clk_reparent(struct clk
*clk
, struct clk
*new_parent
);
355 unsigned long __clk_round_rate(struct clk
*clk
, unsigned long rate
);
359 typedef void (*of_clk_init_cb_t
)(struct device_node
*);
361 int of_clk_add_provider(struct device_node
*np
,
362 struct clk
*(*clk_src_get
)(struct of_phandle_args
*args
,
365 void of_clk_del_provider(struct device_node
*np
);
366 struct clk
*of_clk_src_simple_get(struct of_phandle_args
*clkspec
,
368 struct clk_onecell_data
{
370 unsigned int clk_num
;
372 struct clk
*of_clk_src_onecell_get(struct of_phandle_args
*clkspec
, void *data
);
373 const char *of_clk_get_parent_name(struct device_node
*np
, int index
);
374 void of_clk_init(const struct of_device_id
*matches
);
376 #endif /* CONFIG_COMMON_CLK */
377 #endif /* CLK_PROVIDER_H */