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1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
7 #ifndef _LINUX_CORESIGHT_PMU_H
8 #define _LINUX_CORESIGHT_PMU_H
10 #define CORESIGHT_ETM_PMU_NAME "cs_etm"
11 #define CORESIGHT_ETM_PMU_SEED 0x10
13 /* ETMv3.5/PTM's ETMCR config bit */
14 #define ETM_OPT_CYCACC 12
15 #define ETM_OPT_CTXTID 14
17 #define ETM_OPT_RETSTK 29
19 /* ETMv4 CONFIGR programming bits for the ETM OPTs */
20 #define ETM4_CFG_BIT_CYCACC 4
21 #define ETM4_CFG_BIT_CTXTID 6
22 #define ETM4_CFG_BIT_TS 11
23 #define ETM4_CFG_BIT_RETSTK 12
25 static inline int coresight_get_trace_id(int cpu
)
28 * A trace ID of value 0 is invalid, so let's start at some
29 * random value that fits in 7 bits and go from there. Since
30 * the common convention is to have data trace IDs be I(N) + 1,
31 * set instruction trace IDs as a function of the CPU number.
33 return (CORESIGHT_ETM_PMU_SEED
+ (cpu
* 2));