include/linux/cs5535.h

   1 /*
   2  * AMD CS5535/CS5536 definitions
   3  * Copyright (C) 2006  Advanced Micro Devices, Inc.
   4  * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #ifndef _CS5535_H
  12 #define _CS5535_H
  13
  14 /* MSRs */
  15 #define MSR_GLIU_P2D_RO0        0x10000029
  16
  17 #define MSR_LX_GLD_MSR_CONFIG   0x48002001
  18 #define MSR_LX_MSR_PADSEL       0x48002011      /* NOT 0x48000011; the data
  19                                                  * sheet has the wrong value */
  20 #define MSR_GLCP_SYS_RSTPLL     0x4C000014
  21 #define MSR_GLCP_DOTPLL         0x4C000015
  22
  23 #define MSR_LBAR_SMB            0x5140000B
  24 #define MSR_LBAR_GPIO           0x5140000C
  25 #define MSR_LBAR_MFGPT          0x5140000D
  26 #define MSR_LBAR_ACPI           0x5140000E
  27 #define MSR_LBAR_PMS            0x5140000F
  28
  29 #define MSR_DIVIL_SOFT_RESET    0x51400017
  30
  31 #define MSR_PIC_YSEL_LOW        0x51400020
  32 #define MSR_PIC_YSEL_HIGH       0x51400021
  33 #define MSR_PIC_ZSEL_LOW        0x51400022
  34 #define MSR_PIC_ZSEL_HIGH       0x51400023
  35 #define MSR_PIC_IRQM_LPC        0x51400025
  36
  37 #define MSR_MFGPT_IRQ           0x51400028
  38 #define MSR_MFGPT_NR            0x51400029
  39 #define MSR_MFGPT_SETUP         0x5140002B
  40
  41 #define MSR_LX_SPARE_MSR        0x80000011      /* DC-specific */
  42
  43 #define MSR_GX_GLD_MSR_CONFIG   0xC0002001
  44 #define MSR_GX_MSR_PADSEL       0xC0002011
  45
  46 /* PIC registers */
  47 #define CS5536_PIC_INT_SEL1     0x4d0
  48 #define CS5536_PIC_INT_SEL2     0x4d1
  49
  50 /* resource sizes */
  51 #define LBAR_GPIO_SIZE          0xFF
  52 #define LBAR_MFGPT_SIZE         0x40
  53 #define LBAR_ACPI_SIZE          0x40
  54 #define LBAR_PMS_SIZE           0x80
  55
  56 /*
  57  * PMC registers (PMS block)
  58  * It is only safe to access these registers as dword accesses.
  59  * See CS5536 Specification Update erratas 17 & 18
  60  */
  61 #define CS5536_PM_SCLK          0x10
  62 #define CS5536_PM_IN_SLPCTL     0x20
  63 #define CS5536_PM_WKXD          0x34
  64 #define CS5536_PM_WKD           0x30
  65 #define CS5536_PM_SSC           0x54
  66
  67 /*
  68  * PM registers (ACPI block)
  69  * It is only safe to access these registers as dword accesses.
  70  * See CS5536 Specification Update erratas 17 & 18
  71  */
  72 #define CS5536_PM1_STS          0x00
  73 #define CS5536_PM1_EN           0x02
  74 #define CS5536_PM1_CNT          0x08
  75 #define CS5536_PM_GPE0_STS      0x18
  76
  77 /* CS5536_PM1_STS bits */
  78 #define CS5536_WAK_FLAG         (1 << 15)
  79 #define CS5536_PWRBTN_FLAG      (1 << 8)
  80
  81 /* CS5536_PM1_EN bits */
  82 #define CS5536_PM_PWRBTN        (1 << 8)
  83
  84 /* VSA2 magic values */
  85 #define VSA_VRC_INDEX           0xAC1C
  86 #define VSA_VRC_DATA            0xAC1E
  87 #define VSA_VR_UNLOCK           0xFC53  /* unlock virtual register */
  88 #define VSA_VR_SIGNATURE        0x0003
  89 #define VSA_VR_MEM_SIZE         0x0200
  90 #define AMD_VSA_SIG             0x4132  /* signature is ascii 'VSA2' */
  91 #define GSW_VSA_SIG             0x534d  /* General Software signature */
  92
  93 #include <linux/io.h>
  94
  95 static inline int cs5535_has_vsa2(void)
  96 {
  97         static int has_vsa2 = -1;
  98
  99         if (has_vsa2 == -1) {
 100                 uint16_t val;
 101
 102                 /*
 103                  * The VSA has virtual registers that we can query for a
 104                  * signature.
 105                  */
 106                 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
 107                 outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
 108
 109                 val = inw(VSA_VRC_DATA);
 110                 has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
 111         }
 112
 113         return has_vsa2;
 114 }
 115
 116 /* GPIOs */
 117 #define GPIO_OUTPUT_VAL         0x00
 118 #define GPIO_OUTPUT_ENABLE      0x04
 119 #define GPIO_OUTPUT_OPEN_DRAIN  0x08
 120 #define GPIO_OUTPUT_INVERT      0x0C
 121 #define GPIO_OUTPUT_AUX1        0x10
 122 #define GPIO_OUTPUT_AUX2        0x14
 123 #define GPIO_PULL_UP            0x18
 124 #define GPIO_PULL_DOWN          0x1C
 125 #define GPIO_INPUT_ENABLE       0x20
 126 #define GPIO_INPUT_INVERT       0x24
 127 #define GPIO_INPUT_FILTER       0x28
 128 #define GPIO_INPUT_EVENT_COUNT  0x2C
 129 #define GPIO_READ_BACK          0x30
 130 #define GPIO_INPUT_AUX1         0x34
 131 #define GPIO_EVENTS_ENABLE      0x38
 132 #define GPIO_LOCK_ENABLE        0x3C
 133 #define GPIO_POSITIVE_EDGE_EN   0x40
 134 #define GPIO_NEGATIVE_EDGE_EN   0x44
 135 #define GPIO_POSITIVE_EDGE_STS  0x48
 136 #define GPIO_NEGATIVE_EDGE_STS  0x4C
 137
 138 #define GPIO_FLTR7_AMOUNT       0xD8
 139
 140 #define GPIO_MAP_X              0xE0
 141 #define GPIO_MAP_Y              0xE4
 142 #define GPIO_MAP_Z              0xE8
 143 #define GPIO_MAP_W              0xEC
 144
 145 #define GPIO_FE7_SEL            0xF7
 146
 147 void cs5535_gpio_set(unsigned offset, unsigned int reg);
 148 void cs5535_gpio_clear(unsigned offset, unsigned int reg);
 149 int cs5535_gpio_isset(unsigned offset, unsigned int reg);
 150 int cs5535_gpio_set_irq(unsigned group, unsigned irq);
 151 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
 152
 153 /* MFGPTs */
 154
 155 #define MFGPT_MAX_TIMERS        8
 156 #define MFGPT_TIMER_ANY         (-1)
 157
 158 #define MFGPT_DOMAIN_WORKING    1
 159 #define MFGPT_DOMAIN_STANDBY    2
 160 #define MFGPT_DOMAIN_ANY        (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
 161
 162 #define MFGPT_CMP1              0
 163 #define MFGPT_CMP2              1
 164
 165 #define MFGPT_EVENT_IRQ         0
 166 #define MFGPT_EVENT_NMI         1
 167 #define MFGPT_EVENT_RESET       3
 168
 169 #define MFGPT_REG_CMP1          0
 170 #define MFGPT_REG_CMP2          2
 171 #define MFGPT_REG_COUNTER       4
 172 #define MFGPT_REG_SETUP         6
 173
 174 #define MFGPT_SETUP_CNTEN       (1 << 15)
 175 #define MFGPT_SETUP_CMP2        (1 << 14)
 176 #define MFGPT_SETUP_CMP1        (1 << 13)
 177 #define MFGPT_SETUP_SETUP       (1 << 12)
 178 #define MFGPT_SETUP_STOPEN      (1 << 11)
 179 #define MFGPT_SETUP_EXTEN       (1 << 10)
 180 #define MFGPT_SETUP_REVEN       (1 << 5)
 181 #define MFGPT_SETUP_CLKSEL      (1 << 4)
 182
 183 struct cs5535_mfgpt_timer;
 184
 185 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
 186                 uint16_t reg);
 187 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
 188                 uint16_t value);
 189
 190 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
 191                 int event, int enable);
 192 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
 193                 int *irq, int enable);
 194 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
 195                 int domain);
 196 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
 197
 198 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
 199                 int cmp, int *irq)
 200 {
 201         return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
 202 }
 203
 204 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
 205                 int cmp, int *irq)
 206 {
 207         return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
 208 }
 209
 210 #endif