1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
5 #ifndef LINUX_DMAENGINE_H
6 #define LINUX_DMAENGINE_H
8 #include <linux/device.h>
10 #include <linux/uio.h>
11 #include <linux/bug.h>
12 #include <linux/scatterlist.h>
13 #include <linux/bitmap.h>
14 #include <linux/types.h>
18 * typedef dma_cookie_t - an opaque DMA cookie
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
22 typedef s32 dma_cookie_t
;
23 #define DMA_MIN_COOKIE 1
25 static inline int dma_submit_error(dma_cookie_t cookie
)
27 return cookie
< 0 ? cookie
: 0;
31 * enum dma_status - DMA transaction status
32 * @DMA_COMPLETE: transaction completed
33 * @DMA_IN_PROGRESS: transaction not yet processed
34 * @DMA_PAUSED: transaction is paused
35 * @DMA_ERROR: transaction failed
46 * enum dma_transaction_type - DMA transaction types/indexes
48 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
49 * automatically set as dma devices are registered.
51 enum dma_transaction_type
{
65 DMA_COMPLETION_NO_ORDER
,
68 /* last transaction type for creation of the capabilities mask */
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
74 * @DMA_MEM_TO_MEM: Async/Memcpy mode
75 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
76 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
77 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
79 enum dma_transfer_direction
{
88 * Interleaved Transfer Request
89 * ----------------------------
90 * A chunk is collection of contiguous bytes to be transferred.
91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
92 * ICGs may or may not change between chunks.
93 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
94 * that when repeated an integral number of times, specifies the transfer.
95 * A transfer template is specification of a Frame, the number of times
96 * it is to be repeated and other per-transfer attributes.
98 * Practically, a client driver would have ready a template for each
99 * type of transfer it is going to need during its lifetime and
100 * set only 'src_start' and 'dst_start' before submitting the requests.
103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
104 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
111 * struct data_chunk - Element of scatter-gather list that makes a frame.
112 * @size: Number of bytes to read from source.
113 * size_dst := fn(op, size_src), so doesn't mean much for destination.
114 * @icg: Number of bytes to jump after last src/dst address of this
115 * chunk and before first src/dst address for next chunk.
116 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
117 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
118 * @dst_icg: Number of bytes to jump after last dst address of this
119 * chunk and before the first dst address for next chunk.
120 * Ignored if dst_inc is true and dst_sgl is false.
121 * @src_icg: Number of bytes to jump after last src address of this
122 * chunk and before the first src address for next chunk.
123 * Ignored if src_inc is true and src_sgl is false.
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
135 * @src_start: Bus address of source for the first chunk.
136 * @dst_start: Bus address of destination for the first chunk.
137 * @dir: Specifies the type of Source and Destination.
138 * @src_inc: If the source address increments after reading from it.
139 * @dst_inc: If the destination address increments after writing to it.
140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
141 * Otherwise, source is read contiguously (icg ignored).
142 * Ignored if src_inc is false.
143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
144 * Otherwise, destination is filled contiguously (icg ignored).
145 * Ignored if dst_inc is false.
146 * @numf: Number of frames in this template.
147 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
148 * @sgl: Array of {chunk,icg} pairs that make up a frame.
150 struct dma_interleaved_template
{
151 dma_addr_t src_start
;
152 dma_addr_t dst_start
;
153 enum dma_transfer_direction dir
;
160 struct data_chunk sgl
[];
164 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
165 * control completion, and communicate status.
166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
169 * acknowledges receipt, i.e. has a chance to establish any dependency
171 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
172 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
173 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
174 * sources that were the result of a previous operation, in the case of a PQ
175 * operation it continues the calculation with new sources
176 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
177 * on the result of this operation
178 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
180 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
181 * data and the descriptor should be in different format from normal
183 * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
184 * repeated when it ends until a transaction is issued on the same channel
185 * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
186 * interleaved transactions and is ignored for all other transaction types.
187 * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
188 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
189 * repeated transaction ends. Not setting this flag when the previously queued
190 * transaction is marked with DMA_PREP_REPEAT will cause the new transaction
191 * to never be processed and stay in the issued queue forever. The flag is
192 * ignored if the previous transaction is not a repeated transaction.
194 enum dma_ctrl_flags
{
195 DMA_PREP_INTERRUPT
= (1 << 0),
196 DMA_CTRL_ACK
= (1 << 1),
197 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
198 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
199 DMA_PREP_CONTINUE
= (1 << 4),
200 DMA_PREP_FENCE
= (1 << 5),
201 DMA_CTRL_REUSE
= (1 << 6),
202 DMA_PREP_CMD
= (1 << 7),
203 DMA_PREP_REPEAT
= (1 << 8),
204 DMA_PREP_LOAD_EOT
= (1 << 9),
208 * enum sum_check_bits - bit position of pq_check_flags
210 enum sum_check_bits
{
216 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
217 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
218 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
220 enum sum_check_flags
{
221 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
222 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
227 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
228 * See linux/cpumask.h
230 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
233 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
234 * @memcpy_count: transaction counter
235 * @bytes_transferred: byte counter
239 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
240 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
241 * client driver and it is attached (via the dmaengine_desc_attach_metadata()
242 * helper) to the descriptor.
244 * Client drivers interested to use this mode can follow:
245 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
246 * 1. prepare the descriptor (dmaengine_prep_*)
247 * construct the metadata in the client's buffer
248 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
250 * 3. submit the transfer
252 * 1. prepare the descriptor (dmaengine_prep_*)
253 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
255 * 3. submit the transfer
256 * 4. when the transfer is completed, the metadata should be available in the
259 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
260 * driver. The client driver can ask for the pointer, maximum size and the
261 * currently used size of the metadata and can directly update or read it.
262 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
263 * provided as helper functions.
265 * Note: the metadata area for the descriptor is no longer valid after the
266 * transfer has been completed (valid up to the point when the completion
267 * callback returns if used).
269 * Client drivers interested to use this mode can follow:
270 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
271 * 1. prepare the descriptor (dmaengine_prep_*)
272 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
274 * 3. update the metadata at the pointer
275 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount
276 * of data the client has placed into the metadata buffer
277 * 5. submit the transfer
279 * 1. prepare the descriptor (dmaengine_prep_*)
280 * 2. submit the transfer
281 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
282 * pointer to the engine's metadata area
283 * 4. Read out the metadata from the pointer
285 * Note: the two mode is not compatible and clients must use one mode for a
288 enum dma_desc_metadata_mode
{
289 DESC_METADATA_NONE
= 0,
290 DESC_METADATA_CLIENT
= BIT(0),
291 DESC_METADATA_ENGINE
= BIT(1),
294 struct dma_chan_percpu
{
296 unsigned long memcpy_count
;
297 unsigned long bytes_transferred
;
301 * struct dma_router - DMA router structure
302 * @dev: pointer to the DMA router device
303 * @route_free: function to be called when the route can be disconnected
307 void (*route_free
)(struct device
*dev
, void *route_data
);
311 * struct dma_chan - devices supply DMA channels, clients use them
312 * @device: ptr to the dma device who supplies this channel, always !%NULL
313 * @slave: ptr to the device using this channel
314 * @cookie: last cookie value returned to client
315 * @completed_cookie: last completed cookie for this channel
316 * @chan_id: channel ID for sysfs
317 * @dev: class device for sysfs
318 * @name: backlink name for sysfs
319 * @dbg_client_name: slave name for debugfs in format:
320 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
321 * @device_node: used to add this to the device chan list
322 * @local: per-cpu pointer to a struct dma_chan_percpu
323 * @client_count: how many clients are using this channel
324 * @table_count: number of appearances in the mem-to-mem allocation table
325 * @router: pointer to the DMA router structure
326 * @route_data: channel specific data for the router
327 * @private: private data for certain client-channel associations
330 struct dma_device
*device
;
331 struct device
*slave
;
333 dma_cookie_t completed_cookie
;
337 struct dma_chan_dev
*dev
;
339 #ifdef CONFIG_DEBUG_FS
340 char *dbg_client_name
;
343 struct list_head device_node
;
344 struct dma_chan_percpu __percpu
*local
;
349 struct dma_router
*router
;
356 * struct dma_chan_dev - relate sysfs device node to backing channel device
357 * @chan: driver channel device
358 * @device: sysfs device
359 * @dev_id: parent dma_device dev_id
361 struct dma_chan_dev
{
362 struct dma_chan
*chan
;
363 struct device device
;
368 * enum dma_slave_buswidth - defines bus width of the DMA slave
369 * device, source or target buses
371 enum dma_slave_buswidth
{
372 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
373 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
374 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
375 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
376 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
377 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
378 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
379 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
380 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
384 * struct dma_slave_config - dma slave channel runtime config
385 * @direction: whether the data shall go in or out on this slave
386 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
387 * legal values. DEPRECATED, drivers should use the direction argument
388 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
389 * the dir field in the dma_interleaved_template structure.
390 * @src_addr: this is the physical address where DMA slave data
391 * should be read (RX), if the source is memory this argument is
393 * @dst_addr: this is the physical address where DMA slave data
394 * should be written (TX), if the source is memory this argument
396 * @src_addr_width: this is the width in bytes of the source (RX)
397 * register where DMA data shall be read. If the source
398 * is memory this may be ignored depending on architecture.
399 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
400 * @dst_addr_width: same as src_addr_width but for destination
401 * target (TX) mutatis mutandis.
402 * @src_maxburst: the maximum number of words (note: words, as in
403 * units of the src_addr_width member, not bytes) that can be sent
404 * in one burst to the device. Typically something like half the
405 * FIFO depth on I/O peripherals so you don't overflow it. This
406 * may or may not be applicable on memory sources.
407 * @dst_maxburst: same as src_maxburst but for destination target
409 * @src_port_window_size: The length of the register area in words the data need
410 * to be accessed on the device side. It is only used for devices which is using
411 * an area instead of a single register to receive the data. Typically the DMA
412 * loops in this area in order to transfer the data.
413 * @dst_port_window_size: same as src_port_window_size but for the destination
415 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
416 * with 'true' if peripheral should be flow controller. Direction will be
417 * selected at Runtime.
418 * @slave_id: Slave requester id. Only valid for slave channels. The dma
419 * slave peripheral will have unique id as dma requester which need to be
420 * pass as slave config.
422 * This struct is passed in as configuration data to a DMA engine
423 * in order to set up a certain channel for DMA transport at runtime.
424 * The DMA device/engine has to provide support for an additional
425 * callback in the dma_device structure, device_config and this struct
426 * will then be passed in as an argument to the function.
428 * The rationale for adding configuration information to this struct is as
429 * follows: if it is likely that more than one DMA slave controllers in
430 * the world will support the configuration option, then make it generic.
431 * If not: if it is fixed so that it be sent in static from the platform
432 * data, then prefer to do that.
434 struct dma_slave_config
{
435 enum dma_transfer_direction direction
;
436 phys_addr_t src_addr
;
437 phys_addr_t dst_addr
;
438 enum dma_slave_buswidth src_addr_width
;
439 enum dma_slave_buswidth dst_addr_width
;
442 u32 src_port_window_size
;
443 u32 dst_port_window_size
;
445 unsigned int slave_id
;
449 * enum dma_residue_granularity - Granularity of the reported transfer residue
450 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
451 * DMA channel is only able to tell whether a descriptor has been completed or
452 * not, which means residue reporting is not supported by this channel. The
453 * residue field of the dma_tx_state field will always be 0.
454 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
455 * completed segment of the transfer (For cyclic transfers this is after each
456 * period). This is typically implemented by having the hardware generate an
457 * interrupt after each transferred segment and then the drivers updates the
458 * outstanding residue by the size of the segment. Another possibility is if
459 * the hardware supports scatter-gather and the segment descriptor has a field
460 * which gets set after the segment has been completed. The driver then counts
461 * the number of segments without the flag set to compute the residue.
462 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
463 * burst. This is typically only supported if the hardware has a progress
464 * register of some sort (E.g. a register with the current read/write address
465 * or a register with the amount of bursts/beats/bytes that have been
466 * transferred or still need to be transferred).
468 enum dma_residue_granularity
{
469 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
470 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
471 DMA_RESIDUE_GRANULARITY_BURST
= 2,
475 * struct dma_slave_caps - expose capabilities of a slave channel only
476 * @src_addr_widths: bit mask of src addr widths the channel supports.
477 * Width is specified in bytes, e.g. for a channel supporting
478 * a width of 4 the mask should have BIT(4) set.
479 * @dst_addr_widths: bit mask of dst addr widths the channel supports
480 * @directions: bit mask of slave directions the channel supports.
481 * Since the enum dma_transfer_direction is not defined as bit flag for
482 * each type, the dma controller should set BIT(<TYPE>) and same
483 * should be checked by controller as well
484 * @min_burst: min burst capability per-transfer
485 * @max_burst: max burst capability per-transfer
486 * @max_sg_burst: max number of SG list entries executed in a single burst
487 * DMA tansaction with no software intervention for reinitialization.
488 * Zero value means unlimited number of entries.
489 * @cmd_pause: true, if pause is supported (i.e. for reading residue or
491 * @cmd_resume: true, if resume is supported
492 * @cmd_terminate: true, if terminate cmd is supported
493 * @residue_granularity: granularity of the reported transfer residue
494 * @descriptor_reuse: if a descriptor can be reused by client and
495 * resubmitted multiple times
497 struct dma_slave_caps
{
507 enum dma_residue_granularity residue_granularity
;
508 bool descriptor_reuse
;
511 static inline const char *dma_chan_name(struct dma_chan
*chan
)
513 return dev_name(&chan
->dev
->device
);
516 void dma_chan_cleanup(struct kref
*kref
);
519 * typedef dma_filter_fn - callback filter for dma_request_channel
520 * @chan: channel to be reviewed
521 * @filter_param: opaque parameter passed through dma_request_channel
523 * When this optional parameter is specified in a call to dma_request_channel a
524 * suitable channel is passed to this routine for further dispositioning before
525 * being returned. Where 'suitable' indicates a non-busy channel that
526 * satisfies the given capability mask. It returns 'true' to indicate that the
527 * channel is suitable.
529 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
531 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
533 enum dmaengine_tx_result
{
534 DMA_TRANS_NOERROR
= 0, /* SUCCESS */
535 DMA_TRANS_READ_FAILED
, /* Source DMA read failed */
536 DMA_TRANS_WRITE_FAILED
, /* Destination DMA write failed */
537 DMA_TRANS_ABORTED
, /* Op never submitted / aborted */
540 struct dmaengine_result
{
541 enum dmaengine_tx_result result
;
545 typedef void (*dma_async_tx_callback_result
)(void *dma_async_param
,
546 const struct dmaengine_result
*result
);
548 struct dmaengine_unmap_data
{
549 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
563 struct dma_async_tx_descriptor
;
565 struct dma_descriptor_metadata_ops
{
566 int (*attach
)(struct dma_async_tx_descriptor
*desc
, void *data
,
569 void *(*get_ptr
)(struct dma_async_tx_descriptor
*desc
,
570 size_t *payload_len
, size_t *max_len
);
571 int (*set_len
)(struct dma_async_tx_descriptor
*desc
,
576 * struct dma_async_tx_descriptor - async transaction descriptor
577 * ---dma generic offload fields---
578 * @cookie: tracking cookie for this transaction, set to -EBUSY if
579 * this tx is sitting on a dependency list
580 * @flags: flags to augment operation preparation, control completion, and
582 * @phys: physical address of the descriptor
583 * @chan: target channel for this operation
584 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
585 * descriptor pending. To be pushed on .issue_pending() call
586 * @callback: routine to call after this operation is complete
587 * @callback_param: general parameter to pass to the callback routine
588 * @desc_metadata_mode: core managed metadata mode to protect mixed use of
589 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
591 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
592 * DMA driver if metadata mode is supported with the descriptor
593 * ---async_tx api specific fields---
594 * @next: at completion submit this descriptor
595 * @parent: pointer to the next level up in the dependency chain
596 * @lock: protect the parent and next pointers
598 struct dma_async_tx_descriptor
{
600 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
602 struct dma_chan
*chan
;
603 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
604 int (*desc_free
)(struct dma_async_tx_descriptor
*tx
);
605 dma_async_tx_callback callback
;
606 dma_async_tx_callback_result callback_result
;
607 void *callback_param
;
608 struct dmaengine_unmap_data
*unmap
;
609 enum dma_desc_metadata_mode desc_metadata_mode
;
610 struct dma_descriptor_metadata_ops
*metadata_ops
;
611 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
612 struct dma_async_tx_descriptor
*next
;
613 struct dma_async_tx_descriptor
*parent
;
618 #ifdef CONFIG_DMA_ENGINE
619 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
620 struct dmaengine_unmap_data
*unmap
)
622 kref_get(&unmap
->kref
);
626 struct dmaengine_unmap_data
*
627 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
628 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
630 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
631 struct dmaengine_unmap_data
*unmap
)
634 static inline struct dmaengine_unmap_data
*
635 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
639 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
644 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
649 dmaengine_unmap_put(tx
->unmap
);
653 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
654 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
657 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
660 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
664 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
667 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
670 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
674 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
680 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
682 spin_lock_bh(&txd
->lock
);
684 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
686 spin_unlock_bh(&txd
->lock
);
688 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
693 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
697 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
701 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
705 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
712 * struct dma_tx_state - filled in to report the status of
714 * @last: last completed DMA cookie
715 * @used: last issued DMA cookie (i.e. the one in progress)
716 * @residue: the remaining number of bytes left to transmit
717 * on the selected transfer for states DMA_IN_PROGRESS and
718 * DMA_PAUSED if this is implemented in the driver, else 0
719 * @in_flight_bytes: amount of data in bytes cached by the DMA.
721 struct dma_tx_state
{
729 * enum dmaengine_alignment - defines alignment of the DMA async tx
732 enum dmaengine_alignment
{
733 DMAENGINE_ALIGN_1_BYTE
= 0,
734 DMAENGINE_ALIGN_2_BYTES
= 1,
735 DMAENGINE_ALIGN_4_BYTES
= 2,
736 DMAENGINE_ALIGN_8_BYTES
= 3,
737 DMAENGINE_ALIGN_16_BYTES
= 4,
738 DMAENGINE_ALIGN_32_BYTES
= 5,
739 DMAENGINE_ALIGN_64_BYTES
= 6,
743 * struct dma_slave_map - associates slave device and it's slave channel with
744 * parameter to be used by a filter function
745 * @devname: name of the device
746 * @slave: slave channel name
747 * @param: opaque parameter to pass to struct dma_filter.fn
749 struct dma_slave_map
{
756 * struct dma_filter - information for slave device/channel to filter_fn/param
758 * @fn: filter function callback
759 * @mapcnt: number of slave device/channel in the map
760 * @map: array of channel to filter mapping data
765 const struct dma_slave_map
*map
;
769 * struct dma_device - info on the entity supplying DMA services
770 * @chancnt: how many DMA channels are supported
771 * @privatecnt: how many DMA channels are requested by dma_request_channel
772 * @channels: the list of struct dma_chan
773 * @global_node: list_head for global dma_device_list
774 * @filter: information for device/slave to filter function/param mapping
775 * @cap_mask: one or more dma_capability flags
776 * @desc_metadata_modes: supported metadata modes by the DMA device
777 * @max_xor: maximum number of xor sources, 0 if no capability
778 * @max_pq: maximum number of PQ sources and PQ-continue capability
779 * @copy_align: alignment shift for memcpy operations
780 * @xor_align: alignment shift for xor operations
781 * @pq_align: alignment shift for pq operations
782 * @fill_align: alignment shift for memset operations
783 * @dev_id: unique device ID
784 * @dev: struct device reference for dma mapping api
785 * @owner: owner module (automatically set based on the provided dev)
786 * @src_addr_widths: bit mask of src addr widths the device supports
787 * Width is specified in bytes, e.g. for a device supporting
788 * a width of 4 the mask should have BIT(4) set.
789 * @dst_addr_widths: bit mask of dst addr widths the device supports
790 * @directions: bit mask of slave directions the device supports.
791 * Since the enum dma_transfer_direction is not defined as bit flag for
792 * each type, the dma controller should set BIT(<TYPE>) and same
793 * should be checked by controller as well
794 * @min_burst: min burst capability per-transfer
795 * @max_burst: max burst capability per-transfer
796 * @max_sg_burst: max number of SG list entries executed in a single burst
797 * DMA tansaction with no software intervention for reinitialization.
798 * Zero value means unlimited number of entries.
799 * @residue_granularity: granularity of the transfer residue reported
801 * @device_alloc_chan_resources: allocate resources and return the
802 * number of allocated descriptors
803 * @device_free_chan_resources: release DMA channel's resources
804 * @device_prep_dma_memcpy: prepares a memcpy operation
805 * @device_prep_dma_xor: prepares a xor operation
806 * @device_prep_dma_xor_val: prepares a xor validation operation
807 * @device_prep_dma_pq: prepares a pq operation
808 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
809 * @device_prep_dma_memset: prepares a memset operation
810 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
811 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
812 * @device_prep_slave_sg: prepares a slave dma operation
813 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
814 * The function takes a buffer of size buf_len. The callback function will
815 * be called after period_len bytes have been transferred.
816 * @device_prep_interleaved_dma: Transfer expression in a generic way.
817 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
818 * @device_caps: May be used to override the generic DMA slave capabilities
819 * with per-channel specific ones
820 * @device_config: Pushes a new configuration to a channel, return 0 or an error
822 * @device_pause: Pauses any transfer happening on a channel. Returns
824 * @device_resume: Resumes any transfer on a channel previously
825 * paused. Returns 0 or an error code
826 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
828 * @device_synchronize: Synchronizes the termination of a transfers to the
830 * @device_tx_status: poll for transaction completion, the optional
831 * txstate parameter can be supplied with a pointer to get a
832 * struct with auxiliary transfer status information, otherwise the call
833 * will just return a simple status code
834 * @device_issue_pending: push pending transactions to hardware
835 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
836 * @device_release: called sometime atfer dma_async_device_unregister() is
837 * called and there are no further references to this structure. This
838 * must be implemented to free resources however many existing drivers
839 * do not and are therefore not safe to unbind while in use.
840 * @dbg_summary_show: optional routine to show contents in debugfs; default code
841 * will be used when this is omitted, but custom code can show extra,
842 * controller specific information.
846 unsigned int chancnt
;
847 unsigned int privatecnt
;
848 struct list_head channels
;
849 struct list_head global_node
;
850 struct dma_filter filter
;
851 dma_cap_mask_t cap_mask
;
852 enum dma_desc_metadata_mode desc_metadata_modes
;
853 unsigned short max_xor
;
854 unsigned short max_pq
;
855 enum dmaengine_alignment copy_align
;
856 enum dmaengine_alignment xor_align
;
857 enum dmaengine_alignment pq_align
;
858 enum dmaengine_alignment fill_align
;
859 #define DMA_HAS_PQ_CONTINUE (1 << 15)
863 struct module
*owner
;
865 struct mutex chan_mutex
; /* to protect chan_ida */
873 bool descriptor_reuse
;
874 enum dma_residue_granularity residue_granularity
;
876 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
877 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
879 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
880 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
881 size_t len
, unsigned long flags
);
882 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
883 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
884 unsigned int src_cnt
, size_t len
, unsigned long flags
);
885 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
886 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
887 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
888 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
889 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
890 unsigned int src_cnt
, const unsigned char *scf
,
891 size_t len
, unsigned long flags
);
892 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
893 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
894 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
895 enum sum_check_flags
*pqres
, unsigned long flags
);
896 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
897 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
898 unsigned long flags
);
899 struct dma_async_tx_descriptor
*(*device_prep_dma_memset_sg
)(
900 struct dma_chan
*chan
, struct scatterlist
*sg
,
901 unsigned int nents
, int value
, unsigned long flags
);
902 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
903 struct dma_chan
*chan
, unsigned long flags
);
905 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
906 struct dma_chan
*chan
, struct scatterlist
*sgl
,
907 unsigned int sg_len
, enum dma_transfer_direction direction
,
908 unsigned long flags
, void *context
);
909 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
910 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
911 size_t period_len
, enum dma_transfer_direction direction
,
912 unsigned long flags
);
913 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
914 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
915 unsigned long flags
);
916 struct dma_async_tx_descriptor
*(*device_prep_dma_imm_data
)(
917 struct dma_chan
*chan
, dma_addr_t dst
, u64 data
,
918 unsigned long flags
);
920 void (*device_caps
)(struct dma_chan
*chan
,
921 struct dma_slave_caps
*caps
);
922 int (*device_config
)(struct dma_chan
*chan
,
923 struct dma_slave_config
*config
);
924 int (*device_pause
)(struct dma_chan
*chan
);
925 int (*device_resume
)(struct dma_chan
*chan
);
926 int (*device_terminate_all
)(struct dma_chan
*chan
);
927 void (*device_synchronize
)(struct dma_chan
*chan
);
929 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
931 struct dma_tx_state
*txstate
);
932 void (*device_issue_pending
)(struct dma_chan
*chan
);
933 void (*device_release
)(struct dma_device
*dev
);
934 /* debugfs support */
935 #ifdef CONFIG_DEBUG_FS
936 void (*dbg_summary_show
)(struct seq_file
*s
, struct dma_device
*dev
);
937 struct dentry
*dbg_dev_root
;
941 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
942 struct dma_slave_config
*config
)
944 if (chan
->device
->device_config
)
945 return chan
->device
->device_config(chan
, config
);
950 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
952 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
955 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
956 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
957 enum dma_transfer_direction dir
, unsigned long flags
)
959 struct scatterlist sg
;
960 sg_init_table(&sg
, 1);
961 sg_dma_address(&sg
) = buf
;
962 sg_dma_len(&sg
) = len
;
964 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
967 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
971 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
972 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
973 enum dma_transfer_direction dir
, unsigned long flags
)
975 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
978 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
982 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
984 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
985 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
986 enum dma_transfer_direction dir
, unsigned long flags
,
987 struct rio_dma_ext
*rio_ext
)
989 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
992 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
993 dir
, flags
, rio_ext
);
997 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
998 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
999 size_t period_len
, enum dma_transfer_direction dir
,
1000 unsigned long flags
)
1002 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_cyclic
)
1005 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
1006 period_len
, dir
, flags
);
1009 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
1010 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
1011 unsigned long flags
)
1013 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_interleaved_dma
)
1015 if (flags
& DMA_PREP_REPEAT
&&
1016 !test_bit(DMA_REPEAT
, chan
->device
->cap_mask
.bits
))
1019 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
1022 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memset(
1023 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
1024 unsigned long flags
)
1026 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_memset
)
1029 return chan
->device
->device_prep_dma_memset(chan
, dest
, value
,
1033 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memcpy(
1034 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1035 size_t len
, unsigned long flags
)
1037 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_memcpy
)
1040 return chan
->device
->device_prep_dma_memcpy(chan
, dest
, src
,
1044 static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan
*chan
,
1045 enum dma_desc_metadata_mode mode
)
1050 return !!(chan
->device
->desc_metadata_modes
& mode
);
1053 #ifdef CONFIG_DMA_ENGINE
1054 int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor
*desc
,
1055 void *data
, size_t len
);
1056 void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor
*desc
,
1057 size_t *payload_len
, size_t *max_len
);
1058 int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor
*desc
,
1059 size_t payload_len
);
1060 #else /* CONFIG_DMA_ENGINE */
1061 static inline int dmaengine_desc_attach_metadata(
1062 struct dma_async_tx_descriptor
*desc
, void *data
, size_t len
)
1066 static inline void *dmaengine_desc_get_metadata_ptr(
1067 struct dma_async_tx_descriptor
*desc
, size_t *payload_len
,
1072 static inline int dmaengine_desc_set_metadata_len(
1073 struct dma_async_tx_descriptor
*desc
, size_t payload_len
)
1077 #endif /* CONFIG_DMA_ENGINE */
1080 * dmaengine_terminate_all() - Terminate all active DMA transfers
1081 * @chan: The channel for which to terminate the transfers
1083 * This function is DEPRECATED use either dmaengine_terminate_sync() or
1084 * dmaengine_terminate_async() instead.
1086 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
1088 if (chan
->device
->device_terminate_all
)
1089 return chan
->device
->device_terminate_all(chan
);
1095 * dmaengine_terminate_async() - Terminate all active DMA transfers
1096 * @chan: The channel for which to terminate the transfers
1098 * Calling this function will terminate all active and pending descriptors
1099 * that have previously been submitted to the channel. It is not guaranteed
1100 * though that the transfer for the active descriptor has stopped when the
1101 * function returns. Furthermore it is possible the complete callback of a
1102 * submitted transfer is still running when this function returns.
1104 * dmaengine_synchronize() needs to be called before it is safe to free
1105 * any memory that is accessed by previously submitted descriptors or before
1106 * freeing any resources accessed from within the completion callback of any
1107 * previously submitted descriptors.
1109 * This function can be called from atomic context as well as from within a
1110 * complete callback of a descriptor submitted on the same channel.
1112 * If none of the two conditions above apply consider using
1113 * dmaengine_terminate_sync() instead.
1115 static inline int dmaengine_terminate_async(struct dma_chan
*chan
)
1117 if (chan
->device
->device_terminate_all
)
1118 return chan
->device
->device_terminate_all(chan
);
1124 * dmaengine_synchronize() - Synchronize DMA channel termination
1125 * @chan: The channel to synchronize
1127 * Synchronizes to the DMA channel termination to the current context. When this
1128 * function returns it is guaranteed that all transfers for previously issued
1129 * descriptors have stopped and it is safe to free the memory associated
1130 * with them. Furthermore it is guaranteed that all complete callback functions
1131 * for a previously submitted descriptor have finished running and it is safe to
1132 * free resources accessed from within the complete callbacks.
1134 * The behavior of this function is undefined if dma_async_issue_pending() has
1135 * been called between dmaengine_terminate_async() and this function.
1137 * This function must only be called from non-atomic context and must not be
1138 * called from within a complete callback of a descriptor submitted on the same
1141 static inline void dmaengine_synchronize(struct dma_chan
*chan
)
1145 if (chan
->device
->device_synchronize
)
1146 chan
->device
->device_synchronize(chan
);
1150 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1151 * @chan: The channel for which to terminate the transfers
1153 * Calling this function will terminate all active and pending transfers
1154 * that have previously been submitted to the channel. It is similar to
1155 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1156 * stopped and that all complete callbacks have finished running when the
1159 * This function must only be called from non-atomic context and must not be
1160 * called from within a complete callback of a descriptor submitted on the same
1163 static inline int dmaengine_terminate_sync(struct dma_chan
*chan
)
1167 ret
= dmaengine_terminate_async(chan
);
1171 dmaengine_synchronize(chan
);
1176 static inline int dmaengine_pause(struct dma_chan
*chan
)
1178 if (chan
->device
->device_pause
)
1179 return chan
->device
->device_pause(chan
);
1184 static inline int dmaengine_resume(struct dma_chan
*chan
)
1186 if (chan
->device
->device_resume
)
1187 return chan
->device
->device_resume(chan
);
1192 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
1193 dma_cookie_t cookie
, struct dma_tx_state
*state
)
1195 return chan
->device
->device_tx_status(chan
, cookie
, state
);
1198 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
1200 return desc
->tx_submit(desc
);
1203 static inline bool dmaengine_check_align(enum dmaengine_alignment align
,
1204 size_t off1
, size_t off2
, size_t len
)
1206 return !(((1 << align
) - 1) & (off1
| off2
| len
));
1209 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
1210 size_t off2
, size_t len
)
1212 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
1215 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
1216 size_t off2
, size_t len
)
1218 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
1221 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
1222 size_t off2
, size_t len
)
1224 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
1227 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
1228 size_t off2
, size_t len
)
1230 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
1234 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
1236 dma
->max_pq
= maxpq
;
1237 if (has_pq_continue
)
1238 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
1241 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
1243 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
1246 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
1248 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
1250 return (flags
& mask
) == mask
;
1253 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
1255 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
1258 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
1260 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
1263 /* dma_maxpq - reduce maxpq in the face of continued operations
1264 * @dma - dma device with PQ capability
1265 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1267 * When an engine does not support native continuation we need 3 extra
1268 * source slots to reuse P and Q with the following coefficients:
1269 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1270 * 2/ {01} * Q : use Q to continue Q' calculation
1271 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1273 * In the case where P is disabled we only need 1 extra source:
1274 * 1/ {01} * Q : use Q to continue Q' calculation
1276 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
1278 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
1279 return dma_dev_to_maxpq(dma
);
1280 if (dmaf_p_disabled_continue(flags
))
1281 return dma_dev_to_maxpq(dma
) - 1;
1282 if (dmaf_continue(flags
))
1283 return dma_dev_to_maxpq(dma
) - 3;
1287 static inline size_t dmaengine_get_icg(bool inc
, bool sgl
, size_t icg
,
1300 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template
*xt
,
1301 struct data_chunk
*chunk
)
1303 return dmaengine_get_icg(xt
->dst_inc
, xt
->dst_sgl
,
1304 chunk
->icg
, chunk
->dst_icg
);
1307 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template
*xt
,
1308 struct data_chunk
*chunk
)
1310 return dmaengine_get_icg(xt
->src_inc
, xt
->src_sgl
,
1311 chunk
->icg
, chunk
->src_icg
);
1314 /* --- public DMA engine API --- */
1316 #ifdef CONFIG_DMA_ENGINE
1317 void dmaengine_get(void);
1318 void dmaengine_put(void);
1320 static inline void dmaengine_get(void)
1323 static inline void dmaengine_put(void)
1328 #ifdef CONFIG_ASYNC_TX_DMA
1329 #define async_dmaengine_get() dmaengine_get()
1330 #define async_dmaengine_put() dmaengine_put()
1331 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1332 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1334 #define async_dma_find_channel(type) dma_find_channel(type)
1335 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1337 static inline void async_dmaengine_get(void)
1340 static inline void async_dmaengine_put(void)
1343 static inline struct dma_chan
*
1344 async_dma_find_channel(enum dma_transaction_type type
)
1348 #endif /* CONFIG_ASYNC_TX_DMA */
1349 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
1350 struct dma_chan
*chan
);
1352 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
1354 tx
->flags
|= DMA_CTRL_ACK
;
1357 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
1359 tx
->flags
&= ~DMA_CTRL_ACK
;
1362 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
1364 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
1367 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1369 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1371 set_bit(tx_type
, dstp
->bits
);
1374 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1376 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1378 clear_bit(tx_type
, dstp
->bits
);
1381 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1382 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
1384 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
1387 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1389 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
1391 return test_bit(tx_type
, srcp
->bits
);
1394 #define for_each_dma_cap_mask(cap, mask) \
1395 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1398 * dma_async_issue_pending - flush pending transactions to HW
1399 * @chan: target DMA channel
1401 * This allows drivers to push copies to HW in batches,
1402 * reducing MMIO writes where possible.
1404 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
1406 chan
->device
->device_issue_pending(chan
);
1410 * dma_async_is_tx_complete - poll for transaction completion
1411 * @chan: DMA channel
1412 * @cookie: transaction identifier to check status of
1413 * @last: returns last completed cookie, can be NULL
1414 * @used: returns last issued cookie, can be NULL
1416 * If @last and @used are passed in, upon return they reflect the driver
1417 * internal state and can be used with dma_async_is_complete() to check
1418 * the status of multiple cookies without re-checking hardware state.
1420 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
1421 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
1423 struct dma_tx_state state
;
1424 enum dma_status status
;
1426 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1435 * dma_async_is_complete - test a cookie against chan state
1436 * @cookie: transaction identifier to test status of
1437 * @last_complete: last know completed transaction
1438 * @last_used: last cookie value handed out
1440 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1441 * the test logic is separated for lightweight testing of multiple cookies
1443 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1444 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1446 if (last_complete
<= last_used
) {
1447 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1448 return DMA_COMPLETE
;
1450 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1451 return DMA_COMPLETE
;
1453 return DMA_IN_PROGRESS
;
1457 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1464 st
->residue
= residue
;
1467 #ifdef CONFIG_DMA_ENGINE
1468 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1469 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1470 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1471 void dma_issue_pending_all(void);
1472 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1473 dma_filter_fn fn
, void *fn_param
,
1474 struct device_node
*np
);
1475 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1477 struct dma_chan
*dma_request_chan(struct device
*dev
, const char *name
);
1478 struct dma_chan
*dma_request_chan_by_mask(const dma_cap_mask_t
*mask
);
1480 void dma_release_channel(struct dma_chan
*chan
);
1481 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1483 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1487 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1489 return DMA_COMPLETE
;
1491 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1493 return DMA_COMPLETE
;
1495 static inline void dma_issue_pending_all(void)
1498 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1501 struct device_node
*np
)
1505 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1510 static inline struct dma_chan
*dma_request_chan(struct device
*dev
,
1513 return ERR_PTR(-ENODEV
);
1515 static inline struct dma_chan
*dma_request_chan_by_mask(
1516 const dma_cap_mask_t
*mask
)
1518 return ERR_PTR(-ENODEV
);
1520 static inline void dma_release_channel(struct dma_chan
*chan
)
1523 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1524 struct dma_slave_caps
*caps
)
1530 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1532 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor
*tx
)
1534 struct dma_slave_caps caps
;
1537 ret
= dma_get_slave_caps(tx
->chan
, &caps
);
1541 if (!caps
.descriptor_reuse
)
1544 tx
->flags
|= DMA_CTRL_REUSE
;
1548 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor
*tx
)
1550 tx
->flags
&= ~DMA_CTRL_REUSE
;
1553 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor
*tx
)
1555 return (tx
->flags
& DMA_CTRL_REUSE
) == DMA_CTRL_REUSE
;
1558 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor
*desc
)
1560 /* this is supported for reusable desc, so check that */
1561 if (!dmaengine_desc_test_reuse(desc
))
1564 return desc
->desc_free(desc
);
1567 /* --- DMA device --- */
1569 int dma_async_device_register(struct dma_device
*device
);
1570 int dmaenginem_async_device_register(struct dma_device
*device
);
1571 void dma_async_device_unregister(struct dma_device
*device
);
1572 int dma_async_device_channel_register(struct dma_device
*device
,
1573 struct dma_chan
*chan
);
1574 void dma_async_device_channel_unregister(struct dma_device
*device
,
1575 struct dma_chan
*chan
);
1576 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1577 #define dma_request_channel(mask, x, y) \
1578 __dma_request_channel(&(mask), x, y, NULL)
1580 static inline struct dma_chan
1581 *dma_request_slave_channel_compat(const dma_cap_mask_t mask
,
1582 dma_filter_fn fn
, void *fn_param
,
1583 struct device
*dev
, const char *name
)
1585 struct dma_chan
*chan
;
1587 chan
= dma_request_slave_channel(dev
, name
);
1591 if (!fn
|| !fn_param
)
1594 return __dma_request_channel(&mask
, fn
, fn_param
, NULL
);
1597 static inline char *
1598 dmaengine_get_direction_text(enum dma_transfer_direction dir
)
1601 case DMA_DEV_TO_MEM
:
1602 return "DEV_TO_MEM";
1603 case DMA_MEM_TO_DEV
:
1604 return "MEM_TO_DEV";
1605 case DMA_MEM_TO_MEM
:
1606 return "MEM_TO_MEM";
1607 case DMA_DEV_TO_DEV
:
1608 return "DEV_TO_DEV";
1613 #endif /* DMAENGINE_H */