2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/scatterlist.h>
27 #include <linux/bitmap.h>
31 * typedef dma_cookie_t - an opaque DMA cookie
33 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
35 typedef s32 dma_cookie_t
;
36 #define DMA_MIN_COOKIE 1
37 #define DMA_MAX_COOKIE INT_MAX
39 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
42 * enum dma_status - DMA transaction status
43 * @DMA_SUCCESS: transaction completed successfully
44 * @DMA_IN_PROGRESS: transaction not yet processed
45 * @DMA_PAUSED: transaction is paused
46 * @DMA_ERROR: transaction failed
56 * enum dma_transaction_type - DMA transaction types/indexes
58 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
59 * automatically set as dma devices are registered.
61 enum dma_transaction_type
{
76 /* last transaction type for creation of the capabilities mask */
77 #define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
80 * enum dma_transfer_direction - dma transfer mode and direction indicator
81 * @DMA_MEM_TO_MEM: Async/Memcpy mode
82 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
83 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
84 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
86 enum dma_transfer_direction
{
94 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
95 * control completion, and communicate status.
96 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
98 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
99 * acknowledges receipt, i.e. has has a chance to establish any dependency
101 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
102 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
103 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
104 * (if not set, do the source dma-unmapping as page)
105 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
106 * (if not set, do the destination dma-unmapping as page)
107 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
108 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
109 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
110 * sources that were the result of a previous operation, in the case of a PQ
111 * operation it continues the calculation with new sources
112 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
113 * on the result of this operation
115 enum dma_ctrl_flags
{
116 DMA_PREP_INTERRUPT
= (1 << 0),
117 DMA_CTRL_ACK
= (1 << 1),
118 DMA_COMPL_SKIP_SRC_UNMAP
= (1 << 2),
119 DMA_COMPL_SKIP_DEST_UNMAP
= (1 << 3),
120 DMA_COMPL_SRC_UNMAP_SINGLE
= (1 << 4),
121 DMA_COMPL_DEST_UNMAP_SINGLE
= (1 << 5),
122 DMA_PREP_PQ_DISABLE_P
= (1 << 6),
123 DMA_PREP_PQ_DISABLE_Q
= (1 << 7),
124 DMA_PREP_CONTINUE
= (1 << 8),
125 DMA_PREP_FENCE
= (1 << 9),
129 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
130 * on a running channel.
131 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
132 * @DMA_PAUSE: pause ongoing transfers
133 * @DMA_RESUME: resume paused transfer
134 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
135 * that need to runtime reconfigure the slave channels (as opposed to passing
136 * configuration data in statically from the platform). An additional
137 * argument of struct dma_slave_config must be passed in with this
139 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
140 * into external start mode.
147 FSLDMA_EXTERNAL_START
,
151 * enum sum_check_bits - bit position of pq_check_flags
153 enum sum_check_bits
{
159 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
160 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
161 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
163 enum sum_check_flags
{
164 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
165 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
170 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
171 * See linux/cpumask.h
173 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
176 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
177 * @memcpy_count: transaction counter
178 * @bytes_transferred: byte counter
181 struct dma_chan_percpu
{
183 unsigned long memcpy_count
;
184 unsigned long bytes_transferred
;
188 * struct dma_chan - devices supply DMA channels, clients use them
189 * @device: ptr to the dma device who supplies this channel, always !%NULL
190 * @cookie: last cookie value returned to client
191 * @chan_id: channel ID for sysfs
192 * @dev: class device for sysfs
193 * @device_node: used to add this to the device chan list
194 * @local: per-cpu pointer to a struct dma_chan_percpu
195 * @client-count: how many clients are using this channel
196 * @table_count: number of appearances in the mem-to-mem allocation table
197 * @private: private data for certain client-channel associations
200 struct dma_device
*device
;
205 struct dma_chan_dev
*dev
;
207 struct list_head device_node
;
208 struct dma_chan_percpu __percpu
*local
;
215 * struct dma_chan_dev - relate sysfs device node to backing channel device
216 * @chan - driver channel device
217 * @device - sysfs device
218 * @dev_id - parent dma_device dev_id
219 * @idr_ref - reference count to gate release of dma_device dev_id
221 struct dma_chan_dev
{
222 struct dma_chan
*chan
;
223 struct device device
;
229 * enum dma_slave_buswidth - defines bus with of the DMA slave
230 * device, source or target buses
232 enum dma_slave_buswidth
{
233 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
234 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
235 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
236 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
237 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
241 * struct dma_slave_config - dma slave channel runtime config
242 * @direction: whether the data shall go in or out on this slave
243 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
244 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
245 * need to differentiate source and target addresses.
246 * @src_addr: this is the physical address where DMA slave data
247 * should be read (RX), if the source is memory this argument is
249 * @dst_addr: this is the physical address where DMA slave data
250 * should be written (TX), if the source is memory this argument
252 * @src_addr_width: this is the width in bytes of the source (RX)
253 * register where DMA data shall be read. If the source
254 * is memory this may be ignored depending on architecture.
255 * Legal values: 1, 2, 4, 8.
256 * @dst_addr_width: same as src_addr_width but for destination
257 * target (TX) mutatis mutandis.
258 * @src_maxburst: the maximum number of words (note: words, as in
259 * units of the src_addr_width member, not bytes) that can be sent
260 * in one burst to the device. Typically something like half the
261 * FIFO depth on I/O peripherals so you don't overflow it. This
262 * may or may not be applicable on memory sources.
263 * @dst_maxburst: same as src_maxburst but for destination target
266 * This struct is passed in as configuration data to a DMA engine
267 * in order to set up a certain channel for DMA transport at runtime.
268 * The DMA device/engine has to provide support for an additional
269 * command in the channel config interface, DMA_SLAVE_CONFIG
270 * and this struct will then be passed in as an argument to the
271 * DMA engine device_control() function.
273 * The rationale for adding configuration information to this struct
274 * is as follows: if it is likely that most DMA slave controllers in
275 * the world will support the configuration option, then make it
276 * generic. If not: if it is fixed so that it be sent in static from
277 * the platform data, then prefer to do that. Else, if it is neither
278 * fixed at runtime, nor generic enough (such as bus mastership on
279 * some CPU family and whatnot) then create a custom slave config
280 * struct and pass that, then make this config a member of that
281 * struct, if applicable.
283 struct dma_slave_config
{
284 enum dma_transfer_direction direction
;
287 enum dma_slave_buswidth src_addr_width
;
288 enum dma_slave_buswidth dst_addr_width
;
293 static inline const char *dma_chan_name(struct dma_chan
*chan
)
295 return dev_name(&chan
->dev
->device
);
298 void dma_chan_cleanup(struct kref
*kref
);
301 * typedef dma_filter_fn - callback filter for dma_request_channel
302 * @chan: channel to be reviewed
303 * @filter_param: opaque parameter passed through dma_request_channel
305 * When this optional parameter is specified in a call to dma_request_channel a
306 * suitable channel is passed to this routine for further dispositioning before
307 * being returned. Where 'suitable' indicates a non-busy channel that
308 * satisfies the given capability mask. It returns 'true' to indicate that the
309 * channel is suitable.
311 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
313 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
315 * struct dma_async_tx_descriptor - async transaction descriptor
316 * ---dma generic offload fields---
317 * @cookie: tracking cookie for this transaction, set to -EBUSY if
318 * this tx is sitting on a dependency list
319 * @flags: flags to augment operation preparation, control completion, and
321 * @phys: physical address of the descriptor
322 * @chan: target channel for this operation
323 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
324 * @callback: routine to call after this operation is complete
325 * @callback_param: general parameter to pass to the callback routine
326 * ---async_tx api specific fields---
327 * @next: at completion submit this descriptor
328 * @parent: pointer to the next level up in the dependency chain
329 * @lock: protect the parent and next pointers
331 struct dma_async_tx_descriptor
{
333 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
335 struct dma_chan
*chan
;
336 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
337 dma_async_tx_callback callback
;
338 void *callback_param
;
339 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
340 struct dma_async_tx_descriptor
*next
;
341 struct dma_async_tx_descriptor
*parent
;
346 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
347 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
350 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
353 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
357 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
360 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
363 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
367 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
373 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
375 spin_lock_bh(&txd
->lock
);
377 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
379 spin_unlock_bh(&txd
->lock
);
381 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
386 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
390 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
394 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
398 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
405 * struct dma_tx_state - filled in to report the status of
407 * @last: last completed DMA cookie
408 * @used: last issued DMA cookie (i.e. the one in progress)
409 * @residue: the remaining number of bytes left to transmit
410 * on the selected transfer for states DMA_IN_PROGRESS and
411 * DMA_PAUSED if this is implemented in the driver, else 0
413 struct dma_tx_state
{
420 * struct dma_device - info on the entity supplying DMA services
421 * @chancnt: how many DMA channels are supported
422 * @privatecnt: how many DMA channels are requested by dma_request_channel
423 * @channels: the list of struct dma_chan
424 * @global_node: list_head for global dma_device_list
425 * @cap_mask: one or more dma_capability flags
426 * @max_xor: maximum number of xor sources, 0 if no capability
427 * @max_pq: maximum number of PQ sources and PQ-continue capability
428 * @copy_align: alignment shift for memcpy operations
429 * @xor_align: alignment shift for xor operations
430 * @pq_align: alignment shift for pq operations
431 * @fill_align: alignment shift for memset operations
432 * @dev_id: unique device ID
433 * @dev: struct device reference for dma mapping api
434 * @device_alloc_chan_resources: allocate resources and return the
435 * number of allocated descriptors
436 * @device_free_chan_resources: release DMA channel's resources
437 * @device_prep_dma_memcpy: prepares a memcpy operation
438 * @device_prep_dma_xor: prepares a xor operation
439 * @device_prep_dma_xor_val: prepares a xor validation operation
440 * @device_prep_dma_pq: prepares a pq operation
441 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
442 * @device_prep_dma_memset: prepares a memset operation
443 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
444 * @device_prep_slave_sg: prepares a slave dma operation
445 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
446 * The function takes a buffer of size buf_len. The callback function will
447 * be called after period_len bytes have been transferred.
448 * @device_control: manipulate all pending operations on a channel, returns
450 * @device_tx_status: poll for transaction completion, the optional
451 * txstate parameter can be supplied with a pointer to get a
452 * struct with auxiliary transfer status information, otherwise the call
453 * will just return a simple status code
454 * @device_issue_pending: push pending transactions to hardware
458 unsigned int chancnt
;
459 unsigned int privatecnt
;
460 struct list_head channels
;
461 struct list_head global_node
;
462 dma_cap_mask_t cap_mask
;
463 unsigned short max_xor
;
464 unsigned short max_pq
;
469 #define DMA_HAS_PQ_CONTINUE (1 << 15)
474 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
475 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
477 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
478 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
479 size_t len
, unsigned long flags
);
480 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
481 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
482 unsigned int src_cnt
, size_t len
, unsigned long flags
);
483 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
484 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
485 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
486 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
487 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
488 unsigned int src_cnt
, const unsigned char *scf
,
489 size_t len
, unsigned long flags
);
490 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
491 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
492 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
493 enum sum_check_flags
*pqres
, unsigned long flags
);
494 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
495 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
496 unsigned long flags
);
497 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
498 struct dma_chan
*chan
, unsigned long flags
);
499 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
500 struct dma_chan
*chan
,
501 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
502 struct scatterlist
*src_sg
, unsigned int src_nents
,
503 unsigned long flags
);
505 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
506 struct dma_chan
*chan
, struct scatterlist
*sgl
,
507 unsigned int sg_len
, enum dma_transfer_direction direction
,
508 unsigned long flags
);
509 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
510 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
511 size_t period_len
, enum dma_transfer_direction direction
);
512 int (*device_control
)(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
515 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
517 struct dma_tx_state
*txstate
);
518 void (*device_issue_pending
)(struct dma_chan
*chan
);
521 static inline int dmaengine_device_control(struct dma_chan
*chan
,
522 enum dma_ctrl_cmd cmd
,
525 return chan
->device
->device_control(chan
, cmd
, arg
);
528 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
529 struct dma_slave_config
*config
)
531 return dmaengine_device_control(chan
, DMA_SLAVE_CONFIG
,
532 (unsigned long)config
);
535 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
536 struct dma_chan
*chan
, void *buf
, size_t len
,
537 enum dma_transfer_direction dir
, unsigned long flags
)
539 struct scatterlist sg
;
540 sg_init_one(&sg
, buf
, len
);
542 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1, dir
, flags
);
545 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
547 return dmaengine_device_control(chan
, DMA_TERMINATE_ALL
, 0);
550 static inline int dmaengine_pause(struct dma_chan
*chan
)
552 return dmaengine_device_control(chan
, DMA_PAUSE
, 0);
555 static inline int dmaengine_resume(struct dma_chan
*chan
)
557 return dmaengine_device_control(chan
, DMA_RESUME
, 0);
560 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
562 return desc
->tx_submit(desc
);
565 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
571 mask
= (1 << align
) - 1;
572 if (mask
& (off1
| off2
| len
))
577 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
578 size_t off2
, size_t len
)
580 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
583 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
584 size_t off2
, size_t len
)
586 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
589 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
590 size_t off2
, size_t len
)
592 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
595 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
596 size_t off2
, size_t len
)
598 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
602 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
606 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
609 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
611 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
614 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
616 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
618 return (flags
& mask
) == mask
;
621 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
623 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
626 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
628 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
631 /* dma_maxpq - reduce maxpq in the face of continued operations
632 * @dma - dma device with PQ capability
633 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
635 * When an engine does not support native continuation we need 3 extra
636 * source slots to reuse P and Q with the following coefficients:
637 * 1/ {00} * P : remove P from Q', but use it as a source for P'
638 * 2/ {01} * Q : use Q to continue Q' calculation
639 * 3/ {00} * Q : subtract Q from P' to cancel (2)
641 * In the case where P is disabled we only need 1 extra source:
642 * 1/ {01} * Q : use Q to continue Q' calculation
644 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
646 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
647 return dma_dev_to_maxpq(dma
);
648 else if (dmaf_p_disabled_continue(flags
))
649 return dma_dev_to_maxpq(dma
) - 1;
650 else if (dmaf_continue(flags
))
651 return dma_dev_to_maxpq(dma
) - 3;
655 /* --- public DMA engine API --- */
657 #ifdef CONFIG_DMA_ENGINE
658 void dmaengine_get(void);
659 void dmaengine_put(void);
661 static inline void dmaengine_get(void)
664 static inline void dmaengine_put(void)
669 #ifdef CONFIG_NET_DMA
670 #define net_dmaengine_get() dmaengine_get()
671 #define net_dmaengine_put() dmaengine_put()
673 static inline void net_dmaengine_get(void)
676 static inline void net_dmaengine_put(void)
681 #ifdef CONFIG_ASYNC_TX_DMA
682 #define async_dmaengine_get() dmaengine_get()
683 #define async_dmaengine_put() dmaengine_put()
684 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
685 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
687 #define async_dma_find_channel(type) dma_find_channel(type)
688 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
690 static inline void async_dmaengine_get(void)
693 static inline void async_dmaengine_put(void)
696 static inline struct dma_chan
*
697 async_dma_find_channel(enum dma_transaction_type type
)
701 #endif /* CONFIG_ASYNC_TX_DMA */
703 dma_cookie_t
dma_async_memcpy_buf_to_buf(struct dma_chan
*chan
,
704 void *dest
, void *src
, size_t len
);
705 dma_cookie_t
dma_async_memcpy_buf_to_pg(struct dma_chan
*chan
,
706 struct page
*page
, unsigned int offset
, void *kdata
, size_t len
);
707 dma_cookie_t
dma_async_memcpy_pg_to_pg(struct dma_chan
*chan
,
708 struct page
*dest_pg
, unsigned int dest_off
, struct page
*src_pg
,
709 unsigned int src_off
, size_t len
);
710 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
711 struct dma_chan
*chan
);
713 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
715 tx
->flags
|= DMA_CTRL_ACK
;
718 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
720 tx
->flags
&= ~DMA_CTRL_ACK
;
723 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
725 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
728 #define first_dma_cap(mask) __first_dma_cap(&(mask))
729 static inline int __first_dma_cap(const dma_cap_mask_t
*srcp
)
731 return min_t(int, DMA_TX_TYPE_END
,
732 find_first_bit(srcp
->bits
, DMA_TX_TYPE_END
));
735 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
736 static inline int __next_dma_cap(int n
, const dma_cap_mask_t
*srcp
)
738 return min_t(int, DMA_TX_TYPE_END
,
739 find_next_bit(srcp
->bits
, DMA_TX_TYPE_END
, n
+1));
742 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
744 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
746 set_bit(tx_type
, dstp
->bits
);
749 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
751 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
753 clear_bit(tx_type
, dstp
->bits
);
756 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
757 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
759 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
762 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
764 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
766 return test_bit(tx_type
, srcp
->bits
);
769 #define for_each_dma_cap_mask(cap, mask) \
770 for ((cap) = first_dma_cap(mask); \
771 (cap) < DMA_TX_TYPE_END; \
772 (cap) = next_dma_cap((cap), (mask)))
775 * dma_async_issue_pending - flush pending transactions to HW
776 * @chan: target DMA channel
778 * This allows drivers to push copies to HW in batches,
779 * reducing MMIO writes where possible.
781 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
783 chan
->device
->device_issue_pending(chan
);
786 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
789 * dma_async_is_tx_complete - poll for transaction completion
791 * @cookie: transaction identifier to check status of
792 * @last: returns last completed cookie, can be NULL
793 * @used: returns last issued cookie, can be NULL
795 * If @last and @used are passed in, upon return they reflect the driver
796 * internal state and can be used with dma_async_is_complete() to check
797 * the status of multiple cookies without re-checking hardware state.
799 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
800 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
802 struct dma_tx_state state
;
803 enum dma_status status
;
805 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
813 #define dma_async_memcpy_complete(chan, cookie, last, used)\
814 dma_async_is_tx_complete(chan, cookie, last, used)
817 * dma_async_is_complete - test a cookie against chan state
818 * @cookie: transaction identifier to test status of
819 * @last_complete: last know completed transaction
820 * @last_used: last cookie value handed out
822 * dma_async_is_complete() is used in dma_async_memcpy_complete()
823 * the test logic is separated for lightweight testing of multiple cookies
825 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
826 dma_cookie_t last_complete
, dma_cookie_t last_used
)
828 if (last_complete
<= last_used
) {
829 if ((cookie
<= last_complete
) || (cookie
> last_used
))
832 if ((cookie
<= last_complete
) && (cookie
> last_used
))
835 return DMA_IN_PROGRESS
;
839 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
844 st
->residue
= residue
;
848 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
849 #ifdef CONFIG_DMA_ENGINE
850 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
851 void dma_issue_pending_all(void);
852 struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
, dma_filter_fn fn
, void *fn_param
);
853 void dma_release_channel(struct dma_chan
*chan
);
855 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
859 static inline void dma_issue_pending_all(void)
862 static inline struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
,
863 dma_filter_fn fn
, void *fn_param
)
867 static inline void dma_release_channel(struct dma_chan
*chan
)
872 /* --- DMA device --- */
874 int dma_async_device_register(struct dma_device
*device
);
875 void dma_async_device_unregister(struct dma_device
*device
);
876 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
877 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
878 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
880 /* --- Helper iov-locking functions --- */
882 struct dma_page_list
{
883 char __user
*base_address
;
888 struct dma_pinned_list
{
890 struct dma_page_list page_list
[0];
893 struct dma_pinned_list
*dma_pin_iovec_pages(struct iovec
*iov
, size_t len
);
894 void dma_unpin_iovec_pages(struct dma_pinned_list
* pinned_list
);
896 dma_cookie_t
dma_memcpy_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
897 struct dma_pinned_list
*pinned_list
, unsigned char *kdata
, size_t len
);
898 dma_cookie_t
dma_memcpy_pg_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
899 struct dma_pinned_list
*pinned_list
, struct page
*page
,
900 unsigned int offset
, size_t len
);
902 #endif /* DMAENGINE_H */