2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
17 #ifndef LINUX_DMAENGINE_H
18 #define LINUX_DMAENGINE_H
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/uio.h>
23 #include <linux/bug.h>
24 #include <linux/scatterlist.h>
25 #include <linux/bitmap.h>
26 #include <linux/types.h>
30 * typedef dma_cookie_t - an opaque DMA cookie
32 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
34 typedef s32 dma_cookie_t
;
35 #define DMA_MIN_COOKIE 1
37 static inline int dma_submit_error(dma_cookie_t cookie
)
39 return cookie
< 0 ? cookie
: 0;
43 * enum dma_status - DMA transaction status
44 * @DMA_COMPLETE: transaction completed
45 * @DMA_IN_PROGRESS: transaction not yet processed
46 * @DMA_PAUSED: transaction is paused
47 * @DMA_ERROR: transaction failed
57 * enum dma_transaction_type - DMA transaction types/indexes
59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
60 * automatically set as dma devices are registered.
62 enum dma_transaction_type
{
75 /* last transaction type for creation of the capabilities mask */
80 * enum dma_transfer_direction - dma transfer mode and direction indicator
81 * @DMA_MEM_TO_MEM: Async/Memcpy mode
82 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
83 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
84 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
86 enum dma_transfer_direction
{
95 * Interleaved Transfer Request
96 * ----------------------------
97 * A chunk is collection of contiguous bytes to be transfered.
98 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
99 * ICGs may or maynot change between chunks.
100 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
101 * that when repeated an integral number of times, specifies the transfer.
102 * A transfer template is specification of a Frame, the number of times
103 * it is to be repeated and other per-transfer attributes.
105 * Practically, a client driver would have ready a template for each
106 * type of transfer it is going to need during its lifetime and
107 * set only 'src_start' and 'dst_start' before submitting the requests.
110 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
111 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
118 * struct data_chunk - Element of scatter-gather list that makes a frame.
119 * @size: Number of bytes to read from source.
120 * size_dst := fn(op, size_src), so doesn't mean much for destination.
121 * @icg: Number of bytes to jump after last src/dst address of this
122 * chunk and before first src/dst address for next chunk.
123 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
124 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
132 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
134 * @src_start: Bus address of source for the first chunk.
135 * @dst_start: Bus address of destination for the first chunk.
136 * @dir: Specifies the type of Source and Destination.
137 * @src_inc: If the source address increments after reading from it.
138 * @dst_inc: If the destination address increments after writing to it.
139 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
140 * Otherwise, source is read contiguously (icg ignored).
141 * Ignored if src_inc is false.
142 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
143 * Otherwise, destination is filled contiguously (icg ignored).
144 * Ignored if dst_inc is false.
145 * @numf: Number of frames in this template.
146 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
147 * @sgl: Array of {chunk,icg} pairs that make up a frame.
149 struct dma_interleaved_template
{
150 dma_addr_t src_start
;
151 dma_addr_t dst_start
;
152 enum dma_transfer_direction dir
;
159 struct data_chunk sgl
[0];
163 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
164 * control completion, and communicate status.
165 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
167 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
168 * acknowledges receipt, i.e. has has a chance to establish any dependency
170 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
171 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
172 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
173 * sources that were the result of a previous operation, in the case of a PQ
174 * operation it continues the calculation with new sources
175 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
176 * on the result of this operation
178 enum dma_ctrl_flags
{
179 DMA_PREP_INTERRUPT
= (1 << 0),
180 DMA_CTRL_ACK
= (1 << 1),
181 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
182 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
183 DMA_PREP_CONTINUE
= (1 << 4),
184 DMA_PREP_FENCE
= (1 << 5),
188 * enum sum_check_bits - bit position of pq_check_flags
190 enum sum_check_bits
{
196 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
197 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
198 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
200 enum sum_check_flags
{
201 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
202 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
207 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
208 * See linux/cpumask.h
210 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
213 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
214 * @memcpy_count: transaction counter
215 * @bytes_transferred: byte counter
218 struct dma_chan_percpu
{
220 unsigned long memcpy_count
;
221 unsigned long bytes_transferred
;
225 * struct dma_chan - devices supply DMA channels, clients use them
226 * @device: ptr to the dma device who supplies this channel, always !%NULL
227 * @cookie: last cookie value returned to client
228 * @completed_cookie: last completed cookie for this channel
229 * @chan_id: channel ID for sysfs
230 * @dev: class device for sysfs
231 * @device_node: used to add this to the device chan list
232 * @local: per-cpu pointer to a struct dma_chan_percpu
233 * @client_count: how many clients are using this channel
234 * @table_count: number of appearances in the mem-to-mem allocation table
235 * @private: private data for certain client-channel associations
238 struct dma_device
*device
;
240 dma_cookie_t completed_cookie
;
244 struct dma_chan_dev
*dev
;
246 struct list_head device_node
;
247 struct dma_chan_percpu __percpu
*local
;
254 * struct dma_chan_dev - relate sysfs device node to backing channel device
255 * @chan: driver channel device
256 * @device: sysfs device
257 * @dev_id: parent dma_device dev_id
258 * @idr_ref: reference count to gate release of dma_device dev_id
260 struct dma_chan_dev
{
261 struct dma_chan
*chan
;
262 struct device device
;
268 * enum dma_slave_buswidth - defines bus width of the DMA slave
269 * device, source or target buses
271 enum dma_slave_buswidth
{
272 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
273 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
274 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
275 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
276 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
277 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
278 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
279 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
280 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
284 * struct dma_slave_config - dma slave channel runtime config
285 * @direction: whether the data shall go in or out on this slave
286 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
287 * legal values. DEPRECATED, drivers should use the direction argument
288 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
289 * the dir field in the dma_interleaved_template structure.
290 * @src_addr: this is the physical address where DMA slave data
291 * should be read (RX), if the source is memory this argument is
293 * @dst_addr: this is the physical address where DMA slave data
294 * should be written (TX), if the source is memory this argument
296 * @src_addr_width: this is the width in bytes of the source (RX)
297 * register where DMA data shall be read. If the source
298 * is memory this may be ignored depending on architecture.
299 * Legal values: 1, 2, 4, 8.
300 * @dst_addr_width: same as src_addr_width but for destination
301 * target (TX) mutatis mutandis.
302 * @src_maxburst: the maximum number of words (note: words, as in
303 * units of the src_addr_width member, not bytes) that can be sent
304 * in one burst to the device. Typically something like half the
305 * FIFO depth on I/O peripherals so you don't overflow it. This
306 * may or may not be applicable on memory sources.
307 * @dst_maxburst: same as src_maxburst but for destination target
309 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
310 * with 'true' if peripheral should be flow controller. Direction will be
311 * selected at Runtime.
312 * @slave_id: Slave requester id. Only valid for slave channels. The dma
313 * slave peripheral will have unique id as dma requester which need to be
314 * pass as slave config.
316 * This struct is passed in as configuration data to a DMA engine
317 * in order to set up a certain channel for DMA transport at runtime.
318 * The DMA device/engine has to provide support for an additional
319 * callback in the dma_device structure, device_config and this struct
320 * will then be passed in as an argument to the function.
322 * The rationale for adding configuration information to this struct is as
323 * follows: if it is likely that more than one DMA slave controllers in
324 * the world will support the configuration option, then make it generic.
325 * If not: if it is fixed so that it be sent in static from the platform
326 * data, then prefer to do that.
328 struct dma_slave_config
{
329 enum dma_transfer_direction direction
;
332 enum dma_slave_buswidth src_addr_width
;
333 enum dma_slave_buswidth dst_addr_width
;
337 unsigned int slave_id
;
341 * enum dma_residue_granularity - Granularity of the reported transfer residue
342 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
343 * DMA channel is only able to tell whether a descriptor has been completed or
344 * not, which means residue reporting is not supported by this channel. The
345 * residue field of the dma_tx_state field will always be 0.
346 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
347 * completed segment of the transfer (For cyclic transfers this is after each
348 * period). This is typically implemented by having the hardware generate an
349 * interrupt after each transferred segment and then the drivers updates the
350 * outstanding residue by the size of the segment. Another possibility is if
351 * the hardware supports scatter-gather and the segment descriptor has a field
352 * which gets set after the segment has been completed. The driver then counts
353 * the number of segments without the flag set to compute the residue.
354 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
355 * burst. This is typically only supported if the hardware has a progress
356 * register of some sort (E.g. a register with the current read/write address
357 * or a register with the amount of bursts/beats/bytes that have been
358 * transferred or still need to be transferred).
360 enum dma_residue_granularity
{
361 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
362 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
363 DMA_RESIDUE_GRANULARITY_BURST
= 2,
366 /* struct dma_slave_caps - expose capabilities of a slave channel only
368 * @src_addr_widths: bit mask of src addr widths the channel supports
369 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
370 * @directions: bit mask of slave direction the channel supported
371 * since the enum dma_transfer_direction is not defined as bits for each
372 * type of direction, the dma controller should fill (1 << <TYPE>) and same
373 * should be checked by controller as well
374 * @cmd_pause: true, if pause and thereby resume is supported
375 * @cmd_terminate: true, if terminate cmd is supported
376 * @residue_granularity: granularity of the reported transfer residue
378 struct dma_slave_caps
{
384 enum dma_residue_granularity residue_granularity
;
387 static inline const char *dma_chan_name(struct dma_chan
*chan
)
389 return dev_name(&chan
->dev
->device
);
392 void dma_chan_cleanup(struct kref
*kref
);
395 * typedef dma_filter_fn - callback filter for dma_request_channel
396 * @chan: channel to be reviewed
397 * @filter_param: opaque parameter passed through dma_request_channel
399 * When this optional parameter is specified in a call to dma_request_channel a
400 * suitable channel is passed to this routine for further dispositioning before
401 * being returned. Where 'suitable' indicates a non-busy channel that
402 * satisfies the given capability mask. It returns 'true' to indicate that the
403 * channel is suitable.
405 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
407 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
409 struct dmaengine_unmap_data
{
421 * struct dma_async_tx_descriptor - async transaction descriptor
422 * ---dma generic offload fields---
423 * @cookie: tracking cookie for this transaction, set to -EBUSY if
424 * this tx is sitting on a dependency list
425 * @flags: flags to augment operation preparation, control completion, and
427 * @phys: physical address of the descriptor
428 * @chan: target channel for this operation
429 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
430 * descriptor pending. To be pushed on .issue_pending() call
431 * @callback: routine to call after this operation is complete
432 * @callback_param: general parameter to pass to the callback routine
433 * ---async_tx api specific fields---
434 * @next: at completion submit this descriptor
435 * @parent: pointer to the next level up in the dependency chain
436 * @lock: protect the parent and next pointers
438 struct dma_async_tx_descriptor
{
440 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
442 struct dma_chan
*chan
;
443 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
444 dma_async_tx_callback callback
;
445 void *callback_param
;
446 struct dmaengine_unmap_data
*unmap
;
447 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
448 struct dma_async_tx_descriptor
*next
;
449 struct dma_async_tx_descriptor
*parent
;
454 #ifdef CONFIG_DMA_ENGINE
455 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
456 struct dmaengine_unmap_data
*unmap
)
458 kref_get(&unmap
->kref
);
462 struct dmaengine_unmap_data
*
463 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
464 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
466 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
467 struct dmaengine_unmap_data
*unmap
)
470 static inline struct dmaengine_unmap_data
*
471 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
475 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
480 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
483 dmaengine_unmap_put(tx
->unmap
);
488 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
489 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
492 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
495 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
499 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
502 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
505 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
509 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
515 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
517 spin_lock_bh(&txd
->lock
);
519 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
521 spin_unlock_bh(&txd
->lock
);
523 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
528 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
532 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
536 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
540 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
547 * struct dma_tx_state - filled in to report the status of
549 * @last: last completed DMA cookie
550 * @used: last issued DMA cookie (i.e. the one in progress)
551 * @residue: the remaining number of bytes left to transmit
552 * on the selected transfer for states DMA_IN_PROGRESS and
553 * DMA_PAUSED if this is implemented in the driver, else 0
555 struct dma_tx_state
{
562 * struct dma_device - info on the entity supplying DMA services
563 * @chancnt: how many DMA channels are supported
564 * @privatecnt: how many DMA channels are requested by dma_request_channel
565 * @channels: the list of struct dma_chan
566 * @global_node: list_head for global dma_device_list
567 * @cap_mask: one or more dma_capability flags
568 * @max_xor: maximum number of xor sources, 0 if no capability
569 * @max_pq: maximum number of PQ sources and PQ-continue capability
570 * @copy_align: alignment shift for memcpy operations
571 * @xor_align: alignment shift for xor operations
572 * @pq_align: alignment shift for pq operations
573 * @dev_id: unique device ID
574 * @dev: struct device reference for dma mapping api
575 * @src_addr_widths: bit mask of src addr widths the device supports
576 * @dst_addr_widths: bit mask of dst addr widths the device supports
577 * @directions: bit mask of slave direction the device supports since
578 * the enum dma_transfer_direction is not defined as bits for
579 * each type of direction, the dma controller should fill (1 <<
580 * <TYPE>) and same should be checked by controller as well
581 * @residue_granularity: granularity of the transfer residue reported
583 * @device_alloc_chan_resources: allocate resources and return the
584 * number of allocated descriptors
585 * @device_free_chan_resources: release DMA channel's resources
586 * @device_prep_dma_memcpy: prepares a memcpy operation
587 * @device_prep_dma_xor: prepares a xor operation
588 * @device_prep_dma_xor_val: prepares a xor validation operation
589 * @device_prep_dma_pq: prepares a pq operation
590 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
591 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
592 * @device_prep_slave_sg: prepares a slave dma operation
593 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
594 * The function takes a buffer of size buf_len. The callback function will
595 * be called after period_len bytes have been transferred.
596 * @device_prep_interleaved_dma: Transfer expression in a generic way.
597 * @device_config: Pushes a new configuration to a channel, return 0 or an error
599 * @device_pause: Pauses any transfer happening on a channel. Returns
601 * @device_resume: Resumes any transfer on a channel previously
602 * paused. Returns 0 or an error code
603 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
605 * @device_tx_status: poll for transaction completion, the optional
606 * txstate parameter can be supplied with a pointer to get a
607 * struct with auxiliary transfer status information, otherwise the call
608 * will just return a simple status code
609 * @device_issue_pending: push pending transactions to hardware
613 unsigned int chancnt
;
614 unsigned int privatecnt
;
615 struct list_head channels
;
616 struct list_head global_node
;
617 dma_cap_mask_t cap_mask
;
618 unsigned short max_xor
;
619 unsigned short max_pq
;
623 #define DMA_HAS_PQ_CONTINUE (1 << 15)
631 enum dma_residue_granularity residue_granularity
;
633 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
634 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
636 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
637 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
638 size_t len
, unsigned long flags
);
639 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
640 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
641 unsigned int src_cnt
, size_t len
, unsigned long flags
);
642 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
643 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
644 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
645 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
646 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
647 unsigned int src_cnt
, const unsigned char *scf
,
648 size_t len
, unsigned long flags
);
649 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
650 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
651 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
652 enum sum_check_flags
*pqres
, unsigned long flags
);
653 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
654 struct dma_chan
*chan
, unsigned long flags
);
655 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
656 struct dma_chan
*chan
,
657 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
658 struct scatterlist
*src_sg
, unsigned int src_nents
,
659 unsigned long flags
);
661 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
662 struct dma_chan
*chan
, struct scatterlist
*sgl
,
663 unsigned int sg_len
, enum dma_transfer_direction direction
,
664 unsigned long flags
, void *context
);
665 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
666 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
667 size_t period_len
, enum dma_transfer_direction direction
,
668 unsigned long flags
);
669 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
670 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
671 unsigned long flags
);
673 int (*device_config
)(struct dma_chan
*chan
,
674 struct dma_slave_config
*config
);
675 int (*device_pause
)(struct dma_chan
*chan
);
676 int (*device_resume
)(struct dma_chan
*chan
);
677 int (*device_terminate_all
)(struct dma_chan
*chan
);
679 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
681 struct dma_tx_state
*txstate
);
682 void (*device_issue_pending
)(struct dma_chan
*chan
);
685 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
686 struct dma_slave_config
*config
)
688 if (chan
->device
->device_config
)
689 return chan
->device
->device_config(chan
, config
);
694 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
696 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
699 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
700 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
701 enum dma_transfer_direction dir
, unsigned long flags
)
703 struct scatterlist sg
;
704 sg_init_table(&sg
, 1);
705 sg_dma_address(&sg
) = buf
;
706 sg_dma_len(&sg
) = len
;
708 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
712 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
713 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
714 enum dma_transfer_direction dir
, unsigned long flags
)
716 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
720 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
722 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
723 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
724 enum dma_transfer_direction dir
, unsigned long flags
,
725 struct rio_dma_ext
*rio_ext
)
727 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
728 dir
, flags
, rio_ext
);
732 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
733 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
734 size_t period_len
, enum dma_transfer_direction dir
,
737 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
738 period_len
, dir
, flags
);
741 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
742 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
745 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
748 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_sg(
749 struct dma_chan
*chan
,
750 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
751 struct scatterlist
*src_sg
, unsigned int src_nents
,
754 return chan
->device
->device_prep_dma_sg(chan
, dst_sg
, dst_nents
,
755 src_sg
, src_nents
, flags
);
758 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
760 if (chan
->device
->device_terminate_all
)
761 return chan
->device
->device_terminate_all(chan
);
766 static inline int dmaengine_pause(struct dma_chan
*chan
)
768 if (chan
->device
->device_pause
)
769 return chan
->device
->device_pause(chan
);
774 static inline int dmaengine_resume(struct dma_chan
*chan
)
776 if (chan
->device
->device_resume
)
777 return chan
->device
->device_resume(chan
);
782 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
783 dma_cookie_t cookie
, struct dma_tx_state
*state
)
785 return chan
->device
->device_tx_status(chan
, cookie
, state
);
788 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
790 return desc
->tx_submit(desc
);
793 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
799 mask
= (1 << align
) - 1;
800 if (mask
& (off1
| off2
| len
))
805 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
806 size_t off2
, size_t len
)
808 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
811 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
812 size_t off2
, size_t len
)
814 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
817 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
818 size_t off2
, size_t len
)
820 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
824 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
828 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
831 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
833 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
836 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
838 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
840 return (flags
& mask
) == mask
;
843 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
845 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
848 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
850 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
853 /* dma_maxpq - reduce maxpq in the face of continued operations
854 * @dma - dma device with PQ capability
855 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
857 * When an engine does not support native continuation we need 3 extra
858 * source slots to reuse P and Q with the following coefficients:
859 * 1/ {00} * P : remove P from Q', but use it as a source for P'
860 * 2/ {01} * Q : use Q to continue Q' calculation
861 * 3/ {00} * Q : subtract Q from P' to cancel (2)
863 * In the case where P is disabled we only need 1 extra source:
864 * 1/ {01} * Q : use Q to continue Q' calculation
866 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
868 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
869 return dma_dev_to_maxpq(dma
);
870 else if (dmaf_p_disabled_continue(flags
))
871 return dma_dev_to_maxpq(dma
) - 1;
872 else if (dmaf_continue(flags
))
873 return dma_dev_to_maxpq(dma
) - 3;
877 /* --- public DMA engine API --- */
879 #ifdef CONFIG_DMA_ENGINE
880 void dmaengine_get(void);
881 void dmaengine_put(void);
883 static inline void dmaengine_get(void)
886 static inline void dmaengine_put(void)
891 #ifdef CONFIG_ASYNC_TX_DMA
892 #define async_dmaengine_get() dmaengine_get()
893 #define async_dmaengine_put() dmaengine_put()
894 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
895 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
897 #define async_dma_find_channel(type) dma_find_channel(type)
898 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
900 static inline void async_dmaengine_get(void)
903 static inline void async_dmaengine_put(void)
906 static inline struct dma_chan
*
907 async_dma_find_channel(enum dma_transaction_type type
)
911 #endif /* CONFIG_ASYNC_TX_DMA */
912 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
913 struct dma_chan
*chan
);
915 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
917 tx
->flags
|= DMA_CTRL_ACK
;
920 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
922 tx
->flags
&= ~DMA_CTRL_ACK
;
925 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
927 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
930 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
932 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
934 set_bit(tx_type
, dstp
->bits
);
937 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
939 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
941 clear_bit(tx_type
, dstp
->bits
);
944 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
945 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
947 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
950 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
952 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
954 return test_bit(tx_type
, srcp
->bits
);
957 #define for_each_dma_cap_mask(cap, mask) \
958 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
961 * dma_async_issue_pending - flush pending transactions to HW
962 * @chan: target DMA channel
964 * This allows drivers to push copies to HW in batches,
965 * reducing MMIO writes where possible.
967 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
969 chan
->device
->device_issue_pending(chan
);
973 * dma_async_is_tx_complete - poll for transaction completion
975 * @cookie: transaction identifier to check status of
976 * @last: returns last completed cookie, can be NULL
977 * @used: returns last issued cookie, can be NULL
979 * If @last and @used are passed in, upon return they reflect the driver
980 * internal state and can be used with dma_async_is_complete() to check
981 * the status of multiple cookies without re-checking hardware state.
983 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
984 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
986 struct dma_tx_state state
;
987 enum dma_status status
;
989 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
998 * dma_async_is_complete - test a cookie against chan state
999 * @cookie: transaction identifier to test status of
1000 * @last_complete: last know completed transaction
1001 * @last_used: last cookie value handed out
1003 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1004 * the test logic is separated for lightweight testing of multiple cookies
1006 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1007 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1009 if (last_complete
<= last_used
) {
1010 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1011 return DMA_COMPLETE
;
1013 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1014 return DMA_COMPLETE
;
1016 return DMA_IN_PROGRESS
;
1020 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1025 st
->residue
= residue
;
1029 #ifdef CONFIG_DMA_ENGINE
1030 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1031 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1032 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1033 void dma_issue_pending_all(void);
1034 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1035 dma_filter_fn fn
, void *fn_param
);
1036 struct dma_chan
*dma_request_slave_channel_reason(struct device
*dev
,
1038 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1039 void dma_release_channel(struct dma_chan
*chan
);
1040 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1042 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1046 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1048 return DMA_COMPLETE
;
1050 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1052 return DMA_COMPLETE
;
1054 static inline void dma_issue_pending_all(void)
1057 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1058 dma_filter_fn fn
, void *fn_param
)
1062 static inline struct dma_chan
*dma_request_slave_channel_reason(
1063 struct device
*dev
, const char *name
)
1065 return ERR_PTR(-ENODEV
);
1067 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1072 static inline void dma_release_channel(struct dma_chan
*chan
)
1075 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1076 struct dma_slave_caps
*caps
)
1082 /* --- DMA device --- */
1084 int dma_async_device_register(struct dma_device
*device
);
1085 void dma_async_device_unregister(struct dma_device
*device
);
1086 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1087 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1088 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1089 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1090 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1091 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1093 static inline struct dma_chan
1094 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1095 dma_filter_fn fn
, void *fn_param
,
1096 struct device
*dev
, char *name
)
1098 struct dma_chan
*chan
;
1100 chan
= dma_request_slave_channel(dev
, name
);
1104 return __dma_request_channel(mask
, fn
, fn_param
);
1106 #endif /* DMAENGINE_H */