1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
5 #ifndef LINUX_DMAENGINE_H
6 #define LINUX_DMAENGINE_H
8 #include <linux/device.h>
10 #include <linux/uio.h>
11 #include <linux/bug.h>
12 #include <linux/scatterlist.h>
13 #include <linux/bitmap.h>
14 #include <linux/types.h>
18 * typedef dma_cookie_t - an opaque DMA cookie
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
22 typedef s32 dma_cookie_t
;
23 #define DMA_MIN_COOKIE 1
25 static inline int dma_submit_error(dma_cookie_t cookie
)
27 return cookie
< 0 ? cookie
: 0;
31 * enum dma_status - DMA transaction status
32 * @DMA_COMPLETE: transaction completed
33 * @DMA_IN_PROGRESS: transaction not yet processed
34 * @DMA_PAUSED: transaction is paused
35 * @DMA_ERROR: transaction failed
45 * enum dma_transaction_type - DMA transaction types/indexes
47 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
48 * automatically set as dma devices are registered.
50 enum dma_transaction_type
{
64 /* last transaction type for creation of the capabilities mask */
69 * enum dma_transfer_direction - dma transfer mode and direction indicator
70 * @DMA_MEM_TO_MEM: Async/Memcpy mode
71 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
72 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
73 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
75 enum dma_transfer_direction
{
84 * Interleaved Transfer Request
85 * ----------------------------
86 * A chunk is collection of contiguous bytes to be transfered.
87 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
88 * ICGs may or maynot change between chunks.
89 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
90 * that when repeated an integral number of times, specifies the transfer.
91 * A transfer template is specification of a Frame, the number of times
92 * it is to be repeated and other per-transfer attributes.
94 * Practically, a client driver would have ready a template for each
95 * type of transfer it is going to need during its lifetime and
96 * set only 'src_start' and 'dst_start' before submitting the requests.
99 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
100 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
107 * struct data_chunk - Element of scatter-gather list that makes a frame.
108 * @size: Number of bytes to read from source.
109 * size_dst := fn(op, size_src), so doesn't mean much for destination.
110 * @icg: Number of bytes to jump after last src/dst address of this
111 * chunk and before first src/dst address for next chunk.
112 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
113 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
114 * @dst_icg: Number of bytes to jump after last dst address of this
115 * chunk and before the first dst address for next chunk.
116 * Ignored if dst_inc is true and dst_sgl is false.
117 * @src_icg: Number of bytes to jump after last src address of this
118 * chunk and before the first src address for next chunk.
119 * Ignored if src_inc is true and src_sgl is false.
129 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
131 * @src_start: Bus address of source for the first chunk.
132 * @dst_start: Bus address of destination for the first chunk.
133 * @dir: Specifies the type of Source and Destination.
134 * @src_inc: If the source address increments after reading from it.
135 * @dst_inc: If the destination address increments after writing to it.
136 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
137 * Otherwise, source is read contiguously (icg ignored).
138 * Ignored if src_inc is false.
139 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
140 * Otherwise, destination is filled contiguously (icg ignored).
141 * Ignored if dst_inc is false.
142 * @numf: Number of frames in this template.
143 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
144 * @sgl: Array of {chunk,icg} pairs that make up a frame.
146 struct dma_interleaved_template
{
147 dma_addr_t src_start
;
148 dma_addr_t dst_start
;
149 enum dma_transfer_direction dir
;
156 struct data_chunk sgl
[0];
160 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
161 * control completion, and communicate status.
162 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
164 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
165 * acknowledges receipt, i.e. has has a chance to establish any dependency
167 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
168 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
169 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
170 * sources that were the result of a previous operation, in the case of a PQ
171 * operation it continues the calculation with new sources
172 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
173 * on the result of this operation
174 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
176 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
177 * data and the descriptor should be in different format from normal
180 enum dma_ctrl_flags
{
181 DMA_PREP_INTERRUPT
= (1 << 0),
182 DMA_CTRL_ACK
= (1 << 1),
183 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
184 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
185 DMA_PREP_CONTINUE
= (1 << 4),
186 DMA_PREP_FENCE
= (1 << 5),
187 DMA_CTRL_REUSE
= (1 << 6),
188 DMA_PREP_CMD
= (1 << 7),
192 * enum sum_check_bits - bit position of pq_check_flags
194 enum sum_check_bits
{
200 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
201 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
202 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
204 enum sum_check_flags
{
205 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
206 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
211 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
212 * See linux/cpumask.h
214 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
217 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
218 * @memcpy_count: transaction counter
219 * @bytes_transferred: byte counter
222 struct dma_chan_percpu
{
224 unsigned long memcpy_count
;
225 unsigned long bytes_transferred
;
229 * struct dma_router - DMA router structure
230 * @dev: pointer to the DMA router device
231 * @route_free: function to be called when the route can be disconnected
235 void (*route_free
)(struct device
*dev
, void *route_data
);
239 * struct dma_chan - devices supply DMA channels, clients use them
240 * @device: ptr to the dma device who supplies this channel, always !%NULL
241 * @cookie: last cookie value returned to client
242 * @completed_cookie: last completed cookie for this channel
243 * @chan_id: channel ID for sysfs
244 * @dev: class device for sysfs
245 * @device_node: used to add this to the device chan list
246 * @local: per-cpu pointer to a struct dma_chan_percpu
247 * @client_count: how many clients are using this channel
248 * @table_count: number of appearances in the mem-to-mem allocation table
249 * @router: pointer to the DMA router structure
250 * @route_data: channel specific data for the router
251 * @private: private data for certain client-channel associations
254 struct dma_device
*device
;
256 dma_cookie_t completed_cookie
;
260 struct dma_chan_dev
*dev
;
262 struct list_head device_node
;
263 struct dma_chan_percpu __percpu
*local
;
268 struct dma_router
*router
;
275 * struct dma_chan_dev - relate sysfs device node to backing channel device
276 * @chan: driver channel device
277 * @device: sysfs device
278 * @dev_id: parent dma_device dev_id
279 * @idr_ref: reference count to gate release of dma_device dev_id
281 struct dma_chan_dev
{
282 struct dma_chan
*chan
;
283 struct device device
;
289 * enum dma_slave_buswidth - defines bus width of the DMA slave
290 * device, source or target buses
292 enum dma_slave_buswidth
{
293 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
294 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
295 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
296 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
297 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
298 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
299 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
300 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
301 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
305 * struct dma_slave_config - dma slave channel runtime config
306 * @direction: whether the data shall go in or out on this slave
307 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
308 * legal values. DEPRECATED, drivers should use the direction argument
309 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
310 * the dir field in the dma_interleaved_template structure.
311 * @src_addr: this is the physical address where DMA slave data
312 * should be read (RX), if the source is memory this argument is
314 * @dst_addr: this is the physical address where DMA slave data
315 * should be written (TX), if the source is memory this argument
317 * @src_addr_width: this is the width in bytes of the source (RX)
318 * register where DMA data shall be read. If the source
319 * is memory this may be ignored depending on architecture.
320 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
321 * @dst_addr_width: same as src_addr_width but for destination
322 * target (TX) mutatis mutandis.
323 * @src_maxburst: the maximum number of words (note: words, as in
324 * units of the src_addr_width member, not bytes) that can be sent
325 * in one burst to the device. Typically something like half the
326 * FIFO depth on I/O peripherals so you don't overflow it. This
327 * may or may not be applicable on memory sources.
328 * @dst_maxburst: same as src_maxburst but for destination target
330 * @src_port_window_size: The length of the register area in words the data need
331 * to be accessed on the device side. It is only used for devices which is using
332 * an area instead of a single register to receive the data. Typically the DMA
333 * loops in this area in order to transfer the data.
334 * @dst_port_window_size: same as src_port_window_size but for the destination
336 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
337 * with 'true' if peripheral should be flow controller. Direction will be
338 * selected at Runtime.
339 * @slave_id: Slave requester id. Only valid for slave channels. The dma
340 * slave peripheral will have unique id as dma requester which need to be
341 * pass as slave config.
343 * This struct is passed in as configuration data to a DMA engine
344 * in order to set up a certain channel for DMA transport at runtime.
345 * The DMA device/engine has to provide support for an additional
346 * callback in the dma_device structure, device_config and this struct
347 * will then be passed in as an argument to the function.
349 * The rationale for adding configuration information to this struct is as
350 * follows: if it is likely that more than one DMA slave controllers in
351 * the world will support the configuration option, then make it generic.
352 * If not: if it is fixed so that it be sent in static from the platform
353 * data, then prefer to do that.
355 struct dma_slave_config
{
356 enum dma_transfer_direction direction
;
357 phys_addr_t src_addr
;
358 phys_addr_t dst_addr
;
359 enum dma_slave_buswidth src_addr_width
;
360 enum dma_slave_buswidth dst_addr_width
;
363 u32 src_port_window_size
;
364 u32 dst_port_window_size
;
366 unsigned int slave_id
;
370 * enum dma_residue_granularity - Granularity of the reported transfer residue
371 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
372 * DMA channel is only able to tell whether a descriptor has been completed or
373 * not, which means residue reporting is not supported by this channel. The
374 * residue field of the dma_tx_state field will always be 0.
375 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
376 * completed segment of the transfer (For cyclic transfers this is after each
377 * period). This is typically implemented by having the hardware generate an
378 * interrupt after each transferred segment and then the drivers updates the
379 * outstanding residue by the size of the segment. Another possibility is if
380 * the hardware supports scatter-gather and the segment descriptor has a field
381 * which gets set after the segment has been completed. The driver then counts
382 * the number of segments without the flag set to compute the residue.
383 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
384 * burst. This is typically only supported if the hardware has a progress
385 * register of some sort (E.g. a register with the current read/write address
386 * or a register with the amount of bursts/beats/bytes that have been
387 * transferred or still need to be transferred).
389 enum dma_residue_granularity
{
390 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
391 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
392 DMA_RESIDUE_GRANULARITY_BURST
= 2,
396 * struct dma_slave_caps - expose capabilities of a slave channel only
397 * @src_addr_widths: bit mask of src addr widths the channel supports.
398 * Width is specified in bytes, e.g. for a channel supporting
399 * a width of 4 the mask should have BIT(4) set.
400 * @dst_addr_widths: bit mask of dst addr widths the channel supports
401 * @directions: bit mask of slave directions the channel supports.
402 * Since the enum dma_transfer_direction is not defined as bit flag for
403 * each type, the dma controller should set BIT(<TYPE>) and same
404 * should be checked by controller as well
405 * @max_burst: max burst capability per-transfer
406 * @cmd_pause: true, if pause is supported (i.e. for reading residue or
408 * @cmd_resume: true, if resume is supported
409 * @cmd_terminate: true, if terminate cmd is supported
410 * @residue_granularity: granularity of the reported transfer residue
411 * @descriptor_reuse: if a descriptor can be reused by client and
412 * resubmitted multiple times
414 struct dma_slave_caps
{
422 enum dma_residue_granularity residue_granularity
;
423 bool descriptor_reuse
;
426 static inline const char *dma_chan_name(struct dma_chan
*chan
)
428 return dev_name(&chan
->dev
->device
);
431 void dma_chan_cleanup(struct kref
*kref
);
434 * typedef dma_filter_fn - callback filter for dma_request_channel
435 * @chan: channel to be reviewed
436 * @filter_param: opaque parameter passed through dma_request_channel
438 * When this optional parameter is specified in a call to dma_request_channel a
439 * suitable channel is passed to this routine for further dispositioning before
440 * being returned. Where 'suitable' indicates a non-busy channel that
441 * satisfies the given capability mask. It returns 'true' to indicate that the
442 * channel is suitable.
444 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
446 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
448 enum dmaengine_tx_result
{
449 DMA_TRANS_NOERROR
= 0, /* SUCCESS */
450 DMA_TRANS_READ_FAILED
, /* Source DMA read failed */
451 DMA_TRANS_WRITE_FAILED
, /* Destination DMA write failed */
452 DMA_TRANS_ABORTED
, /* Op never submitted / aborted */
455 struct dmaengine_result
{
456 enum dmaengine_tx_result result
;
460 typedef void (*dma_async_tx_callback_result
)(void *dma_async_param
,
461 const struct dmaengine_result
*result
);
463 struct dmaengine_unmap_data
{
464 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
479 * struct dma_async_tx_descriptor - async transaction descriptor
480 * ---dma generic offload fields---
481 * @cookie: tracking cookie for this transaction, set to -EBUSY if
482 * this tx is sitting on a dependency list
483 * @flags: flags to augment operation preparation, control completion, and
485 * @phys: physical address of the descriptor
486 * @chan: target channel for this operation
487 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
488 * descriptor pending. To be pushed on .issue_pending() call
489 * @callback: routine to call after this operation is complete
490 * @callback_param: general parameter to pass to the callback routine
491 * ---async_tx api specific fields---
492 * @next: at completion submit this descriptor
493 * @parent: pointer to the next level up in the dependency chain
494 * @lock: protect the parent and next pointers
496 struct dma_async_tx_descriptor
{
498 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
500 struct dma_chan
*chan
;
501 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
502 int (*desc_free
)(struct dma_async_tx_descriptor
*tx
);
503 dma_async_tx_callback callback
;
504 dma_async_tx_callback_result callback_result
;
505 void *callback_param
;
506 struct dmaengine_unmap_data
*unmap
;
507 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
508 struct dma_async_tx_descriptor
*next
;
509 struct dma_async_tx_descriptor
*parent
;
514 #ifdef CONFIG_DMA_ENGINE
515 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
516 struct dmaengine_unmap_data
*unmap
)
518 kref_get(&unmap
->kref
);
522 struct dmaengine_unmap_data
*
523 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
524 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
526 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
527 struct dmaengine_unmap_data
*unmap
)
530 static inline struct dmaengine_unmap_data
*
531 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
535 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
540 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
543 dmaengine_unmap_put(tx
->unmap
);
548 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
549 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
552 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
555 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
559 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
562 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
565 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
569 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
575 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
577 spin_lock_bh(&txd
->lock
);
579 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
581 spin_unlock_bh(&txd
->lock
);
583 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
588 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
592 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
596 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
600 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
607 * struct dma_tx_state - filled in to report the status of
609 * @last: last completed DMA cookie
610 * @used: last issued DMA cookie (i.e. the one in progress)
611 * @residue: the remaining number of bytes left to transmit
612 * on the selected transfer for states DMA_IN_PROGRESS and
613 * DMA_PAUSED if this is implemented in the driver, else 0
615 struct dma_tx_state
{
622 * enum dmaengine_alignment - defines alignment of the DMA async tx
625 enum dmaengine_alignment
{
626 DMAENGINE_ALIGN_1_BYTE
= 0,
627 DMAENGINE_ALIGN_2_BYTES
= 1,
628 DMAENGINE_ALIGN_4_BYTES
= 2,
629 DMAENGINE_ALIGN_8_BYTES
= 3,
630 DMAENGINE_ALIGN_16_BYTES
= 4,
631 DMAENGINE_ALIGN_32_BYTES
= 5,
632 DMAENGINE_ALIGN_64_BYTES
= 6,
636 * struct dma_slave_map - associates slave device and it's slave channel with
637 * parameter to be used by a filter function
638 * @devname: name of the device
639 * @slave: slave channel name
640 * @param: opaque parameter to pass to struct dma_filter.fn
642 struct dma_slave_map
{
649 * struct dma_filter - information for slave device/channel to filter_fn/param
651 * @fn: filter function callback
652 * @mapcnt: number of slave device/channel in the map
653 * @map: array of channel to filter mapping data
658 const struct dma_slave_map
*map
;
662 * struct dma_device - info on the entity supplying DMA services
663 * @chancnt: how many DMA channels are supported
664 * @privatecnt: how many DMA channels are requested by dma_request_channel
665 * @channels: the list of struct dma_chan
666 * @global_node: list_head for global dma_device_list
667 * @filter: information for device/slave to filter function/param mapping
668 * @cap_mask: one or more dma_capability flags
669 * @max_xor: maximum number of xor sources, 0 if no capability
670 * @max_pq: maximum number of PQ sources and PQ-continue capability
671 * @copy_align: alignment shift for memcpy operations
672 * @xor_align: alignment shift for xor operations
673 * @pq_align: alignment shift for pq operations
674 * @fill_align: alignment shift for memset operations
675 * @dev_id: unique device ID
676 * @dev: struct device reference for dma mapping api
677 * @src_addr_widths: bit mask of src addr widths the device supports
678 * Width is specified in bytes, e.g. for a device supporting
679 * a width of 4 the mask should have BIT(4) set.
680 * @dst_addr_widths: bit mask of dst addr widths the device supports
681 * @directions: bit mask of slave directions the device supports.
682 * Since the enum dma_transfer_direction is not defined as bit flag for
683 * each type, the dma controller should set BIT(<TYPE>) and same
684 * should be checked by controller as well
685 * @max_burst: max burst capability per-transfer
686 * @residue_granularity: granularity of the transfer residue reported
688 * @device_alloc_chan_resources: allocate resources and return the
689 * number of allocated descriptors
690 * @device_free_chan_resources: release DMA channel's resources
691 * @device_prep_dma_memcpy: prepares a memcpy operation
692 * @device_prep_dma_xor: prepares a xor operation
693 * @device_prep_dma_xor_val: prepares a xor validation operation
694 * @device_prep_dma_pq: prepares a pq operation
695 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
696 * @device_prep_dma_memset: prepares a memset operation
697 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
698 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
699 * @device_prep_slave_sg: prepares a slave dma operation
700 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
701 * The function takes a buffer of size buf_len. The callback function will
702 * be called after period_len bytes have been transferred.
703 * @device_prep_interleaved_dma: Transfer expression in a generic way.
704 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
705 * @device_config: Pushes a new configuration to a channel, return 0 or an error
707 * @device_pause: Pauses any transfer happening on a channel. Returns
709 * @device_resume: Resumes any transfer on a channel previously
710 * paused. Returns 0 or an error code
711 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
713 * @device_synchronize: Synchronizes the termination of a transfers to the
715 * @device_tx_status: poll for transaction completion, the optional
716 * txstate parameter can be supplied with a pointer to get a
717 * struct with auxiliary transfer status information, otherwise the call
718 * will just return a simple status code
719 * @device_issue_pending: push pending transactions to hardware
720 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
724 unsigned int chancnt
;
725 unsigned int privatecnt
;
726 struct list_head channels
;
727 struct list_head global_node
;
728 struct dma_filter filter
;
729 dma_cap_mask_t cap_mask
;
730 unsigned short max_xor
;
731 unsigned short max_pq
;
732 enum dmaengine_alignment copy_align
;
733 enum dmaengine_alignment xor_align
;
734 enum dmaengine_alignment pq_align
;
735 enum dmaengine_alignment fill_align
;
736 #define DMA_HAS_PQ_CONTINUE (1 << 15)
745 bool descriptor_reuse
;
746 enum dma_residue_granularity residue_granularity
;
748 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
749 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
751 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
752 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
753 size_t len
, unsigned long flags
);
754 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
755 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
756 unsigned int src_cnt
, size_t len
, unsigned long flags
);
757 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
758 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
759 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
760 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
761 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
762 unsigned int src_cnt
, const unsigned char *scf
,
763 size_t len
, unsigned long flags
);
764 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
765 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
766 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
767 enum sum_check_flags
*pqres
, unsigned long flags
);
768 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
769 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
770 unsigned long flags
);
771 struct dma_async_tx_descriptor
*(*device_prep_dma_memset_sg
)(
772 struct dma_chan
*chan
, struct scatterlist
*sg
,
773 unsigned int nents
, int value
, unsigned long flags
);
774 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
775 struct dma_chan
*chan
, unsigned long flags
);
777 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
778 struct dma_chan
*chan
, struct scatterlist
*sgl
,
779 unsigned int sg_len
, enum dma_transfer_direction direction
,
780 unsigned long flags
, void *context
);
781 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
782 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
783 size_t period_len
, enum dma_transfer_direction direction
,
784 unsigned long flags
);
785 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
786 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
787 unsigned long flags
);
788 struct dma_async_tx_descriptor
*(*device_prep_dma_imm_data
)(
789 struct dma_chan
*chan
, dma_addr_t dst
, u64 data
,
790 unsigned long flags
);
792 int (*device_config
)(struct dma_chan
*chan
,
793 struct dma_slave_config
*config
);
794 int (*device_pause
)(struct dma_chan
*chan
);
795 int (*device_resume
)(struct dma_chan
*chan
);
796 int (*device_terminate_all
)(struct dma_chan
*chan
);
797 void (*device_synchronize
)(struct dma_chan
*chan
);
799 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
801 struct dma_tx_state
*txstate
);
802 void (*device_issue_pending
)(struct dma_chan
*chan
);
805 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
806 struct dma_slave_config
*config
)
808 if (chan
->device
->device_config
)
809 return chan
->device
->device_config(chan
, config
);
814 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
816 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
819 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
820 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
821 enum dma_transfer_direction dir
, unsigned long flags
)
823 struct scatterlist sg
;
824 sg_init_table(&sg
, 1);
825 sg_dma_address(&sg
) = buf
;
826 sg_dma_len(&sg
) = len
;
828 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
831 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
835 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
836 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
837 enum dma_transfer_direction dir
, unsigned long flags
)
839 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
842 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
846 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
848 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
849 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
850 enum dma_transfer_direction dir
, unsigned long flags
,
851 struct rio_dma_ext
*rio_ext
)
853 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
856 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
857 dir
, flags
, rio_ext
);
861 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
862 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
863 size_t period_len
, enum dma_transfer_direction dir
,
866 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_cyclic
)
869 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
870 period_len
, dir
, flags
);
873 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
874 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
877 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_interleaved_dma
)
880 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
883 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memset(
884 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
887 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_memset
)
890 return chan
->device
->device_prep_dma_memset(chan
, dest
, value
,
894 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memcpy(
895 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
896 size_t len
, unsigned long flags
)
898 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_memcpy
)
901 return chan
->device
->device_prep_dma_memcpy(chan
, dest
, src
,
906 * dmaengine_terminate_all() - Terminate all active DMA transfers
907 * @chan: The channel for which to terminate the transfers
909 * This function is DEPRECATED use either dmaengine_terminate_sync() or
910 * dmaengine_terminate_async() instead.
912 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
914 if (chan
->device
->device_terminate_all
)
915 return chan
->device
->device_terminate_all(chan
);
921 * dmaengine_terminate_async() - Terminate all active DMA transfers
922 * @chan: The channel for which to terminate the transfers
924 * Calling this function will terminate all active and pending descriptors
925 * that have previously been submitted to the channel. It is not guaranteed
926 * though that the transfer for the active descriptor has stopped when the
927 * function returns. Furthermore it is possible the complete callback of a
928 * submitted transfer is still running when this function returns.
930 * dmaengine_synchronize() needs to be called before it is safe to free
931 * any memory that is accessed by previously submitted descriptors or before
932 * freeing any resources accessed from within the completion callback of any
933 * perviously submitted descriptors.
935 * This function can be called from atomic context as well as from within a
936 * complete callback of a descriptor submitted on the same channel.
938 * If none of the two conditions above apply consider using
939 * dmaengine_terminate_sync() instead.
941 static inline int dmaengine_terminate_async(struct dma_chan
*chan
)
943 if (chan
->device
->device_terminate_all
)
944 return chan
->device
->device_terminate_all(chan
);
950 * dmaengine_synchronize() - Synchronize DMA channel termination
951 * @chan: The channel to synchronize
953 * Synchronizes to the DMA channel termination to the current context. When this
954 * function returns it is guaranteed that all transfers for previously issued
955 * descriptors have stopped and and it is safe to free the memory assoicated
956 * with them. Furthermore it is guaranteed that all complete callback functions
957 * for a previously submitted descriptor have finished running and it is safe to
958 * free resources accessed from within the complete callbacks.
960 * The behavior of this function is undefined if dma_async_issue_pending() has
961 * been called between dmaengine_terminate_async() and this function.
963 * This function must only be called from non-atomic context and must not be
964 * called from within a complete callback of a descriptor submitted on the same
967 static inline void dmaengine_synchronize(struct dma_chan
*chan
)
971 if (chan
->device
->device_synchronize
)
972 chan
->device
->device_synchronize(chan
);
976 * dmaengine_terminate_sync() - Terminate all active DMA transfers
977 * @chan: The channel for which to terminate the transfers
979 * Calling this function will terminate all active and pending transfers
980 * that have previously been submitted to the channel. It is similar to
981 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
982 * stopped and that all complete callbacks have finished running when the
985 * This function must only be called from non-atomic context and must not be
986 * called from within a complete callback of a descriptor submitted on the same
989 static inline int dmaengine_terminate_sync(struct dma_chan
*chan
)
993 ret
= dmaengine_terminate_async(chan
);
997 dmaengine_synchronize(chan
);
1002 static inline int dmaengine_pause(struct dma_chan
*chan
)
1004 if (chan
->device
->device_pause
)
1005 return chan
->device
->device_pause(chan
);
1010 static inline int dmaengine_resume(struct dma_chan
*chan
)
1012 if (chan
->device
->device_resume
)
1013 return chan
->device
->device_resume(chan
);
1018 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
1019 dma_cookie_t cookie
, struct dma_tx_state
*state
)
1021 return chan
->device
->device_tx_status(chan
, cookie
, state
);
1024 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
1026 return desc
->tx_submit(desc
);
1029 static inline bool dmaengine_check_align(enum dmaengine_alignment align
,
1030 size_t off1
, size_t off2
, size_t len
)
1036 mask
= (1 << align
) - 1;
1037 if (mask
& (off1
| off2
| len
))
1042 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
1043 size_t off2
, size_t len
)
1045 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
1048 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
1049 size_t off2
, size_t len
)
1051 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
1054 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
1055 size_t off2
, size_t len
)
1057 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
1060 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
1061 size_t off2
, size_t len
)
1063 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
1067 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
1069 dma
->max_pq
= maxpq
;
1070 if (has_pq_continue
)
1071 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
1074 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
1076 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
1079 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
1081 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
1083 return (flags
& mask
) == mask
;
1086 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
1088 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
1091 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
1093 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
1096 /* dma_maxpq - reduce maxpq in the face of continued operations
1097 * @dma - dma device with PQ capability
1098 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1100 * When an engine does not support native continuation we need 3 extra
1101 * source slots to reuse P and Q with the following coefficients:
1102 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1103 * 2/ {01} * Q : use Q to continue Q' calculation
1104 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1106 * In the case where P is disabled we only need 1 extra source:
1107 * 1/ {01} * Q : use Q to continue Q' calculation
1109 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
1111 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
1112 return dma_dev_to_maxpq(dma
);
1113 else if (dmaf_p_disabled_continue(flags
))
1114 return dma_dev_to_maxpq(dma
) - 1;
1115 else if (dmaf_continue(flags
))
1116 return dma_dev_to_maxpq(dma
) - 3;
1120 static inline size_t dmaengine_get_icg(bool inc
, bool sgl
, size_t icg
,
1133 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template
*xt
,
1134 struct data_chunk
*chunk
)
1136 return dmaengine_get_icg(xt
->dst_inc
, xt
->dst_sgl
,
1137 chunk
->icg
, chunk
->dst_icg
);
1140 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template
*xt
,
1141 struct data_chunk
*chunk
)
1143 return dmaengine_get_icg(xt
->src_inc
, xt
->src_sgl
,
1144 chunk
->icg
, chunk
->src_icg
);
1147 /* --- public DMA engine API --- */
1149 #ifdef CONFIG_DMA_ENGINE
1150 void dmaengine_get(void);
1151 void dmaengine_put(void);
1153 static inline void dmaengine_get(void)
1156 static inline void dmaengine_put(void)
1161 #ifdef CONFIG_ASYNC_TX_DMA
1162 #define async_dmaengine_get() dmaengine_get()
1163 #define async_dmaengine_put() dmaengine_put()
1164 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1165 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1167 #define async_dma_find_channel(type) dma_find_channel(type)
1168 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1170 static inline void async_dmaengine_get(void)
1173 static inline void async_dmaengine_put(void)
1176 static inline struct dma_chan
*
1177 async_dma_find_channel(enum dma_transaction_type type
)
1181 #endif /* CONFIG_ASYNC_TX_DMA */
1182 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
1183 struct dma_chan
*chan
);
1185 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
1187 tx
->flags
|= DMA_CTRL_ACK
;
1190 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
1192 tx
->flags
&= ~DMA_CTRL_ACK
;
1195 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
1197 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
1200 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1202 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1204 set_bit(tx_type
, dstp
->bits
);
1207 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1209 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1211 clear_bit(tx_type
, dstp
->bits
);
1214 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1215 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
1217 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
1220 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1222 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
1224 return test_bit(tx_type
, srcp
->bits
);
1227 #define for_each_dma_cap_mask(cap, mask) \
1228 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1231 * dma_async_issue_pending - flush pending transactions to HW
1232 * @chan: target DMA channel
1234 * This allows drivers to push copies to HW in batches,
1235 * reducing MMIO writes where possible.
1237 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
1239 chan
->device
->device_issue_pending(chan
);
1243 * dma_async_is_tx_complete - poll for transaction completion
1244 * @chan: DMA channel
1245 * @cookie: transaction identifier to check status of
1246 * @last: returns last completed cookie, can be NULL
1247 * @used: returns last issued cookie, can be NULL
1249 * If @last and @used are passed in, upon return they reflect the driver
1250 * internal state and can be used with dma_async_is_complete() to check
1251 * the status of multiple cookies without re-checking hardware state.
1253 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
1254 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
1256 struct dma_tx_state state
;
1257 enum dma_status status
;
1259 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1268 * dma_async_is_complete - test a cookie against chan state
1269 * @cookie: transaction identifier to test status of
1270 * @last_complete: last know completed transaction
1271 * @last_used: last cookie value handed out
1273 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1274 * the test logic is separated for lightweight testing of multiple cookies
1276 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1277 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1279 if (last_complete
<= last_used
) {
1280 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1281 return DMA_COMPLETE
;
1283 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1284 return DMA_COMPLETE
;
1286 return DMA_IN_PROGRESS
;
1290 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1295 st
->residue
= residue
;
1299 #ifdef CONFIG_DMA_ENGINE
1300 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1301 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1302 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1303 void dma_issue_pending_all(void);
1304 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1305 dma_filter_fn fn
, void *fn_param
);
1306 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1308 struct dma_chan
*dma_request_chan(struct device
*dev
, const char *name
);
1309 struct dma_chan
*dma_request_chan_by_mask(const dma_cap_mask_t
*mask
);
1311 void dma_release_channel(struct dma_chan
*chan
);
1312 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1314 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1318 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1320 return DMA_COMPLETE
;
1322 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1324 return DMA_COMPLETE
;
1326 static inline void dma_issue_pending_all(void)
1329 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1330 dma_filter_fn fn
, void *fn_param
)
1334 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1339 static inline struct dma_chan
*dma_request_chan(struct device
*dev
,
1342 return ERR_PTR(-ENODEV
);
1344 static inline struct dma_chan
*dma_request_chan_by_mask(
1345 const dma_cap_mask_t
*mask
)
1347 return ERR_PTR(-ENODEV
);
1349 static inline void dma_release_channel(struct dma_chan
*chan
)
1352 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1353 struct dma_slave_caps
*caps
)
1359 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1361 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor
*tx
)
1363 struct dma_slave_caps caps
;
1365 dma_get_slave_caps(tx
->chan
, &caps
);
1367 if (caps
.descriptor_reuse
) {
1368 tx
->flags
|= DMA_CTRL_REUSE
;
1375 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor
*tx
)
1377 tx
->flags
&= ~DMA_CTRL_REUSE
;
1380 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor
*tx
)
1382 return (tx
->flags
& DMA_CTRL_REUSE
) == DMA_CTRL_REUSE
;
1385 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor
*desc
)
1387 /* this is supported for reusable desc, so check that */
1388 if (dmaengine_desc_test_reuse(desc
))
1389 return desc
->desc_free(desc
);
1394 /* --- DMA device --- */
1396 int dma_async_device_register(struct dma_device
*device
);
1397 int dmaenginem_async_device_register(struct dma_device
*device
);
1398 void dma_async_device_unregister(struct dma_device
*device
);
1399 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1400 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1401 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1402 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1403 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1404 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1406 static inline struct dma_chan
1407 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1408 dma_filter_fn fn
, void *fn_param
,
1409 struct device
*dev
, const char *name
)
1411 struct dma_chan
*chan
;
1413 chan
= dma_request_slave_channel(dev
, name
);
1417 if (!fn
|| !fn_param
)
1420 return __dma_request_channel(mask
, fn
, fn_param
);
1422 #endif /* DMAENGINE_H */