2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
17 #ifndef LINUX_DMAENGINE_H
18 #define LINUX_DMAENGINE_H
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/uio.h>
23 #include <linux/bug.h>
24 #include <linux/scatterlist.h>
25 #include <linux/bitmap.h>
26 #include <linux/types.h>
30 * typedef dma_cookie_t - an opaque DMA cookie
32 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
34 typedef s32 dma_cookie_t
;
35 #define DMA_MIN_COOKIE 1
37 static inline int dma_submit_error(dma_cookie_t cookie
)
39 return cookie
< 0 ? cookie
: 0;
43 * enum dma_status - DMA transaction status
44 * @DMA_COMPLETE: transaction completed
45 * @DMA_IN_PROGRESS: transaction not yet processed
46 * @DMA_PAUSED: transaction is paused
47 * @DMA_ERROR: transaction failed
57 * enum dma_transaction_type - DMA transaction types/indexes
59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
60 * automatically set as dma devices are registered.
62 enum dma_transaction_type
{
76 /* last transaction type for creation of the capabilities mask */
81 * enum dma_transfer_direction - dma transfer mode and direction indicator
82 * @DMA_MEM_TO_MEM: Async/Memcpy mode
83 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
84 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
85 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
87 enum dma_transfer_direction
{
96 * Interleaved Transfer Request
97 * ----------------------------
98 * A chunk is collection of contiguous bytes to be transfered.
99 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100 * ICGs may or maynot change between chunks.
101 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102 * that when repeated an integral number of times, specifies the transfer.
103 * A transfer template is specification of a Frame, the number of times
104 * it is to be repeated and other per-transfer attributes.
106 * Practically, a client driver would have ready a template for each
107 * type of transfer it is going to need during its lifetime and
108 * set only 'src_start' and 'dst_start' before submitting the requests.
111 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
112 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
119 * struct data_chunk - Element of scatter-gather list that makes a frame.
120 * @size: Number of bytes to read from source.
121 * size_dst := fn(op, size_src), so doesn't mean much for destination.
122 * @icg: Number of bytes to jump after last src/dst address of this
123 * chunk and before first src/dst address for next chunk.
124 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
126 * @dst_icg: Number of bytes to jump after last dst address of this
127 * chunk and before the first dst address for next chunk.
128 * Ignored if dst_inc is true and dst_sgl is false.
129 * @src_icg: Number of bytes to jump after last src address of this
130 * chunk and before the first src address for next chunk.
131 * Ignored if src_inc is true and src_sgl is false.
141 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
143 * @src_start: Bus address of source for the first chunk.
144 * @dst_start: Bus address of destination for the first chunk.
145 * @dir: Specifies the type of Source and Destination.
146 * @src_inc: If the source address increments after reading from it.
147 * @dst_inc: If the destination address increments after writing to it.
148 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
149 * Otherwise, source is read contiguously (icg ignored).
150 * Ignored if src_inc is false.
151 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
152 * Otherwise, destination is filled contiguously (icg ignored).
153 * Ignored if dst_inc is false.
154 * @numf: Number of frames in this template.
155 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
156 * @sgl: Array of {chunk,icg} pairs that make up a frame.
158 struct dma_interleaved_template
{
159 dma_addr_t src_start
;
160 dma_addr_t dst_start
;
161 enum dma_transfer_direction dir
;
168 struct data_chunk sgl
[0];
172 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
173 * control completion, and communicate status.
174 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
176 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
177 * acknowledges receipt, i.e. has has a chance to establish any dependency
179 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
180 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
181 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
182 * sources that were the result of a previous operation, in the case of a PQ
183 * operation it continues the calculation with new sources
184 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
185 * on the result of this operation
186 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
188 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
189 * data and the descriptor should be in different format from normal
192 enum dma_ctrl_flags
{
193 DMA_PREP_INTERRUPT
= (1 << 0),
194 DMA_CTRL_ACK
= (1 << 1),
195 DMA_PREP_PQ_DISABLE_P
= (1 << 2),
196 DMA_PREP_PQ_DISABLE_Q
= (1 << 3),
197 DMA_PREP_CONTINUE
= (1 << 4),
198 DMA_PREP_FENCE
= (1 << 5),
199 DMA_CTRL_REUSE
= (1 << 6),
200 DMA_PREP_CMD
= (1 << 7),
204 * enum sum_check_bits - bit position of pq_check_flags
206 enum sum_check_bits
{
212 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
213 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
214 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
216 enum sum_check_flags
{
217 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
218 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
223 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
224 * See linux/cpumask.h
226 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
229 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
230 * @memcpy_count: transaction counter
231 * @bytes_transferred: byte counter
234 struct dma_chan_percpu
{
236 unsigned long memcpy_count
;
237 unsigned long bytes_transferred
;
241 * struct dma_router - DMA router structure
242 * @dev: pointer to the DMA router device
243 * @route_free: function to be called when the route can be disconnected
247 void (*route_free
)(struct device
*dev
, void *route_data
);
251 * struct dma_chan - devices supply DMA channels, clients use them
252 * @device: ptr to the dma device who supplies this channel, always !%NULL
253 * @cookie: last cookie value returned to client
254 * @completed_cookie: last completed cookie for this channel
255 * @chan_id: channel ID for sysfs
256 * @dev: class device for sysfs
257 * @device_node: used to add this to the device chan list
258 * @local: per-cpu pointer to a struct dma_chan_percpu
259 * @client_count: how many clients are using this channel
260 * @table_count: number of appearances in the mem-to-mem allocation table
261 * @router: pointer to the DMA router structure
262 * @route_data: channel specific data for the router
263 * @private: private data for certain client-channel associations
266 struct dma_device
*device
;
268 dma_cookie_t completed_cookie
;
272 struct dma_chan_dev
*dev
;
274 struct list_head device_node
;
275 struct dma_chan_percpu __percpu
*local
;
280 struct dma_router
*router
;
287 * struct dma_chan_dev - relate sysfs device node to backing channel device
288 * @chan: driver channel device
289 * @device: sysfs device
290 * @dev_id: parent dma_device dev_id
291 * @idr_ref: reference count to gate release of dma_device dev_id
293 struct dma_chan_dev
{
294 struct dma_chan
*chan
;
295 struct device device
;
301 * enum dma_slave_buswidth - defines bus width of the DMA slave
302 * device, source or target buses
304 enum dma_slave_buswidth
{
305 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
306 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
307 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
308 DMA_SLAVE_BUSWIDTH_3_BYTES
= 3,
309 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
310 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
311 DMA_SLAVE_BUSWIDTH_16_BYTES
= 16,
312 DMA_SLAVE_BUSWIDTH_32_BYTES
= 32,
313 DMA_SLAVE_BUSWIDTH_64_BYTES
= 64,
317 * struct dma_slave_config - dma slave channel runtime config
318 * @direction: whether the data shall go in or out on this slave
319 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
320 * legal values. DEPRECATED, drivers should use the direction argument
321 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
322 * the dir field in the dma_interleaved_template structure.
323 * @src_addr: this is the physical address where DMA slave data
324 * should be read (RX), if the source is memory this argument is
326 * @dst_addr: this is the physical address where DMA slave data
327 * should be written (TX), if the source is memory this argument
329 * @src_addr_width: this is the width in bytes of the source (RX)
330 * register where DMA data shall be read. If the source
331 * is memory this may be ignored depending on architecture.
332 * Legal values: 1, 2, 4, 8.
333 * @dst_addr_width: same as src_addr_width but for destination
334 * target (TX) mutatis mutandis.
335 * @src_maxburst: the maximum number of words (note: words, as in
336 * units of the src_addr_width member, not bytes) that can be sent
337 * in one burst to the device. Typically something like half the
338 * FIFO depth on I/O peripherals so you don't overflow it. This
339 * may or may not be applicable on memory sources.
340 * @dst_maxburst: same as src_maxburst but for destination target
342 * @src_port_window_size: The length of the register area in words the data need
343 * to be accessed on the device side. It is only used for devices which is using
344 * an area instead of a single register to receive the data. Typically the DMA
345 * loops in this area in order to transfer the data.
346 * @dst_port_window_size: same as src_port_window_size but for the destination
348 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
349 * with 'true' if peripheral should be flow controller. Direction will be
350 * selected at Runtime.
351 * @slave_id: Slave requester id. Only valid for slave channels. The dma
352 * slave peripheral will have unique id as dma requester which need to be
353 * pass as slave config.
355 * This struct is passed in as configuration data to a DMA engine
356 * in order to set up a certain channel for DMA transport at runtime.
357 * The DMA device/engine has to provide support for an additional
358 * callback in the dma_device structure, device_config and this struct
359 * will then be passed in as an argument to the function.
361 * The rationale for adding configuration information to this struct is as
362 * follows: if it is likely that more than one DMA slave controllers in
363 * the world will support the configuration option, then make it generic.
364 * If not: if it is fixed so that it be sent in static from the platform
365 * data, then prefer to do that.
367 struct dma_slave_config
{
368 enum dma_transfer_direction direction
;
369 phys_addr_t src_addr
;
370 phys_addr_t dst_addr
;
371 enum dma_slave_buswidth src_addr_width
;
372 enum dma_slave_buswidth dst_addr_width
;
375 u32 src_port_window_size
;
376 u32 dst_port_window_size
;
378 unsigned int slave_id
;
382 * enum dma_residue_granularity - Granularity of the reported transfer residue
383 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
384 * DMA channel is only able to tell whether a descriptor has been completed or
385 * not, which means residue reporting is not supported by this channel. The
386 * residue field of the dma_tx_state field will always be 0.
387 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
388 * completed segment of the transfer (For cyclic transfers this is after each
389 * period). This is typically implemented by having the hardware generate an
390 * interrupt after each transferred segment and then the drivers updates the
391 * outstanding residue by the size of the segment. Another possibility is if
392 * the hardware supports scatter-gather and the segment descriptor has a field
393 * which gets set after the segment has been completed. The driver then counts
394 * the number of segments without the flag set to compute the residue.
395 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
396 * burst. This is typically only supported if the hardware has a progress
397 * register of some sort (E.g. a register with the current read/write address
398 * or a register with the amount of bursts/beats/bytes that have been
399 * transferred or still need to be transferred).
401 enum dma_residue_granularity
{
402 DMA_RESIDUE_GRANULARITY_DESCRIPTOR
= 0,
403 DMA_RESIDUE_GRANULARITY_SEGMENT
= 1,
404 DMA_RESIDUE_GRANULARITY_BURST
= 2,
407 /* struct dma_slave_caps - expose capabilities of a slave channel only
409 * @src_addr_widths: bit mask of src addr widths the channel supports
410 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
411 * @directions: bit mask of slave direction the channel supported
412 * since the enum dma_transfer_direction is not defined as bits for each
413 * type of direction, the dma controller should fill (1 << <TYPE>) and same
414 * should be checked by controller as well
415 * @max_burst: max burst capability per-transfer
416 * @cmd_pause: true, if pause and thereby resume is supported
417 * @cmd_terminate: true, if terminate cmd is supported
418 * @residue_granularity: granularity of the reported transfer residue
419 * @descriptor_reuse: if a descriptor can be reused by client and
420 * resubmitted multiple times
422 struct dma_slave_caps
{
429 enum dma_residue_granularity residue_granularity
;
430 bool descriptor_reuse
;
433 static inline const char *dma_chan_name(struct dma_chan
*chan
)
435 return dev_name(&chan
->dev
->device
);
438 void dma_chan_cleanup(struct kref
*kref
);
441 * typedef dma_filter_fn - callback filter for dma_request_channel
442 * @chan: channel to be reviewed
443 * @filter_param: opaque parameter passed through dma_request_channel
445 * When this optional parameter is specified in a call to dma_request_channel a
446 * suitable channel is passed to this routine for further dispositioning before
447 * being returned. Where 'suitable' indicates a non-busy channel that
448 * satisfies the given capability mask. It returns 'true' to indicate that the
449 * channel is suitable.
451 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
453 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
455 enum dmaengine_tx_result
{
456 DMA_TRANS_NOERROR
= 0, /* SUCCESS */
457 DMA_TRANS_READ_FAILED
, /* Source DMA read failed */
458 DMA_TRANS_WRITE_FAILED
, /* Destination DMA write failed */
459 DMA_TRANS_ABORTED
, /* Op never submitted / aborted */
462 struct dmaengine_result
{
463 enum dmaengine_tx_result result
;
467 typedef void (*dma_async_tx_callback_result
)(void *dma_async_param
,
468 const struct dmaengine_result
*result
);
470 struct dmaengine_unmap_data
{
482 * struct dma_async_tx_descriptor - async transaction descriptor
483 * ---dma generic offload fields---
484 * @cookie: tracking cookie for this transaction, set to -EBUSY if
485 * this tx is sitting on a dependency list
486 * @flags: flags to augment operation preparation, control completion, and
488 * @phys: physical address of the descriptor
489 * @chan: target channel for this operation
490 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
491 * descriptor pending. To be pushed on .issue_pending() call
492 * @callback: routine to call after this operation is complete
493 * @callback_param: general parameter to pass to the callback routine
494 * ---async_tx api specific fields---
495 * @next: at completion submit this descriptor
496 * @parent: pointer to the next level up in the dependency chain
497 * @lock: protect the parent and next pointers
499 struct dma_async_tx_descriptor
{
501 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
503 struct dma_chan
*chan
;
504 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
505 int (*desc_free
)(struct dma_async_tx_descriptor
*tx
);
506 dma_async_tx_callback callback
;
507 dma_async_tx_callback_result callback_result
;
508 void *callback_param
;
509 struct dmaengine_unmap_data
*unmap
;
510 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
511 struct dma_async_tx_descriptor
*next
;
512 struct dma_async_tx_descriptor
*parent
;
517 #ifdef CONFIG_DMA_ENGINE
518 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
519 struct dmaengine_unmap_data
*unmap
)
521 kref_get(&unmap
->kref
);
525 struct dmaengine_unmap_data
*
526 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
);
527 void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
);
529 static inline void dma_set_unmap(struct dma_async_tx_descriptor
*tx
,
530 struct dmaengine_unmap_data
*unmap
)
533 static inline struct dmaengine_unmap_data
*
534 dmaengine_get_unmap_data(struct device
*dev
, int nr
, gfp_t flags
)
538 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data
*unmap
)
543 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor
*tx
)
546 dmaengine_unmap_put(tx
->unmap
);
551 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
552 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
555 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
558 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
562 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
565 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
568 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
572 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
578 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
580 spin_lock_bh(&txd
->lock
);
582 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
584 spin_unlock_bh(&txd
->lock
);
586 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
591 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
595 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
599 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
603 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
610 * struct dma_tx_state - filled in to report the status of
612 * @last: last completed DMA cookie
613 * @used: last issued DMA cookie (i.e. the one in progress)
614 * @residue: the remaining number of bytes left to transmit
615 * on the selected transfer for states DMA_IN_PROGRESS and
616 * DMA_PAUSED if this is implemented in the driver, else 0
618 struct dma_tx_state
{
625 * enum dmaengine_alignment - defines alignment of the DMA async tx
628 enum dmaengine_alignment
{
629 DMAENGINE_ALIGN_1_BYTE
= 0,
630 DMAENGINE_ALIGN_2_BYTES
= 1,
631 DMAENGINE_ALIGN_4_BYTES
= 2,
632 DMAENGINE_ALIGN_8_BYTES
= 3,
633 DMAENGINE_ALIGN_16_BYTES
= 4,
634 DMAENGINE_ALIGN_32_BYTES
= 5,
635 DMAENGINE_ALIGN_64_BYTES
= 6,
639 * struct dma_slave_map - associates slave device and it's slave channel with
640 * parameter to be used by a filter function
641 * @devname: name of the device
642 * @slave: slave channel name
643 * @param: opaque parameter to pass to struct dma_filter.fn
645 struct dma_slave_map
{
652 * struct dma_filter - information for slave device/channel to filter_fn/param
654 * @fn: filter function callback
655 * @mapcnt: number of slave device/channel in the map
656 * @map: array of channel to filter mapping data
661 const struct dma_slave_map
*map
;
665 * struct dma_device - info on the entity supplying DMA services
666 * @chancnt: how many DMA channels are supported
667 * @privatecnt: how many DMA channels are requested by dma_request_channel
668 * @channels: the list of struct dma_chan
669 * @global_node: list_head for global dma_device_list
670 * @filter: information for device/slave to filter function/param mapping
671 * @cap_mask: one or more dma_capability flags
672 * @max_xor: maximum number of xor sources, 0 if no capability
673 * @max_pq: maximum number of PQ sources and PQ-continue capability
674 * @copy_align: alignment shift for memcpy operations
675 * @xor_align: alignment shift for xor operations
676 * @pq_align: alignment shift for pq operations
677 * @fill_align: alignment shift for memset operations
678 * @dev_id: unique device ID
679 * @dev: struct device reference for dma mapping api
680 * @src_addr_widths: bit mask of src addr widths the device supports
681 * @dst_addr_widths: bit mask of dst addr widths the device supports
682 * @directions: bit mask of slave direction the device supports since
683 * the enum dma_transfer_direction is not defined as bits for
684 * each type of direction, the dma controller should fill (1 <<
685 * <TYPE>) and same should be checked by controller as well
686 * @max_burst: max burst capability per-transfer
687 * @residue_granularity: granularity of the transfer residue reported
689 * @device_alloc_chan_resources: allocate resources and return the
690 * number of allocated descriptors
691 * @device_free_chan_resources: release DMA channel's resources
692 * @device_prep_dma_memcpy: prepares a memcpy operation
693 * @device_prep_dma_xor: prepares a xor operation
694 * @device_prep_dma_xor_val: prepares a xor validation operation
695 * @device_prep_dma_pq: prepares a pq operation
696 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
697 * @device_prep_dma_memset: prepares a memset operation
698 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
699 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
700 * @device_prep_slave_sg: prepares a slave dma operation
701 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
702 * The function takes a buffer of size buf_len. The callback function will
703 * be called after period_len bytes have been transferred.
704 * @device_prep_interleaved_dma: Transfer expression in a generic way.
705 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
706 * @device_config: Pushes a new configuration to a channel, return 0 or an error
708 * @device_pause: Pauses any transfer happening on a channel. Returns
710 * @device_resume: Resumes any transfer on a channel previously
711 * paused. Returns 0 or an error code
712 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
714 * @device_synchronize: Synchronizes the termination of a transfers to the
716 * @device_tx_status: poll for transaction completion, the optional
717 * txstate parameter can be supplied with a pointer to get a
718 * struct with auxiliary transfer status information, otherwise the call
719 * will just return a simple status code
720 * @device_issue_pending: push pending transactions to hardware
721 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
725 unsigned int chancnt
;
726 unsigned int privatecnt
;
727 struct list_head channels
;
728 struct list_head global_node
;
729 struct dma_filter filter
;
730 dma_cap_mask_t cap_mask
;
731 unsigned short max_xor
;
732 unsigned short max_pq
;
733 enum dmaengine_alignment copy_align
;
734 enum dmaengine_alignment xor_align
;
735 enum dmaengine_alignment pq_align
;
736 enum dmaengine_alignment fill_align
;
737 #define DMA_HAS_PQ_CONTINUE (1 << 15)
746 bool descriptor_reuse
;
747 enum dma_residue_granularity residue_granularity
;
749 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
750 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
752 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
753 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
754 size_t len
, unsigned long flags
);
755 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
756 struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
757 unsigned int src_cnt
, size_t len
, unsigned long flags
);
758 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
759 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
760 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
761 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
762 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
763 unsigned int src_cnt
, const unsigned char *scf
,
764 size_t len
, unsigned long flags
);
765 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
766 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
767 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
768 enum sum_check_flags
*pqres
, unsigned long flags
);
769 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
770 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
771 unsigned long flags
);
772 struct dma_async_tx_descriptor
*(*device_prep_dma_memset_sg
)(
773 struct dma_chan
*chan
, struct scatterlist
*sg
,
774 unsigned int nents
, int value
, unsigned long flags
);
775 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
776 struct dma_chan
*chan
, unsigned long flags
);
778 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
779 struct dma_chan
*chan
, struct scatterlist
*sgl
,
780 unsigned int sg_len
, enum dma_transfer_direction direction
,
781 unsigned long flags
, void *context
);
782 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
783 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
784 size_t period_len
, enum dma_transfer_direction direction
,
785 unsigned long flags
);
786 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
787 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
788 unsigned long flags
);
789 struct dma_async_tx_descriptor
*(*device_prep_dma_imm_data
)(
790 struct dma_chan
*chan
, dma_addr_t dst
, u64 data
,
791 unsigned long flags
);
793 int (*device_config
)(struct dma_chan
*chan
,
794 struct dma_slave_config
*config
);
795 int (*device_pause
)(struct dma_chan
*chan
);
796 int (*device_resume
)(struct dma_chan
*chan
);
797 int (*device_terminate_all
)(struct dma_chan
*chan
);
798 void (*device_synchronize
)(struct dma_chan
*chan
);
800 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
802 struct dma_tx_state
*txstate
);
803 void (*device_issue_pending
)(struct dma_chan
*chan
);
806 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
807 struct dma_slave_config
*config
)
809 if (chan
->device
->device_config
)
810 return chan
->device
->device_config(chan
, config
);
815 static inline bool is_slave_direction(enum dma_transfer_direction direction
)
817 return (direction
== DMA_MEM_TO_DEV
) || (direction
== DMA_DEV_TO_MEM
);
820 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
821 struct dma_chan
*chan
, dma_addr_t buf
, size_t len
,
822 enum dma_transfer_direction dir
, unsigned long flags
)
824 struct scatterlist sg
;
825 sg_init_table(&sg
, 1);
826 sg_dma_address(&sg
) = buf
;
827 sg_dma_len(&sg
) = len
;
829 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
832 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1,
836 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_sg(
837 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
838 enum dma_transfer_direction dir
, unsigned long flags
)
840 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
843 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
847 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
849 static inline struct dma_async_tx_descriptor
*dmaengine_prep_rio_sg(
850 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
851 enum dma_transfer_direction dir
, unsigned long flags
,
852 struct rio_dma_ext
*rio_ext
)
854 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_slave_sg
)
857 return chan
->device
->device_prep_slave_sg(chan
, sgl
, sg_len
,
858 dir
, flags
, rio_ext
);
862 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_cyclic(
863 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
864 size_t period_len
, enum dma_transfer_direction dir
,
867 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_cyclic
)
870 return chan
->device
->device_prep_dma_cyclic(chan
, buf_addr
, buf_len
,
871 period_len
, dir
, flags
);
874 static inline struct dma_async_tx_descriptor
*dmaengine_prep_interleaved_dma(
875 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
878 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_interleaved_dma
)
881 return chan
->device
->device_prep_interleaved_dma(chan
, xt
, flags
);
884 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memset(
885 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
888 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_memset
)
891 return chan
->device
->device_prep_dma_memset(chan
, dest
, value
,
895 static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_memcpy(
896 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
897 size_t len
, unsigned long flags
)
899 if (!chan
|| !chan
->device
|| !chan
->device
->device_prep_dma_memcpy
)
902 return chan
->device
->device_prep_dma_memcpy(chan
, dest
, src
,
907 * dmaengine_terminate_all() - Terminate all active DMA transfers
908 * @chan: The channel for which to terminate the transfers
910 * This function is DEPRECATED use either dmaengine_terminate_sync() or
911 * dmaengine_terminate_async() instead.
913 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
915 if (chan
->device
->device_terminate_all
)
916 return chan
->device
->device_terminate_all(chan
);
922 * dmaengine_terminate_async() - Terminate all active DMA transfers
923 * @chan: The channel for which to terminate the transfers
925 * Calling this function will terminate all active and pending descriptors
926 * that have previously been submitted to the channel. It is not guaranteed
927 * though that the transfer for the active descriptor has stopped when the
928 * function returns. Furthermore it is possible the complete callback of a
929 * submitted transfer is still running when this function returns.
931 * dmaengine_synchronize() needs to be called before it is safe to free
932 * any memory that is accessed by previously submitted descriptors or before
933 * freeing any resources accessed from within the completion callback of any
934 * perviously submitted descriptors.
936 * This function can be called from atomic context as well as from within a
937 * complete callback of a descriptor submitted on the same channel.
939 * If none of the two conditions above apply consider using
940 * dmaengine_terminate_sync() instead.
942 static inline int dmaengine_terminate_async(struct dma_chan
*chan
)
944 if (chan
->device
->device_terminate_all
)
945 return chan
->device
->device_terminate_all(chan
);
951 * dmaengine_synchronize() - Synchronize DMA channel termination
952 * @chan: The channel to synchronize
954 * Synchronizes to the DMA channel termination to the current context. When this
955 * function returns it is guaranteed that all transfers for previously issued
956 * descriptors have stopped and and it is safe to free the memory assoicated
957 * with them. Furthermore it is guaranteed that all complete callback functions
958 * for a previously submitted descriptor have finished running and it is safe to
959 * free resources accessed from within the complete callbacks.
961 * The behavior of this function is undefined if dma_async_issue_pending() has
962 * been called between dmaengine_terminate_async() and this function.
964 * This function must only be called from non-atomic context and must not be
965 * called from within a complete callback of a descriptor submitted on the same
968 static inline void dmaengine_synchronize(struct dma_chan
*chan
)
972 if (chan
->device
->device_synchronize
)
973 chan
->device
->device_synchronize(chan
);
977 * dmaengine_terminate_sync() - Terminate all active DMA transfers
978 * @chan: The channel for which to terminate the transfers
980 * Calling this function will terminate all active and pending transfers
981 * that have previously been submitted to the channel. It is similar to
982 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
983 * stopped and that all complete callbacks have finished running when the
986 * This function must only be called from non-atomic context and must not be
987 * called from within a complete callback of a descriptor submitted on the same
990 static inline int dmaengine_terminate_sync(struct dma_chan
*chan
)
994 ret
= dmaengine_terminate_async(chan
);
998 dmaengine_synchronize(chan
);
1003 static inline int dmaengine_pause(struct dma_chan
*chan
)
1005 if (chan
->device
->device_pause
)
1006 return chan
->device
->device_pause(chan
);
1011 static inline int dmaengine_resume(struct dma_chan
*chan
)
1013 if (chan
->device
->device_resume
)
1014 return chan
->device
->device_resume(chan
);
1019 static inline enum dma_status
dmaengine_tx_status(struct dma_chan
*chan
,
1020 dma_cookie_t cookie
, struct dma_tx_state
*state
)
1022 return chan
->device
->device_tx_status(chan
, cookie
, state
);
1025 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
1027 return desc
->tx_submit(desc
);
1030 static inline bool dmaengine_check_align(enum dmaengine_alignment align
,
1031 size_t off1
, size_t off2
, size_t len
)
1037 mask
= (1 << align
) - 1;
1038 if (mask
& (off1
| off2
| len
))
1043 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
1044 size_t off2
, size_t len
)
1046 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
1049 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
1050 size_t off2
, size_t len
)
1052 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
1055 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
1056 size_t off2
, size_t len
)
1058 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
1061 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
1062 size_t off2
, size_t len
)
1064 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
1068 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
1070 dma
->max_pq
= maxpq
;
1071 if (has_pq_continue
)
1072 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
1075 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
1077 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
1080 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
1082 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
1084 return (flags
& mask
) == mask
;
1087 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
1089 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
1092 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
1094 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
1097 /* dma_maxpq - reduce maxpq in the face of continued operations
1098 * @dma - dma device with PQ capability
1099 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1101 * When an engine does not support native continuation we need 3 extra
1102 * source slots to reuse P and Q with the following coefficients:
1103 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1104 * 2/ {01} * Q : use Q to continue Q' calculation
1105 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1107 * In the case where P is disabled we only need 1 extra source:
1108 * 1/ {01} * Q : use Q to continue Q' calculation
1110 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
1112 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
1113 return dma_dev_to_maxpq(dma
);
1114 else if (dmaf_p_disabled_continue(flags
))
1115 return dma_dev_to_maxpq(dma
) - 1;
1116 else if (dmaf_continue(flags
))
1117 return dma_dev_to_maxpq(dma
) - 3;
1121 static inline size_t dmaengine_get_icg(bool inc
, bool sgl
, size_t icg
,
1134 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template
*xt
,
1135 struct data_chunk
*chunk
)
1137 return dmaengine_get_icg(xt
->dst_inc
, xt
->dst_sgl
,
1138 chunk
->icg
, chunk
->dst_icg
);
1141 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template
*xt
,
1142 struct data_chunk
*chunk
)
1144 return dmaengine_get_icg(xt
->src_inc
, xt
->src_sgl
,
1145 chunk
->icg
, chunk
->src_icg
);
1148 /* --- public DMA engine API --- */
1150 #ifdef CONFIG_DMA_ENGINE
1151 void dmaengine_get(void);
1152 void dmaengine_put(void);
1154 static inline void dmaengine_get(void)
1157 static inline void dmaengine_put(void)
1162 #ifdef CONFIG_ASYNC_TX_DMA
1163 #define async_dmaengine_get() dmaengine_get()
1164 #define async_dmaengine_put() dmaengine_put()
1165 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1166 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1168 #define async_dma_find_channel(type) dma_find_channel(type)
1169 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1171 static inline void async_dmaengine_get(void)
1174 static inline void async_dmaengine_put(void)
1177 static inline struct dma_chan
*
1178 async_dma_find_channel(enum dma_transaction_type type
)
1182 #endif /* CONFIG_ASYNC_TX_DMA */
1183 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
1184 struct dma_chan
*chan
);
1186 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
1188 tx
->flags
|= DMA_CTRL_ACK
;
1191 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
1193 tx
->flags
&= ~DMA_CTRL_ACK
;
1196 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
1198 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
1201 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1203 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1205 set_bit(tx_type
, dstp
->bits
);
1208 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1210 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
1212 clear_bit(tx_type
, dstp
->bits
);
1215 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1216 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
1218 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
1221 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1223 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
1225 return test_bit(tx_type
, srcp
->bits
);
1228 #define for_each_dma_cap_mask(cap, mask) \
1229 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1232 * dma_async_issue_pending - flush pending transactions to HW
1233 * @chan: target DMA channel
1235 * This allows drivers to push copies to HW in batches,
1236 * reducing MMIO writes where possible.
1238 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
1240 chan
->device
->device_issue_pending(chan
);
1244 * dma_async_is_tx_complete - poll for transaction completion
1245 * @chan: DMA channel
1246 * @cookie: transaction identifier to check status of
1247 * @last: returns last completed cookie, can be NULL
1248 * @used: returns last issued cookie, can be NULL
1250 * If @last and @used are passed in, upon return they reflect the driver
1251 * internal state and can be used with dma_async_is_complete() to check
1252 * the status of multiple cookies without re-checking hardware state.
1254 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
1255 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
1257 struct dma_tx_state state
;
1258 enum dma_status status
;
1260 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
1269 * dma_async_is_complete - test a cookie against chan state
1270 * @cookie: transaction identifier to test status of
1271 * @last_complete: last know completed transaction
1272 * @last_used: last cookie value handed out
1274 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1275 * the test logic is separated for lightweight testing of multiple cookies
1277 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
1278 dma_cookie_t last_complete
, dma_cookie_t last_used
)
1280 if (last_complete
<= last_used
) {
1281 if ((cookie
<= last_complete
) || (cookie
> last_used
))
1282 return DMA_COMPLETE
;
1284 if ((cookie
<= last_complete
) && (cookie
> last_used
))
1285 return DMA_COMPLETE
;
1287 return DMA_IN_PROGRESS
;
1291 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
1296 st
->residue
= residue
;
1300 #ifdef CONFIG_DMA_ENGINE
1301 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
1302 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
1303 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
1304 void dma_issue_pending_all(void);
1305 struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1306 dma_filter_fn fn
, void *fn_param
);
1307 struct dma_chan
*dma_request_slave_channel(struct device
*dev
, const char *name
);
1309 struct dma_chan
*dma_request_chan(struct device
*dev
, const char *name
);
1310 struct dma_chan
*dma_request_chan_by_mask(const dma_cap_mask_t
*mask
);
1312 void dma_release_channel(struct dma_chan
*chan
);
1313 int dma_get_slave_caps(struct dma_chan
*chan
, struct dma_slave_caps
*caps
);
1315 static inline struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
)
1319 static inline enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
)
1321 return DMA_COMPLETE
;
1323 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
1325 return DMA_COMPLETE
;
1327 static inline void dma_issue_pending_all(void)
1330 static inline struct dma_chan
*__dma_request_channel(const dma_cap_mask_t
*mask
,
1331 dma_filter_fn fn
, void *fn_param
)
1335 static inline struct dma_chan
*dma_request_slave_channel(struct device
*dev
,
1340 static inline struct dma_chan
*dma_request_chan(struct device
*dev
,
1343 return ERR_PTR(-ENODEV
);
1345 static inline struct dma_chan
*dma_request_chan_by_mask(
1346 const dma_cap_mask_t
*mask
)
1348 return ERR_PTR(-ENODEV
);
1350 static inline void dma_release_channel(struct dma_chan
*chan
)
1353 static inline int dma_get_slave_caps(struct dma_chan
*chan
,
1354 struct dma_slave_caps
*caps
)
1360 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1362 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor
*tx
)
1364 struct dma_slave_caps caps
;
1366 dma_get_slave_caps(tx
->chan
, &caps
);
1368 if (caps
.descriptor_reuse
) {
1369 tx
->flags
|= DMA_CTRL_REUSE
;
1376 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor
*tx
)
1378 tx
->flags
&= ~DMA_CTRL_REUSE
;
1381 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor
*tx
)
1383 return (tx
->flags
& DMA_CTRL_REUSE
) == DMA_CTRL_REUSE
;
1386 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor
*desc
)
1388 /* this is supported for reusable desc, so check that */
1389 if (dmaengine_desc_test_reuse(desc
))
1390 return desc
->desc_free(desc
);
1395 /* --- DMA device --- */
1397 int dma_async_device_register(struct dma_device
*device
);
1398 void dma_async_device_unregister(struct dma_device
*device
);
1399 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
1400 struct dma_chan
*dma_get_slave_channel(struct dma_chan
*chan
);
1401 struct dma_chan
*dma_get_any_slave_channel(struct dma_device
*device
);
1402 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1403 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1404 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1406 static inline struct dma_chan
1407 *__dma_request_slave_channel_compat(const dma_cap_mask_t
*mask
,
1408 dma_filter_fn fn
, void *fn_param
,
1409 struct device
*dev
, const char *name
)
1411 struct dma_chan
*chan
;
1413 chan
= dma_request_slave_channel(dev
, name
);
1417 if (!fn
|| !fn_param
)
1420 return __dma_request_channel(mask
, fn
, fn_param
);
1422 #endif /* DMAENGINE_H */