1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2006, Intel Corporation.
5 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
6 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
12 #include <linux/acpi.h>
13 #include <linux/types.h>
14 #include <linux/msi.h>
15 #include <linux/irqreturn.h>
16 #include <linux/rwsem.h>
17 #include <linux/rculist.h>
19 struct acpi_dmar_header
;
22 # define DMAR_UNITS_SUPPORTED MAX_IO_APICS
24 # define DMAR_UNITS_SUPPORTED 64
28 #define DMAR_INTR_REMAP 0x1
29 #define DMAR_X2APIC_OPT_OUT 0x2
30 #define DMAR_PLATFORM_OPT_IN 0x4
34 struct dmar_dev_scope
{
35 struct device __rcu
*dev
;
40 #ifdef CONFIG_DMAR_TABLE
41 extern struct acpi_table_header
*dmar_tbl
;
42 struct dmar_drhd_unit
{
43 struct list_head list
; /* list of drhd units */
44 struct acpi_dmar_header
*hdr
; /* ACPI header */
45 u64 reg_base_addr
; /* register base address*/
46 struct dmar_dev_scope
*devices
;/* target device array */
47 int devices_cnt
; /* target device count */
48 u16 segment
; /* PCI domain */
49 u8 ignored
:1; /* ignore drhd */
51 u8 gfx_dedicated
:1; /* graphic dedicated */
52 struct intel_iommu
*iommu
;
55 struct dmar_pci_path
{
61 struct dmar_pci_notify_info
{
67 struct dmar_pci_path path
[];
68 } __attribute__((packed
));
70 extern struct rw_semaphore dmar_global_lock
;
71 extern struct list_head dmar_drhd_units
;
73 #define for_each_drhd_unit(drhd) \
74 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
77 #define for_each_active_drhd_unit(drhd) \
78 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
80 if (drhd->ignored) {} else
82 #define for_each_active_iommu(i, drhd) \
83 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
85 if (i=drhd->iommu, drhd->ignored) {} else
87 #define for_each_iommu(i, drhd) \
88 list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
90 if (i=drhd->iommu, 0) {} else
92 static inline bool dmar_rcu_check(void)
94 return rwsem_is_locked(&dmar_global_lock
) ||
95 system_state
== SYSTEM_BOOTING
;
98 #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
100 #define for_each_dev_scope(devs, cnt, i, tmp) \
101 for ((i) = 0; ((tmp) = (i) < (cnt) ? \
102 dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \
105 #define for_each_active_dev_scope(devs, cnt, i, tmp) \
106 for_each_dev_scope((devs), (cnt), (i), (tmp)) \
107 if (!(tmp)) { continue; } else
109 extern int dmar_table_init(void);
110 extern int dmar_dev_scope_init(void);
111 extern void dmar_register_bus_notifier(void);
112 extern int dmar_parse_dev_scope(void *start
, void *end
, int *cnt
,
113 struct dmar_dev_scope
**devices
, u16 segment
);
114 extern void *dmar_alloc_dev_scope(void *start
, void *end
, int *cnt
);
115 extern void dmar_free_dev_scope(struct dmar_dev_scope
**devices
, int *cnt
);
116 extern int dmar_insert_dev_scope(struct dmar_pci_notify_info
*info
,
117 void *start
, void*end
, u16 segment
,
118 struct dmar_dev_scope
*devices
,
120 extern int dmar_remove_dev_scope(struct dmar_pci_notify_info
*info
,
121 u16 segment
, struct dmar_dev_scope
*devices
,
123 /* Intel IOMMU detection */
124 extern int detect_intel_iommu(void);
125 extern int enable_drhd_fault_handling(void);
126 extern int dmar_device_add(acpi_handle handle
);
127 extern int dmar_device_remove(acpi_handle handle
);
129 static inline int dmar_res_noop(struct acpi_dmar_header
*hdr
, void *arg
)
134 #ifdef CONFIG_INTEL_IOMMU
135 extern int iommu_detected
, no_iommu
;
136 extern int intel_iommu_init(void);
137 extern void intel_iommu_shutdown(void);
138 extern int dmar_parse_one_rmrr(struct acpi_dmar_header
*header
, void *arg
);
139 extern int dmar_parse_one_atsr(struct acpi_dmar_header
*header
, void *arg
);
140 extern int dmar_check_one_atsr(struct acpi_dmar_header
*hdr
, void *arg
);
141 extern int dmar_parse_one_satc(struct acpi_dmar_header
*hdr
, void *arg
);
142 extern int dmar_release_one_atsr(struct acpi_dmar_header
*hdr
, void *arg
);
143 extern int dmar_iommu_hotplug(struct dmar_drhd_unit
*dmaru
, bool insert
);
144 extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info
*info
);
145 #else /* !CONFIG_INTEL_IOMMU: */
146 static inline int intel_iommu_init(void) { return -ENODEV
; }
147 static inline void intel_iommu_shutdown(void) { }
149 #define dmar_parse_one_rmrr dmar_res_noop
150 #define dmar_parse_one_atsr dmar_res_noop
151 #define dmar_check_one_atsr dmar_res_noop
152 #define dmar_release_one_atsr dmar_res_noop
153 #define dmar_parse_one_satc dmar_res_noop
155 static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info
*info
)
160 static inline int dmar_iommu_hotplug(struct dmar_drhd_unit
*dmaru
, bool insert
)
164 #endif /* CONFIG_INTEL_IOMMU */
166 #ifdef CONFIG_IRQ_REMAP
167 extern int dmar_ir_hotplug(struct dmar_drhd_unit
*dmaru
, bool insert
);
168 #else /* CONFIG_IRQ_REMAP */
169 static inline int dmar_ir_hotplug(struct dmar_drhd_unit
*dmaru
, bool insert
)
171 #endif /* CONFIG_IRQ_REMAP */
173 extern bool dmar_platform_optin(void);
175 #else /* CONFIG_DMAR_TABLE */
177 static inline int dmar_device_add(void *handle
)
182 static inline int dmar_device_remove(void *handle
)
187 static inline bool dmar_platform_optin(void)
192 #endif /* CONFIG_DMAR_TABLE */
196 /* Shared between remapped and posted mode*/
198 __u64 present
: 1, /* 0 */
200 __res0
: 6, /* 2 - 6 */
201 avail
: 4, /* 8 - 11 */
202 __res1
: 3, /* 12 - 14 */
204 vector
: 8, /* 16 - 23 */
205 __res2
: 40; /* 24 - 63 */
210 __u64 r_present
: 1, /* 0 */
212 dst_mode
: 1, /* 2 */
213 redir_hint
: 1, /* 3 */
214 trigger_mode
: 1, /* 4 */
215 dlvry_mode
: 3, /* 5 - 7 */
216 r_avail
: 4, /* 8 - 11 */
217 r_res0
: 4, /* 12 - 15 */
218 r_vector
: 8, /* 16 - 23 */
219 r_res1
: 8, /* 24 - 31 */
220 dest_id
: 32; /* 32 - 63 */
225 __u64 p_present
: 1, /* 0 */
227 p_res0
: 6, /* 2 - 7 */
228 p_avail
: 4, /* 8 - 11 */
229 p_res1
: 2, /* 12 - 13 */
230 p_urgent
: 1, /* 14 */
232 p_vector
: 8, /* 16 - 23 */
233 p_res2
: 14, /* 24 - 37 */
234 pda_l
: 26; /* 38 - 63 */
240 /* Shared between remapped and posted mode*/
242 __u64 sid
: 16, /* 64 - 79 */
243 sq
: 2, /* 80 - 81 */
244 svt
: 2, /* 82 - 83 */
245 __res3
: 44; /* 84 - 127 */
250 __u64 p_sid
: 16, /* 64 - 79 */
251 p_sq
: 2, /* 80 - 81 */
252 p_svt
: 2, /* 82 - 83 */
253 p_res3
: 12, /* 84 - 95 */
254 pda_h
: 32; /* 96 - 127 */
260 static inline void dmar_copy_shared_irte(struct irte
*dst
, struct irte
*src
)
262 dst
->present
= src
->present
;
264 dst
->avail
= src
->avail
;
266 dst
->vector
= src
->vector
;
272 #define PDA_LOW_BIT 26
273 #define PDA_HIGH_BIT 32
275 /* Can't use the common MSI interrupt functions
276 * since DMAR is not a pci device
279 extern void dmar_msi_unmask(struct irq_data
*data
);
280 extern void dmar_msi_mask(struct irq_data
*data
);
281 extern void dmar_msi_read(int irq
, struct msi_msg
*msg
);
282 extern void dmar_msi_write(int irq
, struct msi_msg
*msg
);
283 extern int dmar_set_interrupt(struct intel_iommu
*iommu
);
284 extern irqreturn_t
dmar_fault(int irq
, void *dev_id
);
285 extern int dmar_alloc_hwirq(int id
, int node
, void *arg
);
286 extern void dmar_free_hwirq(int irq
);
288 #endif /* __DMAR_H__ */