include/linux/edac.h

   1 /*
   2  * Generic EDAC defs
   3  *
   4  * Author: Dave Jiang <djiang@mvista.com>
   5  *
   6  * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  *
  11  */
  12 #ifndef _LINUX_EDAC_H_
  13 #define _LINUX_EDAC_H_
  14
  15 #include <linux/atomic.h>
  16 #include <linux/device.h>
  17 #include <linux/completion.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/debugfs.h>
  20
  21 #define EDAC_DEVICE_NAME_LEN    31
  22
  23 struct device;
  24
  25 #define EDAC_OPSTATE_INVAL      -1
  26 #define EDAC_OPSTATE_POLL       0
  27 #define EDAC_OPSTATE_NMI        1
  28 #define EDAC_OPSTATE_INT        2
  29
  30 extern int edac_op_state;
  31 extern int edac_err_assert;
  32 extern atomic_t edac_handlers;
  33
  34 extern int edac_handler_set(void);
  35 extern void edac_atomic_assert_error(void);
  36 extern struct bus_type *edac_get_sysfs_subsys(void);
  37
  38 enum {
  39         EDAC_REPORTING_ENABLED,
  40         EDAC_REPORTING_DISABLED,
  41         EDAC_REPORTING_FORCE
  42 };
  43
  44 extern int edac_report_status;
  45 #ifdef CONFIG_EDAC
  46 static inline int get_edac_report_status(void)
  47 {
  48         return edac_report_status;
  49 }
  50
  51 static inline void set_edac_report_status(int new)
  52 {
  53         edac_report_status = new;
  54 }
  55 #else
  56 static inline int get_edac_report_status(void)
  57 {
  58         return EDAC_REPORTING_DISABLED;
  59 }
  60
  61 static inline void set_edac_report_status(int new)
  62 {
  63 }
  64 #endif
  65
  66 static inline void opstate_init(void)
  67 {
  68         switch (edac_op_state) {
  69         case EDAC_OPSTATE_POLL:
  70         case EDAC_OPSTATE_NMI:
  71                 break;
  72         default:
  73                 edac_op_state = EDAC_OPSTATE_POLL;
  74         }
  75         return;
  76 }
  77
  78 /* Max length of a DIMM label*/
  79 #define EDAC_MC_LABEL_LEN       31
  80
  81 /* Maximum size of the location string */
  82 #define LOCATION_SIZE 256
  83
  84 /* Defines the maximum number of labels that can be reported */
  85 #define EDAC_MAX_LABELS         8
  86
  87 /* String used to join two or more labels */
  88 #define OTHER_LABEL " or "
  89
  90 /**
  91  * enum dev_type - describe the type of memory DRAM chips used at the stick
  92  * @DEV_UNKNOWN:        Can't be determined, or MC doesn't support detect it
  93  * @DEV_X1:             1 bit for data
  94  * @DEV_X2:             2 bits for data
  95  * @DEV_X4:             4 bits for data
  96  * @DEV_X8:             8 bits for data
  97  * @DEV_X16:            16 bits for data
  98  * @DEV_X32:            32 bits for data
  99  * @DEV_X64:            64 bits for data
 100  *
 101  * Typical values are x4 and x8.
 102  */
 103 enum dev_type {
 104         DEV_UNKNOWN = 0,
 105         DEV_X1,
 106         DEV_X2,
 107         DEV_X4,
 108         DEV_X8,
 109         DEV_X16,
 110         DEV_X32,                /* Do these parts exist? */
 111         DEV_X64                 /* Do these parts exist? */
 112 };
 113
 114 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 115 #define DEV_FLAG_X1             BIT(DEV_X1)
 116 #define DEV_FLAG_X2             BIT(DEV_X2)
 117 #define DEV_FLAG_X4             BIT(DEV_X4)
 118 #define DEV_FLAG_X8             BIT(DEV_X8)
 119 #define DEV_FLAG_X16            BIT(DEV_X16)
 120 #define DEV_FLAG_X32            BIT(DEV_X32)
 121 #define DEV_FLAG_X64            BIT(DEV_X64)
 122
 123 /**
 124  * enum hw_event_mc_err_type - type of the detected error
 125  *
 126  * @HW_EVENT_ERR_CORRECTED:     Corrected Error - Indicates that an ECC
 127  *                              corrected error was detected
 128  * @HW_EVENT_ERR_UNCORRECTED:   Uncorrected Error - Indicates an error that
 129  *                              can't be corrected by ECC, but it is not
 130  *                              fatal (maybe it is on an unused memory area,
 131  *                              or the memory controller could recover from
 132  *                              it for example, by re-trying the operation).
 133  * @HW_EVENT_ERR_DEFERRED:      Deferred Error - Indicates an uncorrectable
 134  *                              error whose handling is not urgent. This could
 135  *                              be due to hardware data poisoning where the
 136  *                              system can continue operation until the poisoned
 137  *                              data is consumed. Preemptive measures may also
 138  *                              be taken, e.g. offlining pages, etc.
 139  * @HW_EVENT_ERR_FATAL:         Fatal Error - Uncorrected error that could not
 140  *                              be recovered.
 141  * @HW_EVENT_ERR_INFO:          Informational - The CPER spec defines a forth
 142  *                              type of error: informational logs.
 143  */
 144 enum hw_event_mc_err_type {
 145         HW_EVENT_ERR_CORRECTED,
 146         HW_EVENT_ERR_UNCORRECTED,
 147         HW_EVENT_ERR_DEFERRED,
 148         HW_EVENT_ERR_FATAL,
 149         HW_EVENT_ERR_INFO,
 150 };
 151
 152 static inline char *mc_event_error_type(const unsigned int err_type)
 153 {
 154         switch (err_type) {
 155         case HW_EVENT_ERR_CORRECTED:
 156                 return "Corrected";
 157         case HW_EVENT_ERR_UNCORRECTED:
 158                 return "Uncorrected";
 159         case HW_EVENT_ERR_DEFERRED:
 160                 return "Deferred";
 161         case HW_EVENT_ERR_FATAL:
 162                 return "Fatal";
 163         default:
 164         case HW_EVENT_ERR_INFO:
 165                 return "Info";
 166         }
 167 }
 168
 169 /**
 170  * enum mem_type - memory types. For a more detailed reference, please see
 171  *                      http://en.wikipedia.org/wiki/DRAM
 172  *
 173  * @MEM_EMPTY:          Empty csrow
 174  * @MEM_RESERVED:       Reserved csrow type
 175  * @MEM_UNKNOWN:        Unknown csrow type
 176  * @MEM_FPM:            FPM - Fast Page Mode, used on systems up to 1995.
 177  * @MEM_EDO:            EDO - Extended data out, used on systems up to 1998.
 178  * @MEM_BEDO:           BEDO - Burst Extended data out, an EDO variant.
 179  * @MEM_SDR:            SDR - Single data rate SDRAM
 180  *                      http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
 181  *                      They use 3 pins for chip select: Pins 0 and 2 are
 182  *                      for rank 0; pins 1 and 3 are for rank 1, if the memory
 183  *                      is dual-rank.
 184  * @MEM_RDR:            Registered SDR SDRAM
 185  * @MEM_DDR:            Double data rate SDRAM
 186  *                      http://en.wikipedia.org/wiki/DDR_SDRAM
 187  * @MEM_RDDR:           Registered Double data rate SDRAM
 188  *                      This is a variant of the DDR memories.
 189  *                      A registered memory has a buffer inside it, hiding
 190  *                      part of the memory details to the memory controller.
 191  * @MEM_RMBS:           Rambus DRAM, used on a few Pentium III/IV controllers.
 192  * @MEM_DDR2:           DDR2 RAM, as described at JEDEC JESD79-2F.
 193  *                      Those memories are labeled as "PC2-" instead of "PC" to
 194  *                      differentiate from DDR.
 195  * @MEM_FB_DDR2:        Fully-Buffered DDR2, as described at JEDEC Std No. 205
 196  *                      and JESD206.
 197  *                      Those memories are accessed per DIMM slot, and not by
 198  *                      a chip select signal.
 199  * @MEM_RDDR2:          Registered DDR2 RAM
 200  *                      This is a variant of the DDR2 memories.
 201  * @MEM_XDR:            Rambus XDR
 202  *                      It is an evolution of the original RAMBUS memories,
 203  *                      created to compete with DDR2. Weren't used on any
 204  *                      x86 arch, but cell_edac PPC memory controller uses it.
 205  * @MEM_DDR3:           DDR3 RAM
 206  * @MEM_RDDR3:          Registered DDR3 RAM
 207  *                      This is a variant of the DDR3 memories.
 208  * @MEM_LRDDR3:         Load-Reduced DDR3 memory.
 209  * @MEM_DDR4:           Unbuffered DDR4 RAM
 210  * @MEM_RDDR4:          Registered DDR4 RAM
 211  *                      This is a variant of the DDR4 memories.
 212  * @MEM_LRDDR4:         Load-Reduced DDR4 memory.
 213  */
 214 enum mem_type {
 215         MEM_EMPTY = 0,
 216         MEM_RESERVED,
 217         MEM_UNKNOWN,
 218         MEM_FPM,
 219         MEM_EDO,
 220         MEM_BEDO,
 221         MEM_SDR,
 222         MEM_RDR,
 223         MEM_DDR,
 224         MEM_RDDR,
 225         MEM_RMBS,
 226         MEM_DDR2,
 227         MEM_FB_DDR2,
 228         MEM_RDDR2,
 229         MEM_XDR,
 230         MEM_DDR3,
 231         MEM_RDDR3,
 232         MEM_LRDDR3,
 233         MEM_DDR4,
 234         MEM_RDDR4,
 235         MEM_LRDDR4,
 236 };
 237
 238 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 239 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 240 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 241 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 242 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 243 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 244 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 245 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 246 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 247 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 248 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 249 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 250 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 251 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 252 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 253 #define MEM_FLAG_DDR3           BIT(MEM_DDR3)
 254 #define MEM_FLAG_RDDR3          BIT(MEM_RDDR3)
 255 #define MEM_FLAG_DDR4           BIT(MEM_DDR4)
 256 #define MEM_FLAG_RDDR4          BIT(MEM_RDDR4)
 257 #define MEM_FLAG_LRDDR4         BIT(MEM_LRDDR4)
 258
 259 /**
 260  * enum edac-type - Error Detection and Correction capabilities and mode
 261  * @EDAC_UNKNOWN:       Unknown if ECC is available
 262  * @EDAC_NONE:          Doesn't support ECC
 263  * @EDAC_RESERVED:      Reserved ECC type
 264  * @EDAC_PARITY:        Detects parity errors
 265  * @EDAC_EC:            Error Checking - no correction
 266  * @EDAC_SECDED:        Single bit error correction, Double detection
 267  * @EDAC_S2ECD2ED:      Chipkill x2 devices - do these exist?
 268  * @EDAC_S4ECD4ED:      Chipkill x4 devices
 269  * @EDAC_S8ECD8ED:      Chipkill x8 devices
 270  * @EDAC_S16ECD16ED:    Chipkill x16 devices
 271  */
 272 enum edac_type {
 273         EDAC_UNKNOWN =  0,
 274         EDAC_NONE,
 275         EDAC_RESERVED,
 276         EDAC_PARITY,
 277         EDAC_EC,
 278         EDAC_SECDED,
 279         EDAC_S2ECD2ED,
 280         EDAC_S4ECD4ED,
 281         EDAC_S8ECD8ED,
 282         EDAC_S16ECD16ED,
 283 };
 284
 285 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 286 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 287 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 288 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 289 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 290 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 291 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 292 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 293 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 294
 295 /**
 296  * enum scrub_type - scrubbing capabilities
 297  * @SCRUB_UNKNOWN:              Unknown if scrubber is available
 298  * @SCRUB_NONE:                 No scrubber
 299  * @SCRUB_SW_PROG:              SW progressive (sequential) scrubbing
 300  * @SCRUB_SW_SRC:               Software scrub only errors
 301  * @SCRUB_SW_PROG_SRC:          Progressive software scrub from an error
 302  * @SCRUB_SW_TUNABLE:           Software scrub frequency is tunable
 303  * @SCRUB_HW_PROG:              HW progressive (sequential) scrubbing
 304  * @SCRUB_HW_SRC:               Hardware scrub only errors
 305  * @SCRUB_HW_PROG_SRC:          Progressive hardware scrub from an error
 306  * @SCRUB_HW_TUNABLE:           Hardware scrub frequency is tunable
 307  */
 308 enum scrub_type {
 309         SCRUB_UNKNOWN = 0,
 310         SCRUB_NONE,
 311         SCRUB_SW_PROG,
 312         SCRUB_SW_SRC,
 313         SCRUB_SW_PROG_SRC,
 314         SCRUB_SW_TUNABLE,
 315         SCRUB_HW_PROG,
 316         SCRUB_HW_SRC,
 317         SCRUB_HW_PROG_SRC,
 318         SCRUB_HW_TUNABLE
 319 };
 320
 321 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 322 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 323 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 324 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 325 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 326 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 327 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 328 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 329
 330 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 331
 332 /* EDAC internal operation states */
 333 #define OP_ALLOC                0x100
 334 #define OP_RUNNING_POLL         0x201
 335 #define OP_RUNNING_INTERRUPT    0x202
 336 #define OP_RUNNING_POLL_INTR    0x203
 337 #define OP_OFFLINE              0x300
 338
 339 /**
 340  * enum edac_mc_layer - memory controller hierarchy layer
 341  *
 342  * @EDAC_MC_LAYER_BRANCH:       memory layer is named "branch"
 343  * @EDAC_MC_LAYER_CHANNEL:      memory layer is named "channel"
 344  * @EDAC_MC_LAYER_SLOT:         memory layer is named "slot"
 345  * @EDAC_MC_LAYER_CHIP_SELECT:  memory layer is named "chip select"
 346  * @EDAC_MC_LAYER_ALL_MEM:      memory layout is unknown. All memory is mapped
 347  *                              as a single memory area. This is used when
 348  *                              retrieving errors from a firmware driven driver.
 349  *
 350  * This enum is used by the drivers to tell edac_mc_sysfs what name should
 351  * be used when describing a memory stick location.
 352  */
 353 enum edac_mc_layer_type {
 354         EDAC_MC_LAYER_BRANCH,
 355         EDAC_MC_LAYER_CHANNEL,
 356         EDAC_MC_LAYER_SLOT,
 357         EDAC_MC_LAYER_CHIP_SELECT,
 358         EDAC_MC_LAYER_ALL_MEM,
 359 };
 360
 361 /**
 362  * struct edac_mc_layer - describes the memory controller hierarchy
 363  * @type:               layer type
 364  * @size:               number of components per layer. For example,
 365  *                      if the channel layer has two channels, size = 2
 366  * @is_virt_csrow:      This layer is part of the "csrow" when old API
 367  *                      compatibility mode is enabled. Otherwise, it is
 368  *                      a channel
 369  */
 370 struct edac_mc_layer {
 371         enum edac_mc_layer_type type;
 372         unsigned                size;
 373         bool                    is_virt_csrow;
 374 };
 375
 376 /*
 377  * Maximum number of layers used by the memory controller to uniquely
 378  * identify a single memory stick.
 379  * NOTE: Changing this constant requires not only to change the constant
 380  * below, but also to change the existing code at the core, as there are
 381  * some code there that are optimized for 3 layers.
 382  */
 383 #define EDAC_MAX_LAYERS         3
 384
 385 /**
 386  * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer
 387  *                 array for the element given by [layer0,layer1,layer2]
 388  *                 position
 389  *
 390  * @layers:     a struct edac_mc_layer array, describing how many elements
 391  *              were allocated for each layer
 392  * @nlayers:    Number of layers at the @layers array
 393  * @layer0:     layer0 position
 394  * @layer1:     layer1 position. Unused if n_layers < 2
 395  * @layer2:     layer2 position. Unused if n_layers < 3
 396  *
 397  * For 1 layer, this macro returns "var[layer0] - var";
 398  *
 399  * For 2 layers, this macro is similar to allocate a bi-dimensional array
 400  * and to return "var[layer0][layer1] - var";
 401  *
 402  * For 3 layers, this macro is similar to allocate a tri-dimensional array
 403  * and to return "var[layer0][layer1][layer2] - var".
 404  *
 405  * A loop could be used here to make it more generic, but, as we only have
 406  * 3 layers, this is a little faster.
 407  *
 408  * By design, layers can never be 0 or more than 3. If that ever happens,
 409  * a NULL is returned, causing an OOPS during the memory allocation routine,
 410  * with would point to the developer that he's doing something wrong.
 411  */
 412 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({               \
 413         int __i;                                                        \
 414         if ((nlayers) == 1)                                             \
 415                 __i = layer0;                                           \
 416         else if ((nlayers) == 2)                                        \
 417                 __i = (layer1) + ((layers[1]).size * (layer0));         \
 418         else if ((nlayers) == 3)                                        \
 419                 __i = (layer2) + ((layers[2]).size * ((layer1) +        \
 420                             ((layers[1]).size * (layer0))));            \
 421         else                                                            \
 422                 __i = -EINVAL;                                          \
 423         __i;                                                            \
 424 })
 425
 426 /**
 427  * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
 428  *                 for the element given by [layer0,layer1,layer2] position
 429  *
 430  * @layers:     a struct edac_mc_layer array, describing how many elements
 431  *              were allocated for each layer
 432  * @var:        name of the var where we want to get the pointer
 433  *              (like mci->dimms)
 434  * @nlayers:    Number of layers at the @layers array
 435  * @layer0:     layer0 position
 436  * @layer1:     layer1 position. Unused if n_layers < 2
 437  * @layer2:     layer2 position. Unused if n_layers < 3
 438  *
 439  * For 1 layer, this macro returns "var[layer0]";
 440  *
 441  * For 2 layers, this macro is similar to allocate a bi-dimensional array
 442  * and to return "var[layer0][layer1]";
 443  *
 444  * For 3 layers, this macro is similar to allocate a tri-dimensional array
 445  * and to return "var[layer0][layer1][layer2]";
 446  */
 447 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({  \
 448         typeof(*var) __p;                                               \
 449         int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2);      \
 450         if (___i < 0)                                                   \
 451                 __p = NULL;                                             \
 452         else                                                            \
 453                 __p = (var)[___i];                                      \
 454         __p;                                                            \
 455 })
 456
 457 struct dimm_info {
 458         struct device dev;
 459
 460         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 461
 462         /* Memory location data */
 463         unsigned location[EDAC_MAX_LAYERS];
 464
 465         struct mem_ctl_info *mci;       /* the parent */
 466
 467         u32 grain;              /* granularity of reported error in bytes */
 468         enum dev_type dtype;    /* memory device type */
 469         enum mem_type mtype;    /* memory dimm type */
 470         enum edac_type edac_mode;       /* EDAC mode for this dimm */
 471
 472         u32 nr_pages;                   /* number of pages on this dimm */
 473
 474         unsigned csrow, cschannel;      /* Points to the old API data */
 475 };
 476
 477 /**
 478  * struct rank_info - contains the information for one DIMM rank
 479  *
 480  * @chan_idx:   channel number where the rank is (typically, 0 or 1)
 481  * @ce_count:   number of correctable errors for this rank
 482  * @csrow:      A pointer to the chip select row structure (the parent
 483  *              structure). The location of the rank is given by
 484  *              the (csrow->csrow_idx, chan_idx) vector.
 485  * @dimm:       A pointer to the DIMM structure, where the DIMM label
 486  *              information is stored.
 487  *
 488  * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
 489  *        This is a bad assumption, but it makes this patch easier. Later
 490  *        patches in this series will fix this issue.
 491  */
 492 struct rank_info {
 493         int chan_idx;
 494         struct csrow_info *csrow;
 495         struct dimm_info *dimm;
 496
 497         u32 ce_count;           /* Correctable Errors for this csrow */
 498 };
 499
 500 struct csrow_info {
 501         struct device dev;
 502
 503         /* Used only by edac_mc_find_csrow_by_page() */
 504         unsigned long first_page;       /* first page number in csrow */
 505         unsigned long last_page;        /* last page number in csrow */
 506         unsigned long page_mask;        /* used for interleaving -
 507                                          * 0UL for non intlv */
 508
 509         int csrow_idx;                  /* the chip-select row */
 510
 511         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 512         u32 ce_count;           /* Correctable Errors for this csrow */
 513
 514         struct mem_ctl_info *mci;       /* the parent */
 515
 516         /* channel information for this csrow */
 517         u32 nr_channels;
 518         struct rank_info **channels;
 519 };
 520
 521 /*
 522  * struct errcount_attribute - used to store the several error counts
 523  */
 524 struct errcount_attribute_data {
 525         int n_layers;
 526         int pos[EDAC_MAX_LAYERS];
 527         int layer0, layer1, layer2;
 528 };
 529
 530 /**
 531  * struct edac_raw_error_desc - Raw error report structure
 532  * @grain:                      minimum granularity for an error report, in bytes
 533  * @error_count:                number of errors of the same type
 534  * @top_layer:                  top layer of the error (layer[0])
 535  * @mid_layer:                  middle layer of the error (layer[1])
 536  * @low_layer:                  low layer of the error (layer[2])
 537  * @page_frame_number:          page where the error happened
 538  * @offset_in_page:             page offset
 539  * @syndrome:                   syndrome of the error (or 0 if unknown or if
 540  *                              the syndrome is not applicable)
 541  * @msg:                        error message
 542  * @location:                   location of the error
 543  * @label:                      label of the affected DIMM(s)
 544  * @other_detail:               other driver-specific detail about the error
 545  * @enable_per_layer_report:    if false, the error affects all layers
 546  *                              (typically, a memory controller error)
 547  */
 548 struct edac_raw_error_desc {
 549         /*
 550          * NOTE: everything before grain won't be cleaned by
 551          * edac_raw_error_desc_clean()
 552          */
 553         char location[LOCATION_SIZE];
 554         char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
 555         long grain;
 556
 557         /* the vars below and grain will be cleaned on every new error report */
 558         u16 error_count;
 559         int top_layer;
 560         int mid_layer;
 561         int low_layer;
 562         unsigned long page_frame_number;
 563         unsigned long offset_in_page;
 564         unsigned long syndrome;
 565         const char *msg;
 566         const char *other_detail;
 567         bool enable_per_layer_report;
 568 };
 569
 570 /* MEMORY controller information structure
 571  */
 572 struct mem_ctl_info {
 573         struct device                   dev;
 574         struct bus_type                 *bus;
 575
 576         struct list_head link;  /* for global list of mem_ctl_info structs */
 577
 578         struct module *owner;   /* Module owner of this control struct */
 579
 580         unsigned long mtype_cap;        /* memory types supported by mc */
 581         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 582         unsigned long edac_cap; /* configuration capabilities - this is
 583                                  * closely related to edac_ctl_cap.  The
 584                                  * difference is that the controller may be
 585                                  * capable of s4ecd4ed which would be listed
 586                                  * in edac_ctl_cap, but if channels aren't
 587                                  * capable of s4ecd4ed then the edac_cap would
 588                                  * not have that capability.
 589                                  */
 590         unsigned long scrub_cap;        /* chipset scrub capabilities */
 591         enum scrub_type scrub_mode;     /* current scrub mode */
 592
 593         /* Translates sdram memory scrub rate given in bytes/sec to the
 594            internal representation and configures whatever else needs
 595            to be configured.
 596          */
 597         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
 598
 599         /* Get the current sdram memory scrub rate from the internal
 600            representation and converts it to the closest matching
 601            bandwidth in bytes/sec.
 602          */
 603         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
 604
 605
 606         /* pointer to edac checking routine */
 607         void (*edac_check) (struct mem_ctl_info * mci);
 608
 609         /*
 610          * Remaps memory pages: controller pages to physical pages.
 611          * For most MC's, this will be NULL.
 612          */
 613         /* FIXME - why not send the phys page to begin with? */
 614         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 615                                            unsigned long page);
 616         int mc_idx;
 617         struct csrow_info **csrows;
 618         unsigned nr_csrows, num_cschannel;
 619
 620         /*
 621          * Memory Controller hierarchy
 622          *
 623          * There are basically two types of memory controller: the ones that
 624          * sees memory sticks ("dimms"), and the ones that sees memory ranks.
 625          * All old memory controllers enumerate memories per rank, but most
 626          * of the recent drivers enumerate memories per DIMM, instead.
 627          * When the memory controller is per rank, csbased is true.
 628          */
 629         unsigned n_layers;
 630         struct edac_mc_layer *layers;
 631         bool csbased;
 632
 633         /*
 634          * DIMM info. Will eventually remove the entire csrows_info some day
 635          */
 636         unsigned tot_dimms;
 637         struct dimm_info **dimms;
 638
 639         /*
 640          * FIXME - what about controllers on other busses? - IDs must be
 641          * unique.  dev pointer should be sufficiently unique, but
 642          * BUS:SLOT.FUNC numbers may not be unique.
 643          */
 644         struct device *pdev;
 645         const char *mod_name;
 646         const char *mod_ver;
 647         const char *ctl_name;
 648         const char *dev_name;
 649         void *pvt_info;
 650         unsigned long start_time;       /* mci load start time (in jiffies) */
 651
 652         /*
 653          * drivers shouldn't access those fields directly, as the core
 654          * already handles that.
 655          */
 656         u32 ce_noinfo_count, ue_noinfo_count;
 657         u32 ue_mc, ce_mc;
 658         u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
 659
 660         struct completion complete;
 661
 662         /* Additional top controller level attributes, but specified
 663          * by the low level driver.
 664          *
 665          * Set by the low level driver to provide attributes at the
 666          * controller level.
 667          * An array of structures, NULL terminated
 668          *
 669          * If attributes are desired, then set to array of attributes
 670          * If no attributes are desired, leave NULL
 671          */
 672         const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 673
 674         /* work struct for this MC */
 675         struct delayed_work work;
 676
 677         /*
 678          * Used to report an error - by being at the global struct
 679          * makes the memory allocated by the EDAC core
 680          */
 681         struct edac_raw_error_desc error_desc;
 682
 683         /* the internal state of this controller instance */
 684         int op_state;
 685
 686         struct dentry *debugfs;
 687         u8 fake_inject_layer[EDAC_MAX_LAYERS];
 688         bool fake_inject_ue;
 689         u16 fake_inject_count;
 690 };
 691
 692 /*
 693  * Maximum number of memory controllers in the coherent fabric.
 694  */
 695 #define EDAC_MAX_MCS    16
 696
 697 #endif