include/linux/edac.h

   1 /*
   2  * Generic EDAC defs
   3  *
   4  * Author: Dave Jiang <djiang@mvista.com>
   5  *
   6  * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  *
  11  */
  12 #ifndef _LINUX_EDAC_H_
  13 #define _LINUX_EDAC_H_
  14
  15 #include <linux/atomic.h>
  16 #include <linux/device.h>
  17 #include <linux/completion.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/debugfs.h>
  20
  21 #define EDAC_DEVICE_NAME_LEN    31
  22
  23 struct device;
  24
  25 #define EDAC_OPSTATE_INVAL      -1
  26 #define EDAC_OPSTATE_POLL       0
  27 #define EDAC_OPSTATE_NMI        1
  28 #define EDAC_OPSTATE_INT        2
  29
  30 extern int edac_op_state;
  31
  32 struct bus_type *edac_get_sysfs_subsys(void);
  33 int edac_get_report_status(void);
  34 void edac_set_report_status(int new);
  35
  36 enum {
  37         EDAC_REPORTING_ENABLED,
  38         EDAC_REPORTING_DISABLED,
  39         EDAC_REPORTING_FORCE
  40 };
  41
  42 static inline void opstate_init(void)
  43 {
  44         switch (edac_op_state) {
  45         case EDAC_OPSTATE_POLL:
  46         case EDAC_OPSTATE_NMI:
  47                 break;
  48         default:
  49                 edac_op_state = EDAC_OPSTATE_POLL;
  50         }
  51         return;
  52 }
  53
  54 /* Max length of a DIMM label*/
  55 #define EDAC_MC_LABEL_LEN       31
  56
  57 /* Maximum size of the location string */
  58 #define LOCATION_SIZE 256
  59
  60 /* Defines the maximum number of labels that can be reported */
  61 #define EDAC_MAX_LABELS         8
  62
  63 /* String used to join two or more labels */
  64 #define OTHER_LABEL " or "
  65
  66 /**
  67  * enum dev_type - describe the type of memory DRAM chips used at the stick
  68  * @DEV_UNKNOWN:        Can't be determined, or MC doesn't support detect it
  69  * @DEV_X1:             1 bit for data
  70  * @DEV_X2:             2 bits for data
  71  * @DEV_X4:             4 bits for data
  72  * @DEV_X8:             8 bits for data
  73  * @DEV_X16:            16 bits for data
  74  * @DEV_X32:            32 bits for data
  75  * @DEV_X64:            64 bits for data
  76  *
  77  * Typical values are x4 and x8.
  78  */
  79 enum dev_type {
  80         DEV_UNKNOWN = 0,
  81         DEV_X1,
  82         DEV_X2,
  83         DEV_X4,
  84         DEV_X8,
  85         DEV_X16,
  86         DEV_X32,                /* Do these parts exist? */
  87         DEV_X64                 /* Do these parts exist? */
  88 };
  89
  90 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
  91 #define DEV_FLAG_X1             BIT(DEV_X1)
  92 #define DEV_FLAG_X2             BIT(DEV_X2)
  93 #define DEV_FLAG_X4             BIT(DEV_X4)
  94 #define DEV_FLAG_X8             BIT(DEV_X8)
  95 #define DEV_FLAG_X16            BIT(DEV_X16)
  96 #define DEV_FLAG_X32            BIT(DEV_X32)
  97 #define DEV_FLAG_X64            BIT(DEV_X64)
  98
  99 /**
 100  * enum hw_event_mc_err_type - type of the detected error
 101  *
 102  * @HW_EVENT_ERR_CORRECTED:     Corrected Error - Indicates that an ECC
 103  *                              corrected error was detected
 104  * @HW_EVENT_ERR_UNCORRECTED:   Uncorrected Error - Indicates an error that
 105  *                              can't be corrected by ECC, but it is not
 106  *                              fatal (maybe it is on an unused memory area,
 107  *                              or the memory controller could recover from
 108  *                              it for example, by re-trying the operation).
 109  * @HW_EVENT_ERR_DEFERRED:      Deferred Error - Indicates an uncorrectable
 110  *                              error whose handling is not urgent. This could
 111  *                              be due to hardware data poisoning where the
 112  *                              system can continue operation until the poisoned
 113  *                              data is consumed. Preemptive measures may also
 114  *                              be taken, e.g. offlining pages, etc.
 115  * @HW_EVENT_ERR_FATAL:         Fatal Error - Uncorrected error that could not
 116  *                              be recovered.
 117  * @HW_EVENT_ERR_INFO:          Informational - The CPER spec defines a forth
 118  *                              type of error: informational logs.
 119  */
 120 enum hw_event_mc_err_type {
 121         HW_EVENT_ERR_CORRECTED,
 122         HW_EVENT_ERR_UNCORRECTED,
 123         HW_EVENT_ERR_DEFERRED,
 124         HW_EVENT_ERR_FATAL,
 125         HW_EVENT_ERR_INFO,
 126 };
 127
 128 static inline char *mc_event_error_type(const unsigned int err_type)
 129 {
 130         switch (err_type) {
 131         case HW_EVENT_ERR_CORRECTED:
 132                 return "Corrected";
 133         case HW_EVENT_ERR_UNCORRECTED:
 134                 return "Uncorrected";
 135         case HW_EVENT_ERR_DEFERRED:
 136                 return "Deferred";
 137         case HW_EVENT_ERR_FATAL:
 138                 return "Fatal";
 139         default:
 140         case HW_EVENT_ERR_INFO:
 141                 return "Info";
 142         }
 143 }
 144
 145 /**
 146  * enum mem_type - memory types. For a more detailed reference, please see
 147  *                      http://en.wikipedia.org/wiki/DRAM
 148  *
 149  * @MEM_EMPTY:          Empty csrow
 150  * @MEM_RESERVED:       Reserved csrow type
 151  * @MEM_UNKNOWN:        Unknown csrow type
 152  * @MEM_FPM:            FPM - Fast Page Mode, used on systems up to 1995.
 153  * @MEM_EDO:            EDO - Extended data out, used on systems up to 1998.
 154  * @MEM_BEDO:           BEDO - Burst Extended data out, an EDO variant.
 155  * @MEM_SDR:            SDR - Single data rate SDRAM
 156  *                      http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
 157  *                      They use 3 pins for chip select: Pins 0 and 2 are
 158  *                      for rank 0; pins 1 and 3 are for rank 1, if the memory
 159  *                      is dual-rank.
 160  * @MEM_RDR:            Registered SDR SDRAM
 161  * @MEM_DDR:            Double data rate SDRAM
 162  *                      http://en.wikipedia.org/wiki/DDR_SDRAM
 163  * @MEM_RDDR:           Registered Double data rate SDRAM
 164  *                      This is a variant of the DDR memories.
 165  *                      A registered memory has a buffer inside it, hiding
 166  *                      part of the memory details to the memory controller.
 167  * @MEM_RMBS:           Rambus DRAM, used on a few Pentium III/IV controllers.
 168  * @MEM_DDR2:           DDR2 RAM, as described at JEDEC JESD79-2F.
 169  *                      Those memories are labeled as "PC2-" instead of "PC" to
 170  *                      differentiate from DDR.
 171  * @MEM_FB_DDR2:        Fully-Buffered DDR2, as described at JEDEC Std No. 205
 172  *                      and JESD206.
 173  *                      Those memories are accessed per DIMM slot, and not by
 174  *                      a chip select signal.
 175  * @MEM_RDDR2:          Registered DDR2 RAM
 176  *                      This is a variant of the DDR2 memories.
 177  * @MEM_XDR:            Rambus XDR
 178  *                      It is an evolution of the original RAMBUS memories,
 179  *                      created to compete with DDR2. Weren't used on any
 180  *                      x86 arch, but cell_edac PPC memory controller uses it.
 181  * @MEM_DDR3:           DDR3 RAM
 182  * @MEM_RDDR3:          Registered DDR3 RAM
 183  *                      This is a variant of the DDR3 memories.
 184  * @MEM_LRDDR3:         Load-Reduced DDR3 memory.
 185  * @MEM_DDR4:           Unbuffered DDR4 RAM
 186  * @MEM_RDDR4:          Registered DDR4 RAM
 187  *                      This is a variant of the DDR4 memories.
 188  * @MEM_LRDDR4:         Load-Reduced DDR4 memory.
 189  */
 190 enum mem_type {
 191         MEM_EMPTY = 0,
 192         MEM_RESERVED,
 193         MEM_UNKNOWN,
 194         MEM_FPM,
 195         MEM_EDO,
 196         MEM_BEDO,
 197         MEM_SDR,
 198         MEM_RDR,
 199         MEM_DDR,
 200         MEM_RDDR,
 201         MEM_RMBS,
 202         MEM_DDR2,
 203         MEM_FB_DDR2,
 204         MEM_RDDR2,
 205         MEM_XDR,
 206         MEM_DDR3,
 207         MEM_RDDR3,
 208         MEM_LRDDR3,
 209         MEM_DDR4,
 210         MEM_RDDR4,
 211         MEM_LRDDR4,
 212 };
 213
 214 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 215 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 216 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 217 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 218 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 219 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 220 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 221 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 222 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 223 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 224 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 225 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 226 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 227 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 228 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 229 #define MEM_FLAG_DDR3           BIT(MEM_DDR3)
 230 #define MEM_FLAG_RDDR3          BIT(MEM_RDDR3)
 231 #define MEM_FLAG_DDR4           BIT(MEM_DDR4)
 232 #define MEM_FLAG_RDDR4          BIT(MEM_RDDR4)
 233 #define MEM_FLAG_LRDDR4         BIT(MEM_LRDDR4)
 234
 235 /**
 236  * enum edac-type - Error Detection and Correction capabilities and mode
 237  * @EDAC_UNKNOWN:       Unknown if ECC is available
 238  * @EDAC_NONE:          Doesn't support ECC
 239  * @EDAC_RESERVED:      Reserved ECC type
 240  * @EDAC_PARITY:        Detects parity errors
 241  * @EDAC_EC:            Error Checking - no correction
 242  * @EDAC_SECDED:        Single bit error correction, Double detection
 243  * @EDAC_S2ECD2ED:      Chipkill x2 devices - do these exist?
 244  * @EDAC_S4ECD4ED:      Chipkill x4 devices
 245  * @EDAC_S8ECD8ED:      Chipkill x8 devices
 246  * @EDAC_S16ECD16ED:    Chipkill x16 devices
 247  */
 248 enum edac_type {
 249         EDAC_UNKNOWN =  0,
 250         EDAC_NONE,
 251         EDAC_RESERVED,
 252         EDAC_PARITY,
 253         EDAC_EC,
 254         EDAC_SECDED,
 255         EDAC_S2ECD2ED,
 256         EDAC_S4ECD4ED,
 257         EDAC_S8ECD8ED,
 258         EDAC_S16ECD16ED,
 259 };
 260
 261 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 262 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 263 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 264 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 265 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 266 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 267 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 268 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 269 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 270
 271 /**
 272  * enum scrub_type - scrubbing capabilities
 273  * @SCRUB_UNKNOWN:              Unknown if scrubber is available
 274  * @SCRUB_NONE:                 No scrubber
 275  * @SCRUB_SW_PROG:              SW progressive (sequential) scrubbing
 276  * @SCRUB_SW_SRC:               Software scrub only errors
 277  * @SCRUB_SW_PROG_SRC:          Progressive software scrub from an error
 278  * @SCRUB_SW_TUNABLE:           Software scrub frequency is tunable
 279  * @SCRUB_HW_PROG:              HW progressive (sequential) scrubbing
 280  * @SCRUB_HW_SRC:               Hardware scrub only errors
 281  * @SCRUB_HW_PROG_SRC:          Progressive hardware scrub from an error
 282  * @SCRUB_HW_TUNABLE:           Hardware scrub frequency is tunable
 283  */
 284 enum scrub_type {
 285         SCRUB_UNKNOWN = 0,
 286         SCRUB_NONE,
 287         SCRUB_SW_PROG,
 288         SCRUB_SW_SRC,
 289         SCRUB_SW_PROG_SRC,
 290         SCRUB_SW_TUNABLE,
 291         SCRUB_HW_PROG,
 292         SCRUB_HW_SRC,
 293         SCRUB_HW_PROG_SRC,
 294         SCRUB_HW_TUNABLE
 295 };
 296
 297 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 298 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 299 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 300 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 301 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 302 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 303 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 304 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 305
 306 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 307
 308 /* EDAC internal operation states */
 309 #define OP_ALLOC                0x100
 310 #define OP_RUNNING_POLL         0x201
 311 #define OP_RUNNING_INTERRUPT    0x202
 312 #define OP_RUNNING_POLL_INTR    0x203
 313 #define OP_OFFLINE              0x300
 314
 315 /**
 316  * enum edac_mc_layer - memory controller hierarchy layer
 317  *
 318  * @EDAC_MC_LAYER_BRANCH:       memory layer is named "branch"
 319  * @EDAC_MC_LAYER_CHANNEL:      memory layer is named "channel"
 320  * @EDAC_MC_LAYER_SLOT:         memory layer is named "slot"
 321  * @EDAC_MC_LAYER_CHIP_SELECT:  memory layer is named "chip select"
 322  * @EDAC_MC_LAYER_ALL_MEM:      memory layout is unknown. All memory is mapped
 323  *                              as a single memory area. This is used when
 324  *                              retrieving errors from a firmware driven driver.
 325  *
 326  * This enum is used by the drivers to tell edac_mc_sysfs what name should
 327  * be used when describing a memory stick location.
 328  */
 329 enum edac_mc_layer_type {
 330         EDAC_MC_LAYER_BRANCH,
 331         EDAC_MC_LAYER_CHANNEL,
 332         EDAC_MC_LAYER_SLOT,
 333         EDAC_MC_LAYER_CHIP_SELECT,
 334         EDAC_MC_LAYER_ALL_MEM,
 335 };
 336
 337 /**
 338  * struct edac_mc_layer - describes the memory controller hierarchy
 339  * @type:               layer type
 340  * @size:               number of components per layer. For example,
 341  *                      if the channel layer has two channels, size = 2
 342  * @is_virt_csrow:      This layer is part of the "csrow" when old API
 343  *                      compatibility mode is enabled. Otherwise, it is
 344  *                      a channel
 345  */
 346 struct edac_mc_layer {
 347         enum edac_mc_layer_type type;
 348         unsigned                size;
 349         bool                    is_virt_csrow;
 350 };
 351
 352 /*
 353  * Maximum number of layers used by the memory controller to uniquely
 354  * identify a single memory stick.
 355  * NOTE: Changing this constant requires not only to change the constant
 356  * below, but also to change the existing code at the core, as there are
 357  * some code there that are optimized for 3 layers.
 358  */
 359 #define EDAC_MAX_LAYERS         3
 360
 361 /**
 362  * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer
 363  *                 array for the element given by [layer0,layer1,layer2]
 364  *                 position
 365  *
 366  * @layers:     a struct edac_mc_layer array, describing how many elements
 367  *              were allocated for each layer
 368  * @nlayers:    Number of layers at the @layers array
 369  * @layer0:     layer0 position
 370  * @layer1:     layer1 position. Unused if n_layers < 2
 371  * @layer2:     layer2 position. Unused if n_layers < 3
 372  *
 373  * For 1 layer, this macro returns "var[layer0] - var";
 374  *
 375  * For 2 layers, this macro is similar to allocate a bi-dimensional array
 376  * and to return "var[layer0][layer1] - var";
 377  *
 378  * For 3 layers, this macro is similar to allocate a tri-dimensional array
 379  * and to return "var[layer0][layer1][layer2] - var".
 380  *
 381  * A loop could be used here to make it more generic, but, as we only have
 382  * 3 layers, this is a little faster.
 383  *
 384  * By design, layers can never be 0 or more than 3. If that ever happens,
 385  * a NULL is returned, causing an OOPS during the memory allocation routine,
 386  * with would point to the developer that he's doing something wrong.
 387  */
 388 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({               \
 389         int __i;                                                        \
 390         if ((nlayers) == 1)                                             \
 391                 __i = layer0;                                           \
 392         else if ((nlayers) == 2)                                        \
 393                 __i = (layer1) + ((layers[1]).size * (layer0));         \
 394         else if ((nlayers) == 3)                                        \
 395                 __i = (layer2) + ((layers[2]).size * ((layer1) +        \
 396                             ((layers[1]).size * (layer0))));            \
 397         else                                                            \
 398                 __i = -EINVAL;                                          \
 399         __i;                                                            \
 400 })
 401
 402 /**
 403  * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
 404  *                 for the element given by [layer0,layer1,layer2] position
 405  *
 406  * @layers:     a struct edac_mc_layer array, describing how many elements
 407  *              were allocated for each layer
 408  * @var:        name of the var where we want to get the pointer
 409  *              (like mci->dimms)
 410  * @nlayers:    Number of layers at the @layers array
 411  * @layer0:     layer0 position
 412  * @layer1:     layer1 position. Unused if n_layers < 2
 413  * @layer2:     layer2 position. Unused if n_layers < 3
 414  *
 415  * For 1 layer, this macro returns "var[layer0]";
 416  *
 417  * For 2 layers, this macro is similar to allocate a bi-dimensional array
 418  * and to return "var[layer0][layer1]";
 419  *
 420  * For 3 layers, this macro is similar to allocate a tri-dimensional array
 421  * and to return "var[layer0][layer1][layer2]";
 422  */
 423 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({  \
 424         typeof(*var) __p;                                               \
 425         int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2);      \
 426         if (___i < 0)                                                   \
 427                 __p = NULL;                                             \
 428         else                                                            \
 429                 __p = (var)[___i];                                      \
 430         __p;                                                            \
 431 })
 432
 433 struct dimm_info {
 434         struct device dev;
 435
 436         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 437
 438         /* Memory location data */
 439         unsigned location[EDAC_MAX_LAYERS];
 440
 441         struct mem_ctl_info *mci;       /* the parent */
 442
 443         u32 grain;              /* granularity of reported error in bytes */
 444         enum dev_type dtype;    /* memory device type */
 445         enum mem_type mtype;    /* memory dimm type */
 446         enum edac_type edac_mode;       /* EDAC mode for this dimm */
 447
 448         u32 nr_pages;                   /* number of pages on this dimm */
 449
 450         unsigned csrow, cschannel;      /* Points to the old API data */
 451 };
 452
 453 /**
 454  * struct rank_info - contains the information for one DIMM rank
 455  *
 456  * @chan_idx:   channel number where the rank is (typically, 0 or 1)
 457  * @ce_count:   number of correctable errors for this rank
 458  * @csrow:      A pointer to the chip select row structure (the parent
 459  *              structure). The location of the rank is given by
 460  *              the (csrow->csrow_idx, chan_idx) vector.
 461  * @dimm:       A pointer to the DIMM structure, where the DIMM label
 462  *              information is stored.
 463  *
 464  * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
 465  *        This is a bad assumption, but it makes this patch easier. Later
 466  *        patches in this series will fix this issue.
 467  */
 468 struct rank_info {
 469         int chan_idx;
 470         struct csrow_info *csrow;
 471         struct dimm_info *dimm;
 472
 473         u32 ce_count;           /* Correctable Errors for this csrow */
 474 };
 475
 476 struct csrow_info {
 477         struct device dev;
 478
 479         /* Used only by edac_mc_find_csrow_by_page() */
 480         unsigned long first_page;       /* first page number in csrow */
 481         unsigned long last_page;        /* last page number in csrow */
 482         unsigned long page_mask;        /* used for interleaving -
 483                                          * 0UL for non intlv */
 484
 485         int csrow_idx;                  /* the chip-select row */
 486
 487         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 488         u32 ce_count;           /* Correctable Errors for this csrow */
 489
 490         struct mem_ctl_info *mci;       /* the parent */
 491
 492         /* channel information for this csrow */
 493         u32 nr_channels;
 494         struct rank_info **channels;
 495 };
 496
 497 /*
 498  * struct errcount_attribute - used to store the several error counts
 499  */
 500 struct errcount_attribute_data {
 501         int n_layers;
 502         int pos[EDAC_MAX_LAYERS];
 503         int layer0, layer1, layer2;
 504 };
 505
 506 /**
 507  * struct edac_raw_error_desc - Raw error report structure
 508  * @grain:                      minimum granularity for an error report, in bytes
 509  * @error_count:                number of errors of the same type
 510  * @top_layer:                  top layer of the error (layer[0])
 511  * @mid_layer:                  middle layer of the error (layer[1])
 512  * @low_layer:                  low layer of the error (layer[2])
 513  * @page_frame_number:          page where the error happened
 514  * @offset_in_page:             page offset
 515  * @syndrome:                   syndrome of the error (or 0 if unknown or if
 516  *                              the syndrome is not applicable)
 517  * @msg:                        error message
 518  * @location:                   location of the error
 519  * @label:                      label of the affected DIMM(s)
 520  * @other_detail:               other driver-specific detail about the error
 521  * @enable_per_layer_report:    if false, the error affects all layers
 522  *                              (typically, a memory controller error)
 523  */
 524 struct edac_raw_error_desc {
 525         /*
 526          * NOTE: everything before grain won't be cleaned by
 527          * edac_raw_error_desc_clean()
 528          */
 529         char location[LOCATION_SIZE];
 530         char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
 531         long grain;
 532
 533         /* the vars below and grain will be cleaned on every new error report */
 534         u16 error_count;
 535         int top_layer;
 536         int mid_layer;
 537         int low_layer;
 538         unsigned long page_frame_number;
 539         unsigned long offset_in_page;
 540         unsigned long syndrome;
 541         const char *msg;
 542         const char *other_detail;
 543         bool enable_per_layer_report;
 544 };
 545
 546 /* MEMORY controller information structure
 547  */
 548 struct mem_ctl_info {
 549         struct device                   dev;
 550         struct bus_type                 *bus;
 551
 552         struct list_head link;  /* for global list of mem_ctl_info structs */
 553
 554         struct module *owner;   /* Module owner of this control struct */
 555
 556         unsigned long mtype_cap;        /* memory types supported by mc */
 557         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 558         unsigned long edac_cap; /* configuration capabilities - this is
 559                                  * closely related to edac_ctl_cap.  The
 560                                  * difference is that the controller may be
 561                                  * capable of s4ecd4ed which would be listed
 562                                  * in edac_ctl_cap, but if channels aren't
 563                                  * capable of s4ecd4ed then the edac_cap would
 564                                  * not have that capability.
 565                                  */
 566         unsigned long scrub_cap;        /* chipset scrub capabilities */
 567         enum scrub_type scrub_mode;     /* current scrub mode */
 568
 569         /* Translates sdram memory scrub rate given in bytes/sec to the
 570            internal representation and configures whatever else needs
 571            to be configured.
 572          */
 573         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
 574
 575         /* Get the current sdram memory scrub rate from the internal
 576            representation and converts it to the closest matching
 577            bandwidth in bytes/sec.
 578          */
 579         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
 580
 581
 582         /* pointer to edac checking routine */
 583         void (*edac_check) (struct mem_ctl_info * mci);
 584
 585         /*
 586          * Remaps memory pages: controller pages to physical pages.
 587          * For most MC's, this will be NULL.
 588          */
 589         /* FIXME - why not send the phys page to begin with? */
 590         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 591                                            unsigned long page);
 592         int mc_idx;
 593         struct csrow_info **csrows;
 594         unsigned nr_csrows, num_cschannel;
 595
 596         /*
 597          * Memory Controller hierarchy
 598          *
 599          * There are basically two types of memory controller: the ones that
 600          * sees memory sticks ("dimms"), and the ones that sees memory ranks.
 601          * All old memory controllers enumerate memories per rank, but most
 602          * of the recent drivers enumerate memories per DIMM, instead.
 603          * When the memory controller is per rank, csbased is true.
 604          */
 605         unsigned n_layers;
 606         struct edac_mc_layer *layers;
 607         bool csbased;
 608
 609         /*
 610          * DIMM info. Will eventually remove the entire csrows_info some day
 611          */
 612         unsigned tot_dimms;
 613         struct dimm_info **dimms;
 614
 615         /*
 616          * FIXME - what about controllers on other busses? - IDs must be
 617          * unique.  dev pointer should be sufficiently unique, but
 618          * BUS:SLOT.FUNC numbers may not be unique.
 619          */
 620         struct device *pdev;
 621         const char *mod_name;
 622         const char *ctl_name;
 623         const char *dev_name;
 624         void *pvt_info;
 625         unsigned long start_time;       /* mci load start time (in jiffies) */
 626
 627         /*
 628          * drivers shouldn't access those fields directly, as the core
 629          * already handles that.
 630          */
 631         u32 ce_noinfo_count, ue_noinfo_count;
 632         u32 ue_mc, ce_mc;
 633         u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
 634
 635         struct completion complete;
 636
 637         /* Additional top controller level attributes, but specified
 638          * by the low level driver.
 639          *
 640          * Set by the low level driver to provide attributes at the
 641          * controller level.
 642          * An array of structures, NULL terminated
 643          *
 644          * If attributes are desired, then set to array of attributes
 645          * If no attributes are desired, leave NULL
 646          */
 647         const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 648
 649         /* work struct for this MC */
 650         struct delayed_work work;
 651
 652         /*
 653          * Used to report an error - by being at the global struct
 654          * makes the memory allocated by the EDAC core
 655          */
 656         struct edac_raw_error_desc error_desc;
 657
 658         /* the internal state of this controller instance */
 659         int op_state;
 660
 661         struct dentry *debugfs;
 662         u8 fake_inject_layer[EDAC_MAX_LAYERS];
 663         bool fake_inject_ue;
 664         u16 fake_inject_count;
 665 };
 666
 667 /*
 668  * Maximum number of memory controllers in the coherent fabric.
 669  */
 670 #define EDAC_MAX_MCS    16
 671
 672 #endif