2 * twl4030.h - header for TWL4030 PM and audio CODEC device
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/types.h>
29 #include <linux/phy/phy.h>
30 #include <linux/input/matrix_keypad.h>
33 * Using the twl4030 core we address registers using a pair
34 * { module id, relative register offset }
35 * which that core then maps to the relevant
36 * { i2c slave, absolute register address }
38 * The module IDs are meaningful only to the twl4030 core code,
39 * which uses them as array indices to look up the first register
40 * address each module uses within a given i2c slave.
43 /* Module IDs for similar functionalities found in twl4030/twl6030 */
47 TWL_MODULE_MAIN_CHARGE
,
49 TWL_MODULE_PM_RECEIVER
,
54 TWL_MODULE_SECURED_REG
,
59 /* Modules only available in twl4030 series */
60 enum twl4030_module_ids
{
61 TWL4030_MODULE_AUDIO_VOICE
= TWL_MODULE_LAST
,
65 TWL4030_MODULE_KEYPAD
,
68 TWL4030_MODULE_INTERRUPTS
,
69 TWL4030_MODULE_PRECHARGE
,
70 TWL4030_MODULE_BACKUP
,
73 TWL5031_MODULE_ACCESSORY
,
74 TWL5031_MODULE_INTERRUPTS
,
79 /* Modules only available in twl6030 series */
80 enum twl6030_module_ids
{
81 TWL6030_MODULE_ID0
= TWL_MODULE_LAST
,
85 TWL6030_MODULE_GASGAUGE
,
90 /* Until the clients has been converted to use TWL_MODULE_LED */
91 #define TWL4030_MODULE_LED TWL_MODULE_LED
93 #define GPIO_INTR_OFFSET 0
94 #define KEYPAD_INTR_OFFSET 1
95 #define BCI_INTR_OFFSET 2
96 #define MADC_INTR_OFFSET 3
97 #define USB_INTR_OFFSET 4
98 #define CHARGERFAULT_INTR_OFFSET 5
99 #define BCI_PRES_INTR_OFFSET 9
100 #define USB_PRES_INTR_OFFSET 10
101 #define RTC_INTR_OFFSET 11
104 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
106 #define PWR_INTR_OFFSET 0
107 #define HOTDIE_INTR_OFFSET 12
108 #define SMPSLDO_INTR_OFFSET 13
109 #define BATDETECT_INTR_OFFSET 14
110 #define SIMDETECT_INTR_OFFSET 15
111 #define MMCDETECT_INTR_OFFSET 16
112 #define GASGAUGE_INTR_OFFSET 17
113 #define USBOTG_INTR_OFFSET 4
114 #define CHARGER_INTR_OFFSET 2
115 #define RSV_INTR_OFFSET 0
117 /* INT register offsets */
118 #define REG_INT_STS_A 0x00
119 #define REG_INT_STS_B 0x01
120 #define REG_INT_STS_C 0x02
122 #define REG_INT_MSK_LINE_A 0x03
123 #define REG_INT_MSK_LINE_B 0x04
124 #define REG_INT_MSK_LINE_C 0x05
126 #define REG_INT_MSK_STS_A 0x06
127 #define REG_INT_MSK_STS_B 0x07
128 #define REG_INT_MSK_STS_C 0x08
130 /* MASK INT REG GROUP A */
131 #define TWL6030_PWR_INT_MASK 0x07
132 #define TWL6030_RTC_INT_MASK 0x18
133 #define TWL6030_HOTDIE_INT_MASK 0x20
134 #define TWL6030_SMPSLDOA_INT_MASK 0xC0
136 /* MASK INT REG GROUP B */
137 #define TWL6030_SMPSLDOB_INT_MASK 0x01
138 #define TWL6030_BATDETECT_INT_MASK 0x02
139 #define TWL6030_SIMDETECT_INT_MASK 0x04
140 #define TWL6030_MMCDETECT_INT_MASK 0x08
141 #define TWL6030_GPADC_INT_MASK 0x60
142 #define TWL6030_GASGAUGE_INT_MASK 0x80
144 /* MASK INT REG GROUP C */
145 #define TWL6030_USBOTG_INT_MASK 0x0F
146 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10
147 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60
149 #define TWL6030_MMCCTRL 0xEE
150 #define VMMC_AUTO_OFF (0x1 << 3)
151 #define SW_FC (0x1 << 2)
154 #define TWL6030_CFG_INPUT_PUPD3 0xF2
155 #define MMC_PU (0x1 << 3)
156 #define MMC_PD (0x1 << 2)
158 #define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
159 #define TWL_SIL_REV(rev) ((rev) >> 24)
160 #define TWL_SIL_5030 0x09002F
161 #define TWL5030_REV_1_0 0x00
162 #define TWL5030_REV_1_1 0x10
163 #define TWL5030_REV_1_2 0x30
165 #define TWL4030_CLASS_ID 0x4030
166 #define TWL6030_CLASS_ID 0x6030
167 unsigned int twl_rev(void);
168 #define GET_TWL_REV (twl_rev())
169 #define TWL_CLASS_IS(class, id) \
170 static inline int twl_class_is_ ##class(void) \
172 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
175 TWL_CLASS_IS(4030, TWL4030_CLASS_ID
)
176 TWL_CLASS_IS(6030, TWL6030_CLASS_ID
)
178 /* Set the regcache bypass for the regmap associated with the nodule */
179 int twl_set_regcache_bypass(u8 mod_no
, bool enable
);
182 * Read and write several 8-bit registers at once.
184 int twl_i2c_write(u8 mod_no
, u8
*value
, u8 reg
, unsigned num_bytes
);
185 int twl_i2c_read(u8 mod_no
, u8
*value
, u8 reg
, unsigned num_bytes
);
188 * Read and write single 8-bit registers
190 static inline int twl_i2c_write_u8(u8 mod_no
, u8 val
, u8 reg
) {
191 return twl_i2c_write(mod_no
, &val
, reg
, 1);
194 static inline int twl_i2c_read_u8(u8 mod_no
, u8
*val
, u8 reg
) {
195 return twl_i2c_read(mod_no
, val
, reg
, 1);
198 static inline int twl_i2c_write_u16(u8 mod_no
, u16 val
, u8 reg
) {
199 val
= cpu_to_le16(val
);
200 return twl_i2c_write(mod_no
, (u8
*) &val
, reg
, 2);
203 static inline int twl_i2c_read_u16(u8 mod_no
, u16
*val
, u8 reg
) {
205 ret
= twl_i2c_read(mod_no
, (u8
*) val
, reg
, 2);
206 *val
= le16_to_cpu(*val
);
210 int twl_get_type(void);
211 int twl_get_version(void);
212 int twl_get_hfclk_rate(void);
214 int twl6030_interrupt_unmask(u8 bit_mask
, u8 offset
);
215 int twl6030_interrupt_mask(u8 bit_mask
, u8 offset
);
217 /* Card detect Configuration for MMC1 Controller on OMAP4 */
218 #ifdef CONFIG_TWL4030_CORE
219 int twl6030_mmc_card_detect_config(void);
221 static inline int twl6030_mmc_card_detect_config(void)
223 pr_debug("twl6030_mmc_card_detect_config not supported\n");
228 /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
229 #ifdef CONFIG_TWL4030_CORE
230 int twl6030_mmc_card_detect(struct device
*dev
, int slot
);
232 static inline int twl6030_mmc_card_detect(struct device
*dev
, int slot
)
234 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
238 /*----------------------------------------------------------------------*/
241 * NOTE: at up to 1024 registers, this is a big chip.
243 * Avoid putting register declarations in this file, instead of into
244 * a driver-private file, unless some of the registers in a block
245 * need to be shared with other drivers. One example is blocks that
246 * have Secondary IRQ Handler (SIH) registers.
249 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
250 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
251 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
253 /*----------------------------------------------------------------------*/
256 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
259 #define REG_GPIODATAIN1 0x0
260 #define REG_GPIODATAIN2 0x1
261 #define REG_GPIODATAIN3 0x2
262 #define REG_GPIODATADIR1 0x3
263 #define REG_GPIODATADIR2 0x4
264 #define REG_GPIODATADIR3 0x5
265 #define REG_GPIODATAOUT1 0x6
266 #define REG_GPIODATAOUT2 0x7
267 #define REG_GPIODATAOUT3 0x8
268 #define REG_CLEARGPIODATAOUT1 0x9
269 #define REG_CLEARGPIODATAOUT2 0xA
270 #define REG_CLEARGPIODATAOUT3 0xB
271 #define REG_SETGPIODATAOUT1 0xC
272 #define REG_SETGPIODATAOUT2 0xD
273 #define REG_SETGPIODATAOUT3 0xE
274 #define REG_GPIO_DEBEN1 0xF
275 #define REG_GPIO_DEBEN2 0x10
276 #define REG_GPIO_DEBEN3 0x11
277 #define REG_GPIO_CTRL 0x12
278 #define REG_GPIOPUPDCTR1 0x13
279 #define REG_GPIOPUPDCTR2 0x14
280 #define REG_GPIOPUPDCTR3 0x15
281 #define REG_GPIOPUPDCTR4 0x16
282 #define REG_GPIOPUPDCTR5 0x17
283 #define REG_GPIO_ISR1A 0x19
284 #define REG_GPIO_ISR2A 0x1A
285 #define REG_GPIO_ISR3A 0x1B
286 #define REG_GPIO_IMR1A 0x1C
287 #define REG_GPIO_IMR2A 0x1D
288 #define REG_GPIO_IMR3A 0x1E
289 #define REG_GPIO_ISR1B 0x1F
290 #define REG_GPIO_ISR2B 0x20
291 #define REG_GPIO_ISR3B 0x21
292 #define REG_GPIO_IMR1B 0x22
293 #define REG_GPIO_IMR2B 0x23
294 #define REG_GPIO_IMR3B 0x24
295 #define REG_GPIO_EDR1 0x28
296 #define REG_GPIO_EDR2 0x29
297 #define REG_GPIO_EDR3 0x2A
298 #define REG_GPIO_EDR4 0x2B
299 #define REG_GPIO_EDR5 0x2C
300 #define REG_GPIO_SIH_CTRL 0x2D
302 /* Up to 18 signals are available as GPIOs, when their
303 * pins are not assigned to another use (such as ULPI/USB).
305 #define TWL4030_GPIO_MAX 18
307 /*----------------------------------------------------------------------*/
309 /*Interface Bit Register (INTBR) offsets
310 *(Use TWL_4030_MODULE_INTBR)
313 #define REG_IDCODE_7_0 0x00
314 #define REG_IDCODE_15_8 0x01
315 #define REG_IDCODE_16_23 0x02
316 #define REG_IDCODE_31_24 0x03
317 #define REG_GPPUPDCTR1 0x0F
318 #define REG_UNLOCK_TEST_REG 0x12
320 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
322 #define I2C_SCL_CTRL_PU BIT(0)
323 #define I2C_SDA_CTRL_PU BIT(2)
324 #define SR_I2C_SCL_CTRL_PU BIT(4)
325 #define SR_I2C_SDA_CTRL_PU BIT(6)
327 #define TWL_EEPROM_R_UNLOCK 0x49
329 /*----------------------------------------------------------------------*/
332 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
333 * ... SIH/interrupt only
336 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
337 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
338 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
339 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
340 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
341 #define TWL4030_KEYPAD_KEYP_EDR 0x16
342 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
344 /*----------------------------------------------------------------------*/
347 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
348 * ... SIH/interrupt only
351 #define TWL4030_MADC_ISR1 0x61
352 #define TWL4030_MADC_IMR1 0x62
353 #define TWL4030_MADC_ISR2 0x63
354 #define TWL4030_MADC_IMR2 0x64
355 #define TWL4030_MADC_SIR 0x65 /* test register */
356 #define TWL4030_MADC_EDR 0x66
357 #define TWL4030_MADC_SIH_CTRL 0x67
359 /*----------------------------------------------------------------------*/
362 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
365 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
366 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
367 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
368 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
369 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
370 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
371 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
372 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
373 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
374 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
375 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
376 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
377 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
378 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
380 /*----------------------------------------------------------------------*/
383 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
386 #define TWL4030_INT_PWR_ISR1 0x0
387 #define TWL4030_INT_PWR_IMR1 0x1
388 #define TWL4030_INT_PWR_ISR2 0x2
389 #define TWL4030_INT_PWR_IMR2 0x3
390 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
391 #define TWL4030_INT_PWR_EDR1 0x5
392 #define TWL4030_INT_PWR_EDR2 0x6
393 #define TWL4030_INT_PWR_SIH_CTRL 0x7
395 /*----------------------------------------------------------------------*/
398 * Accessory Interrupts
400 #define TWL5031_ACIIMR_LSB 0x05
401 #define TWL5031_ACIIMR_MSB 0x06
402 #define TWL5031_ACIIDR_LSB 0x07
403 #define TWL5031_ACIIDR_MSB 0x08
404 #define TWL5031_ACCISR1 0x0F
405 #define TWL5031_ACCIMR1 0x10
406 #define TWL5031_ACCISR2 0x11
407 #define TWL5031_ACCIMR2 0x12
408 #define TWL5031_ACCSIR 0x13
409 #define TWL5031_ACCEDR1 0x14
410 #define TWL5031_ACCSIHCTRL 0x15
412 /*----------------------------------------------------------------------*/
415 * Battery Charger Controller
418 #define TWL5031_INTERRUPTS_BCIISR1 0x0
419 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
420 #define TWL5031_INTERRUPTS_BCIISR2 0x2
421 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
422 #define TWL5031_INTERRUPTS_BCISIR 0x4
423 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
424 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
425 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
427 /*----------------------------------------------------------------------*/
430 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
433 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
434 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
435 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
436 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
437 #define TWL4030_PM_MASTER_STS_BOOT 0x04
438 #define TWL4030_PM_MASTER_CFG_BOOT 0x05
439 #define TWL4030_PM_MASTER_SHUNDAN 0x06
440 #define TWL4030_PM_MASTER_BOOT_BCI 0x07
441 #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
442 #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
443 #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
444 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
445 #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
446 #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
447 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
448 #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
449 #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
450 #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
451 #define TWL4030_PM_MASTER_STS_P123_STATE 0x13
452 #define TWL4030_PM_MASTER_PB_CFG 0x14
453 #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
454 #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
455 #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
456 #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
457 #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
458 #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
459 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
460 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
461 #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
462 #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
463 #define TWL4030_PM_MASTER_MEMORY_DATA 0x24
465 #define TWL4030_PM_MASTER_KEY_CFG1 0xc0
466 #define TWL4030_PM_MASTER_KEY_CFG2 0x0c
468 #define TWL4030_PM_MASTER_KEY_TST1 0xe0
469 #define TWL4030_PM_MASTER_KEY_TST2 0x0e
471 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
473 /*----------------------------------------------------------------------*/
475 /* Power bus message definitions */
477 /* The TWL4030/5030 splits its power-management resources (the various
478 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
479 * P3. These groups can then be configured to transition between sleep, wait-on
480 * and active states by sending messages to the power bus. See Section 5.4.2
481 * Power Resources of TWL4030 TRM
484 /* Processor groups */
485 #define DEV_GRP_NULL 0x0
486 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
487 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
488 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
490 /* Resource groups */
491 #define RES_GRP_RES 0x0 /* Reserved */
492 #define RES_GRP_PP 0x1 /* Power providers */
493 #define RES_GRP_RC 0x2 /* Reset and control */
494 #define RES_GRP_PP_RC 0x3
495 #define RES_GRP_PR 0x4 /* Power references */
496 #define RES_GRP_PP_PR 0x5
497 #define RES_GRP_RC_PR 0x6
498 #define RES_GRP_ALL 0x7 /* All resource groups */
500 #define RES_TYPE2_R0 0x0
501 #define RES_TYPE2_R1 0x1
502 #define RES_TYPE2_R2 0x2
504 #define RES_TYPE_R0 0x0
505 #define RES_TYPE_ALL 0x7
507 /* Resource states */
508 #define RES_STATE_WRST 0xF
509 #define RES_STATE_ACTIVE 0xE
510 #define RES_STATE_SLEEP 0x8
511 #define RES_STATE_OFF 0x0
513 /* Power resources */
515 /* Power providers */
526 #define RES_VINTANA1 11
527 #define RES_VINTANA2 12
528 #define RES_VINTDIG 13
532 #define RES_VUSB_1V5 17
533 #define RES_VUSB_1V8 18
534 #define RES_VUSB_3V1 19
535 #define RES_VUSBCP 20
537 /* Reset and control */
538 #define RES_NRES_PWRON 22
541 #define RES_HFCLKOUT 25
542 #define RES_32KCLKOUT 26
544 /* Power Reference */
545 #define RES_MAIN_REF 28
547 #define TOTAL_RESOURCES 28
549 * Power Bus Message Format ... these can be sent individually by Linux,
550 * but are usually part of downloaded scripts that are run when various
551 * power events are triggered.
553 * Broadcast Message (16 Bits):
554 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
557 * Singular Message (16 Bits):
558 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
561 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
562 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
563 | (type) << 4 | (state))
565 #define MSG_SINGULAR(devgrp, id, state) \
566 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
568 #define MSG_BROADCAST_ALL(devgrp, state) \
569 ((devgrp) << 5 | (state))
571 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
572 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
573 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
574 /*----------------------------------------------------------------------*/
576 struct twl4030_clock_init_data
{
577 bool ck32k_lowpwr_enable
;
580 struct twl4030_bci_platform_data
{
581 int *battery_tmp_tbl
;
582 unsigned int tblsize
;
583 int bb_uvolt
; /* voltage to charge backup battery */
584 int bb_uamp
; /* current for backup battery charging */
587 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
588 struct twl4030_gpio_platform_data
{
589 /* package the two LED signals as output-only GPIOs? */
592 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
595 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
598 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
599 * should be enabled. Else, if that bit is set in "pulldowns",
600 * that pulldown is enabled. Don't waste power by letting any
601 * digital inputs float...
606 int (*setup
)(struct device
*dev
,
607 unsigned gpio
, unsigned ngpio
);
608 int (*teardown
)(struct device
*dev
,
609 unsigned gpio
, unsigned ngpio
);
612 struct twl4030_madc_platform_data
{
616 /* Boards have unique mappings of {row, col} --> keycode.
617 * Column and row are 8 bits each, but range only from 0..7.
618 * a PERSISTENT_KEY is "always on" and never reported.
620 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
622 struct twl4030_keypad_data
{
623 const struct matrix_keymap_data
*keymap_data
;
629 enum twl4030_usb_mode
{
630 T2_USB_MODE_ULPI
= 1,
631 T2_USB_MODE_CEA2011_3PIN
= 2,
634 struct twl4030_usb_data
{
635 enum twl4030_usb_mode usb_mode
;
636 unsigned long features
;
637 struct phy_init_data
*init_data
;
639 int (*phy_init
)(struct device
*dev
);
640 int (*phy_exit
)(struct device
*dev
);
641 /* Power on/off the PHY */
642 int (*phy_power
)(struct device
*dev
, int iD
, int on
);
643 /* enable/disable phy clocks */
644 int (*phy_set_clock
)(struct device
*dev
, int on
);
645 /* suspend/resume of phy */
646 int (*phy_suspend
)(struct device
*dev
, int suspend
);
654 struct twl4030_script
{
655 struct twl4030_ins
*script
;
658 #define TWL4030_WRST_SCRIPT (1<<0)
659 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
660 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
661 #define TWL4030_SLEEP_SCRIPT (1<<3)
664 struct twl4030_resconfig
{
666 u8 devgroup
; /* Processor group that Power resource belongs to */
667 u8 type
; /* Power resource addressed, 6 / broadcast message */
668 u8 type2
; /* Power resource addressed, 3 / broadcast message */
669 u8 remap_off
; /* off state remapping */
670 u8 remap_sleep
; /* sleep state remapping */
673 struct twl4030_power_data
{
674 struct twl4030_script
**scripts
;
676 struct twl4030_resconfig
*resource_config
;
677 struct twl4030_resconfig
*board_config
;
678 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
679 bool use_poweroff
; /* Board is wired for TWL poweroff */
682 extern int twl4030_remove_script(u8 flags
);
683 extern void twl4030_power_off(void);
685 struct twl4030_codec_data
{
686 unsigned int digimic_delay
; /* in ms */
687 unsigned int ramp_delay_value
;
688 unsigned int offset_cncl_path
;
689 unsigned int hs_extmute
:1;
693 struct twl4030_vibra_data
{
694 unsigned int coexist
;
697 struct twl4030_audio_data
{
698 unsigned int audio_mclk
;
699 struct twl4030_codec_data
*codec
;
700 struct twl4030_vibra_data
*vibra
;
703 int audpwron_gpio
; /* audio power-on gpio */
704 int naudint_irq
; /* audio interrupt */
705 unsigned int irq_base
;
708 struct twl4030_platform_data
{
709 struct twl4030_clock_init_data
*clock
;
710 struct twl4030_bci_platform_data
*bci
;
711 struct twl4030_gpio_platform_data
*gpio
;
712 struct twl4030_madc_platform_data
*madc
;
713 struct twl4030_keypad_data
*keypad
;
714 struct twl4030_usb_data
*usb
;
715 struct twl4030_power_data
*power
;
716 struct twl4030_audio_data
*audio
;
718 /* Common LDO regulators for TWL4030/TWL6030 */
719 struct regulator_init_data
*vdac
;
720 struct regulator_init_data
*vaux1
;
721 struct regulator_init_data
*vaux2
;
722 struct regulator_init_data
*vaux3
;
723 struct regulator_init_data
*vdd1
;
724 struct regulator_init_data
*vdd2
;
725 struct regulator_init_data
*vdd3
;
726 /* TWL4030 LDO regulators */
727 struct regulator_init_data
*vpll1
;
728 struct regulator_init_data
*vpll2
;
729 struct regulator_init_data
*vmmc1
;
730 struct regulator_init_data
*vmmc2
;
731 struct regulator_init_data
*vsim
;
732 struct regulator_init_data
*vaux4
;
733 struct regulator_init_data
*vio
;
734 struct regulator_init_data
*vintana1
;
735 struct regulator_init_data
*vintana2
;
736 struct regulator_init_data
*vintdig
;
737 /* TWL6030 LDO regulators */
738 struct regulator_init_data
*vmmc
;
739 struct regulator_init_data
*vpp
;
740 struct regulator_init_data
*vusim
;
741 struct regulator_init_data
*vana
;
742 struct regulator_init_data
*vcxio
;
743 struct regulator_init_data
*vusb
;
744 struct regulator_init_data
*clk32kg
;
745 struct regulator_init_data
*v1v8
;
746 struct regulator_init_data
*v2v1
;
747 /* TWL6032 LDO regulators */
748 struct regulator_init_data
*ldo1
;
749 struct regulator_init_data
*ldo2
;
750 struct regulator_init_data
*ldo3
;
751 struct regulator_init_data
*ldo4
;
752 struct regulator_init_data
*ldo5
;
753 struct regulator_init_data
*ldo6
;
754 struct regulator_init_data
*ldo7
;
755 struct regulator_init_data
*ldoln
;
756 struct regulator_init_data
*ldousb
;
757 /* TWL6032 DCDC regulators */
758 struct regulator_init_data
*smps3
;
759 struct regulator_init_data
*smps4
;
760 struct regulator_init_data
*vio6025
;
763 struct twl_regulator_driver_data
{
764 int (*set_voltage
)(void *data
, int target_uV
);
765 int (*get_voltage
)(void *data
);
767 unsigned long features
;
769 /* chip-specific feature flags, for twl_regulator_driver_data.features */
770 #define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */
771 #define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */
772 #define TWL5031 BIT(2) /* twl5031 has different registers */
773 #define TWL6030_CLASS BIT(3) /* TWL6030 class */
774 #define TWL6032_SUBCLASS BIT(4) /* TWL6032 has changed registers */
775 #define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible
776 * but not officially supported.
777 * This flag is necessary to
781 /*----------------------------------------------------------------------*/
783 int twl4030_sih_setup(struct device
*dev
, int module
, int irq_base
);
785 /* Offsets to Power Registers */
786 #define TWL4030_VDAC_DEV_GRP 0x3B
787 #define TWL4030_VDAC_DEDICATED 0x3E
788 #define TWL4030_VAUX1_DEV_GRP 0x17
789 #define TWL4030_VAUX1_DEDICATED 0x1A
790 #define TWL4030_VAUX2_DEV_GRP 0x1B
791 #define TWL4030_VAUX2_DEDICATED 0x1E
792 #define TWL4030_VAUX3_DEV_GRP 0x1F
793 #define TWL4030_VAUX3_DEDICATED 0x22
795 static inline int twl4030charger_usb_en(int enable
) { return 0; }
797 /*----------------------------------------------------------------------*/
799 /* Linux-specific regulator identifiers ... for now, we only support
800 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
801 * need to tie into hardware based voltage scaling (cpufreq etc), while
802 * VIO is generally fixed.
805 /* TWL4030 SMPS/LDO's */
806 /* EXTERNAL dc-to-dc buck converters */
807 #define TWL4030_REG_VDD1 0
808 #define TWL4030_REG_VDD2 1
809 #define TWL4030_REG_VIO 2
812 #define TWL4030_REG_VDAC 3
813 #define TWL4030_REG_VPLL1 4
814 #define TWL4030_REG_VPLL2 5 /* not on all chips */
815 #define TWL4030_REG_VMMC1 6
816 #define TWL4030_REG_VMMC2 7 /* not on all chips */
817 #define TWL4030_REG_VSIM 8 /* not on all chips */
818 #define TWL4030_REG_VAUX1 9 /* not on all chips */
819 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
820 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
821 #define TWL4030_REG_VAUX3 12 /* not on all chips */
822 #define TWL4030_REG_VAUX4 13 /* not on all chips */
825 #define TWL4030_REG_VINTANA1 14
826 #define TWL4030_REG_VINTANA2 15
827 #define TWL4030_REG_VINTDIG 16
828 #define TWL4030_REG_VUSB1V5 17
829 #define TWL4030_REG_VUSB1V8 18
830 #define TWL4030_REG_VUSB3V1 19
832 /* TWL6030 SMPS/LDO's */
833 /* EXTERNAL dc-to-dc buck convertor controllable via SR */
834 #define TWL6030_REG_VDD1 30
835 #define TWL6030_REG_VDD2 31
836 #define TWL6030_REG_VDD3 32
838 /* Non SR compliant dc-to-dc buck convertors */
839 #define TWL6030_REG_VMEM 33
840 #define TWL6030_REG_V2V1 34
841 #define TWL6030_REG_V1V29 35
842 #define TWL6030_REG_V1V8 36
845 #define TWL6030_REG_VAUX1_6030 37
846 #define TWL6030_REG_VAUX2_6030 38
847 #define TWL6030_REG_VAUX3_6030 39
848 #define TWL6030_REG_VMMC 40
849 #define TWL6030_REG_VPP 41
850 #define TWL6030_REG_VUSIM 42
851 #define TWL6030_REG_VANA 43
852 #define TWL6030_REG_VCXIO 44
853 #define TWL6030_REG_VDAC 45
854 #define TWL6030_REG_VUSB 46
857 #define TWL6030_REG_VRTC 47
858 #define TWL6030_REG_CLK32KG 48
860 /* LDOs on 6025 have different names */
861 #define TWL6032_REG_LDO2 49
862 #define TWL6032_REG_LDO4 50
863 #define TWL6032_REG_LDO3 51
864 #define TWL6032_REG_LDO5 52
865 #define TWL6032_REG_LDO1 53
866 #define TWL6032_REG_LDO7 54
867 #define TWL6032_REG_LDO6 55
868 #define TWL6032_REG_LDOLN 56
869 #define TWL6032_REG_LDOUSB 57
871 /* 6025 DCDC supplies */
872 #define TWL6032_REG_SMPS3 58
873 #define TWL6032_REG_SMPS4 59
874 #define TWL6032_REG_VIO 60
877 #endif /* End of __TWL4030_H */