include/linux/intel-iommu.h

   1 /*
   2  * Copyright © 2006-2015, Intel Corporation.
   3  *
   4  * Authors: Ashok Raj <ashok.raj@intel.com>
   5  *          Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
   6  *          David Woodhouse <David.Woodhouse@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  19  * Place - Suite 330, Boston, MA 02111-1307 USA.
  20  */
  21
  22 #ifndef _INTEL_IOMMU_H_
  23 #define _INTEL_IOMMU_H_
  24
  25 #include <linux/types.h>
  26 #include <linux/iova.h>
  27 #include <linux/io.h>
  28 #include <linux/idr.h>
  29 #include <linux/dma_remapping.h>
  30 #include <linux/mmu_notifier.h>
  31 #include <linux/list.h>
  32 #include <linux/iommu.h>
  33 #include <linux/io-64-nonatomic-lo-hi.h>
  34
  35 #include <asm/cacheflush.h>
  36 #include <asm/iommu.h>
  37
  38 /*
  39  * Intel IOMMU register specification per version 1.0 public spec.
  40  */
  41
  42 #define DMAR_VER_REG    0x0     /* Arch version supported by this IOMMU */
  43 #define DMAR_CAP_REG    0x8     /* Hardware supported capabilities */
  44 #define DMAR_ECAP_REG   0x10    /* Extended capabilities supported */
  45 #define DMAR_GCMD_REG   0x18    /* Global command register */
  46 #define DMAR_GSTS_REG   0x1c    /* Global status register */
  47 #define DMAR_RTADDR_REG 0x20    /* Root entry table */
  48 #define DMAR_CCMD_REG   0x28    /* Context command reg */
  49 #define DMAR_FSTS_REG   0x34    /* Fault Status register */
  50 #define DMAR_FECTL_REG  0x38    /* Fault control register */
  51 #define DMAR_FEDATA_REG 0x3c    /* Fault event interrupt data register */
  52 #define DMAR_FEADDR_REG 0x40    /* Fault event interrupt addr register */
  53 #define DMAR_FEUADDR_REG 0x44   /* Upper address register */
  54 #define DMAR_AFLOG_REG  0x58    /* Advanced Fault control */
  55 #define DMAR_PMEN_REG   0x64    /* Enable Protected Memory Region */
  56 #define DMAR_PLMBASE_REG 0x68   /* PMRR Low addr */
  57 #define DMAR_PLMLIMIT_REG 0x6c  /* PMRR low limit */
  58 #define DMAR_PHMBASE_REG 0x70   /* pmrr high base addr */
  59 #define DMAR_PHMLIMIT_REG 0x78  /* pmrr high limit */
  60 #define DMAR_IQH_REG    0x80    /* Invalidation queue head register */
  61 #define DMAR_IQT_REG    0x88    /* Invalidation queue tail register */
  62 #define DMAR_IQ_SHIFT   4       /* Invalidation queue head/tail shift */
  63 #define DMAR_IQA_REG    0x90    /* Invalidation queue addr register */
  64 #define DMAR_ICS_REG    0x9c    /* Invalidation complete status register */
  65 #define DMAR_IRTA_REG   0xb8    /* Interrupt remapping table addr register */
  66 #define DMAR_PQH_REG    0xc0    /* Page request queue head register */
  67 #define DMAR_PQT_REG    0xc8    /* Page request queue tail register */
  68 #define DMAR_PQA_REG    0xd0    /* Page request queue address register */
  69 #define DMAR_PRS_REG    0xdc    /* Page request status register */
  70 #define DMAR_PECTL_REG  0xe0    /* Page request event control register */
  71 #define DMAR_PEDATA_REG 0xe4    /* Page request event interrupt data register */
  72 #define DMAR_PEADDR_REG 0xe8    /* Page request event interrupt addr register */
  73 #define DMAR_PEUADDR_REG 0xec   /* Page request event Upper address register */
  74
  75 #define OFFSET_STRIDE           (9)
  76
  77 #define dmar_readq(a) readq(a)
  78 #define dmar_writeq(a,v) writeq(v,a)
  79
  80 #define DMAR_VER_MAJOR(v)               (((v) & 0xf0) >> 4)
  81 #define DMAR_VER_MINOR(v)               ((v) & 0x0f)
  82
  83 /*
  84  * Decoding Capability Register
  85  */
  86 #define cap_pi_support(c)       (((c) >> 59) & 1)
  87 #define cap_read_drain(c)       (((c) >> 55) & 1)
  88 #define cap_write_drain(c)      (((c) >> 54) & 1)
  89 #define cap_max_amask_val(c)    (((c) >> 48) & 0x3f)
  90 #define cap_num_fault_regs(c)   ((((c) >> 40) & 0xff) + 1)
  91 #define cap_pgsel_inv(c)        (((c) >> 39) & 1)
  92
  93 #define cap_super_page_val(c)   (((c) >> 34) & 0xf)
  94 #define cap_super_offset(c)     (((find_first_bit(&cap_super_page_val(c), 4)) \
  95                                         * OFFSET_STRIDE) + 21)
  96
  97 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
  98 #define cap_max_fault_reg_offset(c) \
  99         (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
 100
 101 #define cap_zlr(c)              (((c) >> 22) & 1)
 102 #define cap_isoch(c)            (((c) >> 23) & 1)
 103 #define cap_mgaw(c)             ((((c) >> 16) & 0x3f) + 1)
 104 #define cap_sagaw(c)            (((c) >> 8) & 0x1f)
 105 #define cap_caching_mode(c)     (((c) >> 7) & 1)
 106 #define cap_phmr(c)             (((c) >> 6) & 1)
 107 #define cap_plmr(c)             (((c) >> 5) & 1)
 108 #define cap_rwbf(c)             (((c) >> 4) & 1)
 109 #define cap_afl(c)              (((c) >> 3) & 1)
 110 #define cap_ndoms(c)            (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
 111 /*
 112  * Extended Capability Register
 113  */
 114
 115 #define ecap_dit(e)             ((e >> 41) & 0x1)
 116 #define ecap_pasid(e)           ((e >> 40) & 0x1)
 117 #define ecap_pss(e)             ((e >> 35) & 0x1f)
 118 #define ecap_eafs(e)            ((e >> 34) & 0x1)
 119 #define ecap_nwfs(e)            ((e >> 33) & 0x1)
 120 #define ecap_srs(e)             ((e >> 31) & 0x1)
 121 #define ecap_ers(e)             ((e >> 30) & 0x1)
 122 #define ecap_prs(e)             ((e >> 29) & 0x1)
 123 #define ecap_broken_pasid(e)    ((e >> 28) & 0x1)
 124 #define ecap_dis(e)             ((e >> 27) & 0x1)
 125 #define ecap_nest(e)            ((e >> 26) & 0x1)
 126 #define ecap_mts(e)             ((e >> 25) & 0x1)
 127 #define ecap_ecs(e)             ((e >> 24) & 0x1)
 128 #define ecap_iotlb_offset(e)    ((((e) >> 8) & 0x3ff) * 16)
 129 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
 130 #define ecap_coherent(e)        ((e) & 0x1)
 131 #define ecap_qis(e)             ((e) & 0x2)
 132 #define ecap_pass_through(e)    ((e >> 6) & 0x1)
 133 #define ecap_eim_support(e)     ((e >> 4) & 0x1)
 134 #define ecap_ir_support(e)      ((e >> 3) & 0x1)
 135 #define ecap_dev_iotlb_support(e)       (((e) >> 2) & 0x1)
 136 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
 137 #define ecap_sc_support(e)      ((e >> 7) & 0x1) /* Snooping Control */
 138
 139 /* IOTLB_REG */
 140 #define DMA_TLB_FLUSH_GRANU_OFFSET  60
 141 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
 142 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
 143 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
 144 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
 145 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
 146 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
 147 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
 148 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
 149 #define DMA_TLB_IVT (((u64)1) << 63)
 150 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
 151 #define DMA_TLB_MAX_SIZE (0x3f)
 152
 153 /* INVALID_DESC */
 154 #define DMA_CCMD_INVL_GRANU_OFFSET  61
 155 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
 156 #define DMA_ID_TLB_DSI_FLUSH    (((u64)2) << 4)
 157 #define DMA_ID_TLB_PSI_FLUSH    (((u64)3) << 4)
 158 #define DMA_ID_TLB_READ_DRAIN   (((u64)1) << 7)
 159 #define DMA_ID_TLB_WRITE_DRAIN  (((u64)1) << 6)
 160 #define DMA_ID_TLB_DID(id)      (((u64)((id & 0xffff) << 16)))
 161 #define DMA_ID_TLB_IH_NONLEAF   (((u64)1) << 6)
 162 #define DMA_ID_TLB_ADDR(addr)   (addr)
 163 #define DMA_ID_TLB_ADDR_MASK(mask)      (mask)
 164
 165 /* PMEN_REG */
 166 #define DMA_PMEN_EPM (((u32)1)<<31)
 167 #define DMA_PMEN_PRS (((u32)1)<<0)
 168
 169 /* GCMD_REG */
 170 #define DMA_GCMD_TE (((u32)1) << 31)
 171 #define DMA_GCMD_SRTP (((u32)1) << 30)
 172 #define DMA_GCMD_SFL (((u32)1) << 29)
 173 #define DMA_GCMD_EAFL (((u32)1) << 28)
 174 #define DMA_GCMD_WBF (((u32)1) << 27)
 175 #define DMA_GCMD_QIE (((u32)1) << 26)
 176 #define DMA_GCMD_SIRTP (((u32)1) << 24)
 177 #define DMA_GCMD_IRE (((u32) 1) << 25)
 178 #define DMA_GCMD_CFI (((u32) 1) << 23)
 179
 180 /* GSTS_REG */
 181 #define DMA_GSTS_TES (((u32)1) << 31)
 182 #define DMA_GSTS_RTPS (((u32)1) << 30)
 183 #define DMA_GSTS_FLS (((u32)1) << 29)
 184 #define DMA_GSTS_AFLS (((u32)1) << 28)
 185 #define DMA_GSTS_WBFS (((u32)1) << 27)
 186 #define DMA_GSTS_QIES (((u32)1) << 26)
 187 #define DMA_GSTS_IRTPS (((u32)1) << 24)
 188 #define DMA_GSTS_IRES (((u32)1) << 25)
 189 #define DMA_GSTS_CFIS (((u32)1) << 23)
 190
 191 /* DMA_RTADDR_REG */
 192 #define DMA_RTADDR_RTT (((u64)1) << 11)
 193
 194 /* CCMD_REG */
 195 #define DMA_CCMD_ICC (((u64)1) << 63)
 196 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
 197 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
 198 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
 199 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
 200 #define DMA_CCMD_MASK_NOBIT 0
 201 #define DMA_CCMD_MASK_1BIT 1
 202 #define DMA_CCMD_MASK_2BIT 2
 203 #define DMA_CCMD_MASK_3BIT 3
 204 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
 205 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
 206
 207 /* FECTL_REG */
 208 #define DMA_FECTL_IM (((u32)1) << 31)
 209
 210 /* FSTS_REG */
 211 #define DMA_FSTS_PPF ((u32)2)
 212 #define DMA_FSTS_PFO ((u32)1)
 213 #define DMA_FSTS_IQE (1 << 4)
 214 #define DMA_FSTS_ICE (1 << 5)
 215 #define DMA_FSTS_ITE (1 << 6)
 216 #define DMA_FSTS_PRO (1 << 7)
 217 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
 218
 219 /* FRCD_REG, 32 bits access */
 220 #define DMA_FRCD_F (((u32)1) << 31)
 221 #define dma_frcd_type(d) ((d >> 30) & 1)
 222 #define dma_frcd_fault_reason(c) (c & 0xff)
 223 #define dma_frcd_source_id(c) (c & 0xffff)
 224 /* low 64 bit */
 225 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
 226
 227 /* PRS_REG */
 228 #define DMA_PRS_PPR     ((u32)1)
 229
 230 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)                     \
 231 do {                                                                    \
 232         cycles_t start_time = get_cycles();                             \
 233         while (1) {                                                     \
 234                 sts = op(iommu->reg + offset);                          \
 235                 if (cond)                                               \
 236                         break;                                          \
 237                 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
 238                         panic("DMAR hardware is malfunctioning\n");     \
 239                 cpu_relax();                                            \
 240         }                                                               \
 241 } while (0)
 242
 243 #define QI_LENGTH       256     /* queue length */
 244
 245 enum {
 246         QI_FREE,
 247         QI_IN_USE,
 248         QI_DONE,
 249         QI_ABORT
 250 };
 251
 252 #define QI_CC_TYPE              0x1
 253 #define QI_IOTLB_TYPE           0x2
 254 #define QI_DIOTLB_TYPE          0x3
 255 #define QI_IEC_TYPE             0x4
 256 #define QI_IWD_TYPE             0x5
 257 #define QI_EIOTLB_TYPE          0x6
 258 #define QI_PC_TYPE              0x7
 259 #define QI_DEIOTLB_TYPE         0x8
 260 #define QI_PGRP_RESP_TYPE       0x9
 261 #define QI_PSTRM_RESP_TYPE      0xa
 262
 263 #define QI_IEC_SELECTIVE        (((u64)1) << 4)
 264 #define QI_IEC_IIDEX(idx)       (((u64)(idx & 0xffff) << 32))
 265 #define QI_IEC_IM(m)            (((u64)(m & 0x1f) << 27))
 266
 267 #define QI_IWD_STATUS_DATA(d)   (((u64)d) << 32)
 268 #define QI_IWD_STATUS_WRITE     (((u64)1) << 5)
 269
 270 #define QI_IOTLB_DID(did)       (((u64)did) << 16)
 271 #define QI_IOTLB_DR(dr)         (((u64)dr) << 7)
 272 #define QI_IOTLB_DW(dw)         (((u64)dw) << 6)
 273 #define QI_IOTLB_GRAN(gran)     (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
 274 #define QI_IOTLB_ADDR(addr)     (((u64)addr) & VTD_PAGE_MASK)
 275 #define QI_IOTLB_IH(ih)         (((u64)ih) << 6)
 276 #define QI_IOTLB_AM(am)         (((u8)am))
 277
 278 #define QI_CC_FM(fm)            (((u64)fm) << 48)
 279 #define QI_CC_SID(sid)          (((u64)sid) << 32)
 280 #define QI_CC_DID(did)          (((u64)did) << 16)
 281 #define QI_CC_GRAN(gran)        (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
 282
 283 #define QI_DEV_IOTLB_SID(sid)   ((u64)((sid) & 0xffff) << 32)
 284 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
 285 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
 286 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
 287                                    ((u64)((pfsid >> 4) & 0xfff) << 52))
 288 #define QI_DEV_IOTLB_SIZE       1
 289 #define QI_DEV_IOTLB_MAX_INVS   32
 290
 291 #define QI_PC_PASID(pasid)      (((u64)pasid) << 32)
 292 #define QI_PC_DID(did)          (((u64)did) << 16)
 293 #define QI_PC_GRAN(gran)        (((u64)gran) << 4)
 294
 295 #define QI_PC_ALL_PASIDS        (QI_PC_TYPE | QI_PC_GRAN(0))
 296 #define QI_PC_PASID_SEL         (QI_PC_TYPE | QI_PC_GRAN(1))
 297
 298 #define QI_EIOTLB_ADDR(addr)    ((u64)(addr) & VTD_PAGE_MASK)
 299 #define QI_EIOTLB_GL(gl)        (((u64)gl) << 7)
 300 #define QI_EIOTLB_IH(ih)        (((u64)ih) << 6)
 301 #define QI_EIOTLB_AM(am)        (((u64)am))
 302 #define QI_EIOTLB_PASID(pasid)  (((u64)pasid) << 32)
 303 #define QI_EIOTLB_DID(did)      (((u64)did) << 16)
 304 #define QI_EIOTLB_GRAN(gran)    (((u64)gran) << 4)
 305
 306 #define QI_DEV_EIOTLB_ADDR(a)   ((u64)(a) & VTD_PAGE_MASK)
 307 #define QI_DEV_EIOTLB_SIZE      (((u64)1) << 11)
 308 #define QI_DEV_EIOTLB_GLOB(g)   ((u64)g)
 309 #define QI_DEV_EIOTLB_PASID(p)  (((u64)p) << 32)
 310 #define QI_DEV_EIOTLB_SID(sid)  ((u64)((sid) & 0xffff) << 16)
 311 #define QI_DEV_EIOTLB_QDEP(qd)  ((u64)((qd) & 0x1f) << 4)
 312 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
 313                                     ((u64)((pfsid >> 4) & 0xfff) << 52))
 314 #define QI_DEV_EIOTLB_MAX_INVS  32
 315
 316 #define QI_PGRP_IDX(idx)        (((u64)(idx)) << 55)
 317 #define QI_PGRP_PRIV(priv)      (((u64)(priv)) << 32)
 318 #define QI_PGRP_RESP_CODE(res)  ((u64)(res))
 319 #define QI_PGRP_PASID(pasid)    (((u64)(pasid)) << 32)
 320 #define QI_PGRP_DID(did)        (((u64)(did)) << 16)
 321 #define QI_PGRP_PASID_P(p)      (((u64)(p)) << 4)
 322
 323 #define QI_PSTRM_ADDR(addr)     (((u64)(addr)) & VTD_PAGE_MASK)
 324 #define QI_PSTRM_DEVFN(devfn)   (((u64)(devfn)) << 4)
 325 #define QI_PSTRM_RESP_CODE(res) ((u64)(res))
 326 #define QI_PSTRM_IDX(idx)       (((u64)(idx)) << 55)
 327 #define QI_PSTRM_PRIV(priv)     (((u64)(priv)) << 32)
 328 #define QI_PSTRM_BUS(bus)       (((u64)(bus)) << 24)
 329 #define QI_PSTRM_PASID(pasid)   (((u64)(pasid)) << 4)
 330
 331 #define QI_RESP_SUCCESS         0x0
 332 #define QI_RESP_INVALID         0x1
 333 #define QI_RESP_FAILURE         0xf
 334
 335 #define QI_GRAN_ALL_ALL                 0
 336 #define QI_GRAN_NONG_ALL                1
 337 #define QI_GRAN_NONG_PASID              2
 338 #define QI_GRAN_PSI_PASID               3
 339
 340 struct qi_desc {
 341         u64 low, high;
 342 };
 343
 344 struct q_inval {
 345         raw_spinlock_t  q_lock;
 346         struct qi_desc  *desc;          /* invalidation queue */
 347         int             *desc_status;   /* desc status */
 348         int             free_head;      /* first free entry */
 349         int             free_tail;      /* last free entry */
 350         int             free_cnt;
 351 };
 352
 353 #ifdef CONFIG_IRQ_REMAP
 354 /* 1MB - maximum possible interrupt remapping table size */
 355 #define INTR_REMAP_PAGE_ORDER   8
 356 #define INTR_REMAP_TABLE_REG_SIZE       0xf
 357 #define INTR_REMAP_TABLE_REG_SIZE_MASK  0xf
 358
 359 #define INTR_REMAP_TABLE_ENTRIES        65536
 360
 361 struct irq_domain;
 362
 363 struct ir_table {
 364         struct irte *base;
 365         unsigned long *bitmap;
 366 };
 367 #endif
 368
 369 struct iommu_flush {
 370         void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
 371                               u8 fm, u64 type);
 372         void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
 373                             unsigned int size_order, u64 type);
 374 };
 375
 376 enum {
 377         SR_DMAR_FECTL_REG,
 378         SR_DMAR_FEDATA_REG,
 379         SR_DMAR_FEADDR_REG,
 380         SR_DMAR_FEUADDR_REG,
 381         MAX_SR_DMAR_REGS
 382 };
 383
 384 #define VTD_FLAG_TRANS_PRE_ENABLED      (1 << 0)
 385 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED  (1 << 1)
 386
 387 struct pasid_entry;
 388 struct pasid_state_entry;
 389 struct page_req_dsc;
 390
 391 struct intel_iommu {
 392         void __iomem    *reg; /* Pointer to hardware regs, virtual addr */
 393         u64             reg_phys; /* physical address of hw register set */
 394         u64             reg_size; /* size of hw register set */
 395         u64             cap;
 396         u64             ecap;
 397         u32             gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
 398         raw_spinlock_t  register_lock; /* protect register handling */
 399         int             seq_id; /* sequence id of the iommu */
 400         int             agaw; /* agaw of this iommu */
 401         int             msagaw; /* max sagaw of this iommu */
 402         unsigned int    irq, pr_irq;
 403         u16             segment;     /* PCI segment# */
 404         unsigned char   name[13];    /* Device Name */
 405
 406 #ifdef CONFIG_INTEL_IOMMU
 407         unsigned long   *domain_ids; /* bitmap of domains */
 408         struct dmar_domain ***domains; /* ptr to domains */
 409         spinlock_t      lock; /* protect context, domain ids */
 410         struct root_entry *root_entry; /* virtual address */
 411
 412         struct iommu_flush flush;
 413 #endif
 414 #ifdef CONFIG_INTEL_IOMMU_SVM
 415         /* These are large and need to be contiguous, so we allocate just
 416          * one for now. We'll maybe want to rethink that if we truly give
 417          * devices away to userspace processes (e.g. for DPDK) and don't
 418          * want to trust that userspace will use *only* the PASID it was
 419          * told to. But while it's all driver-arbitrated, we're fine. */
 420         struct pasid_entry *pasid_table;
 421         struct pasid_state_entry *pasid_state_table;
 422         struct page_req_dsc *prq;
 423         unsigned char prq_name[16];    /* Name for PRQ interrupt */
 424         struct idr pasid_idr;
 425         u32 pasid_max;
 426 #endif
 427         struct q_inval  *qi;            /* Queued invalidation info */
 428         u32 *iommu_state; /* Store iommu states between suspend and resume.*/
 429
 430 #ifdef CONFIG_IRQ_REMAP
 431         struct ir_table *ir_table;      /* Interrupt remapping info */
 432         struct irq_domain *ir_domain;
 433         struct irq_domain *ir_msi_domain;
 434 #endif
 435         struct iommu_device iommu;  /* IOMMU core code handle */
 436         int             node;
 437         u32             flags;      /* Software defined flags */
 438 };
 439
 440 static inline void __iommu_flush_cache(
 441         struct intel_iommu *iommu, void *addr, int size)
 442 {
 443         if (!ecap_coherent(iommu->ecap))
 444                 clflush_cache_range(addr, size);
 445 }
 446
 447 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
 448 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
 449
 450 extern int dmar_enable_qi(struct intel_iommu *iommu);
 451 extern void dmar_disable_qi(struct intel_iommu *iommu);
 452 extern int dmar_reenable_qi(struct intel_iommu *iommu);
 453 extern void qi_global_iec(struct intel_iommu *iommu);
 454
 455 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
 456                              u8 fm, u64 type);
 457 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
 458                           unsigned int size_order, u64 type);
 459 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
 460                         u16 qdep, u64 addr, unsigned mask);
 461 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
 462
 463 extern int dmar_ir_support(void);
 464
 465 #ifdef CONFIG_INTEL_IOMMU_SVM
 466 extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
 467 extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
 468 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
 469 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
 470
 471 struct svm_dev_ops;
 472
 473 struct intel_svm_dev {
 474         struct list_head list;
 475         struct rcu_head rcu;
 476         struct device *dev;
 477         struct svm_dev_ops *ops;
 478         int users;
 479         u16 did;
 480         u16 dev_iotlb:1;
 481         u16 sid, qdep;
 482 };
 483
 484 struct intel_svm {
 485         struct mmu_notifier notifier;
 486         struct mm_struct *mm;
 487         struct intel_iommu *iommu;
 488         int flags;
 489         int pasid;
 490         struct list_head devs;
 491 };
 492
 493 extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
 494 extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
 495 #endif
 496
 497 extern const struct attribute_group *intel_iommu_groups[];
 498
 499 #endif