include/linux/intel-iommu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright © 2006-2015, Intel Corporation.
   4  *
   5  * Authors: Ashok Raj <ashok.raj@intel.com>
   6  *          Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
   7  *          David Woodhouse <David.Woodhouse@intel.com>
   8  */
   9
  10 #ifndef _INTEL_IOMMU_H_
  11 #define _INTEL_IOMMU_H_
  12
  13 #include <linux/types.h>
  14 #include <linux/iova.h>
  15 #include <linux/io.h>
  16 #include <linux/idr.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/list.h>
  19 #include <linux/iommu.h>
  20 #include <linux/io-64-nonatomic-lo-hi.h>
  21 #include <linux/dmar.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/iommu.h>
  25
  26 /*
  27  * VT-d hardware uses 4KiB page size regardless of host page size.
  28  */
  29 #define VTD_PAGE_SHIFT          (12)
  30 #define VTD_PAGE_SIZE           (1UL << VTD_PAGE_SHIFT)
  31 #define VTD_PAGE_MASK           (((u64)-1) << VTD_PAGE_SHIFT)
  32 #define VTD_PAGE_ALIGN(addr)    (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
  33
  34 #define VTD_STRIDE_SHIFT        (9)
  35 #define VTD_STRIDE_MASK         (((u64)-1) << VTD_STRIDE_SHIFT)
  36
  37 #define DMA_PTE_READ (1)
  38 #define DMA_PTE_WRITE (2)
  39 #define DMA_PTE_LARGE_PAGE (1 << 7)
  40 #define DMA_PTE_SNP (1 << 11)
  41
  42 #define CONTEXT_TT_MULTI_LEVEL  0
  43 #define CONTEXT_TT_DEV_IOTLB    1
  44 #define CONTEXT_TT_PASS_THROUGH 2
  45 #define CONTEXT_PASIDE          BIT_ULL(3)
  46
  47 /*
  48  * Intel IOMMU register specification per version 1.0 public spec.
  49  */
  50 #define DMAR_VER_REG    0x0     /* Arch version supported by this IOMMU */
  51 #define DMAR_CAP_REG    0x8     /* Hardware supported capabilities */
  52 #define DMAR_ECAP_REG   0x10    /* Extended capabilities supported */
  53 #define DMAR_GCMD_REG   0x18    /* Global command register */
  54 #define DMAR_GSTS_REG   0x1c    /* Global status register */
  55 #define DMAR_RTADDR_REG 0x20    /* Root entry table */
  56 #define DMAR_CCMD_REG   0x28    /* Context command reg */
  57 #define DMAR_FSTS_REG   0x34    /* Fault Status register */
  58 #define DMAR_FECTL_REG  0x38    /* Fault control register */
  59 #define DMAR_FEDATA_REG 0x3c    /* Fault event interrupt data register */
  60 #define DMAR_FEADDR_REG 0x40    /* Fault event interrupt addr register */
  61 #define DMAR_FEUADDR_REG 0x44   /* Upper address register */
  62 #define DMAR_AFLOG_REG  0x58    /* Advanced Fault control */
  63 #define DMAR_PMEN_REG   0x64    /* Enable Protected Memory Region */
  64 #define DMAR_PLMBASE_REG 0x68   /* PMRR Low addr */
  65 #define DMAR_PLMLIMIT_REG 0x6c  /* PMRR low limit */
  66 #define DMAR_PHMBASE_REG 0x70   /* pmrr high base addr */
  67 #define DMAR_PHMLIMIT_REG 0x78  /* pmrr high limit */
  68 #define DMAR_IQH_REG    0x80    /* Invalidation queue head register */
  69 #define DMAR_IQT_REG    0x88    /* Invalidation queue tail register */
  70 #define DMAR_IQ_SHIFT   4       /* Invalidation queue head/tail shift */
  71 #define DMAR_IQA_REG    0x90    /* Invalidation queue addr register */
  72 #define DMAR_ICS_REG    0x9c    /* Invalidation complete status register */
  73 #define DMAR_IRTA_REG   0xb8    /* Interrupt remapping table addr register */
  74 #define DMAR_PQH_REG    0xc0    /* Page request queue head register */
  75 #define DMAR_PQT_REG    0xc8    /* Page request queue tail register */
  76 #define DMAR_PQA_REG    0xd0    /* Page request queue address register */
  77 #define DMAR_PRS_REG    0xdc    /* Page request status register */
  78 #define DMAR_PECTL_REG  0xe0    /* Page request event control register */
  79 #define DMAR_PEDATA_REG 0xe4    /* Page request event interrupt data register */
  80 #define DMAR_PEADDR_REG 0xe8    /* Page request event interrupt addr register */
  81 #define DMAR_PEUADDR_REG 0xec   /* Page request event Upper address register */
  82 #define DMAR_MTRRCAP_REG 0x100  /* MTRR capability register */
  83 #define DMAR_MTRRDEF_REG 0x108  /* MTRR default type register */
  84 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
  85 #define DMAR_MTRR_FIX16K_80000_REG 0x128
  86 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
  87 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
  88 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
  89 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
  90 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
  91 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
  92 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
  93 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
  94 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
  95 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
  96 #define DMAR_MTRR_PHYSMASK0_REG 0x188
  97 #define DMAR_MTRR_PHYSBASE1_REG 0x190
  98 #define DMAR_MTRR_PHYSMASK1_REG 0x198
  99 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
 100 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
 101 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
 102 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
 103 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
 104 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
 105 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
 106 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
 107 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
 108 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
 109 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
 110 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
 111 #define DMAR_MTRR_PHYSBASE8_REG 0x200
 112 #define DMAR_MTRR_PHYSMASK8_REG 0x208
 113 #define DMAR_MTRR_PHYSBASE9_REG 0x210
 114 #define DMAR_MTRR_PHYSMASK9_REG 0x218
 115 #define DMAR_VCCAP_REG          0xe00 /* Virtual command capability register */
 116 #define DMAR_VCMD_REG           0xe10 /* Virtual command register */
 117 #define DMAR_VCRSP_REG          0xe20 /* Virtual command response register */
 118
 119 #define OFFSET_STRIDE           (9)
 120
 121 #define dmar_readq(a) readq(a)
 122 #define dmar_writeq(a,v) writeq(v,a)
 123
 124 #define DMAR_VER_MAJOR(v)               (((v) & 0xf0) >> 4)
 125 #define DMAR_VER_MINOR(v)               ((v) & 0x0f)
 126
 127 /*
 128  * Decoding Capability Register
 129  */
 130 #define cap_5lp_support(c)      (((c) >> 60) & 1)
 131 #define cap_pi_support(c)       (((c) >> 59) & 1)
 132 #define cap_fl1gp_support(c)    (((c) >> 56) & 1)
 133 #define cap_read_drain(c)       (((c) >> 55) & 1)
 134 #define cap_write_drain(c)      (((c) >> 54) & 1)
 135 #define cap_max_amask_val(c)    (((c) >> 48) & 0x3f)
 136 #define cap_num_fault_regs(c)   ((((c) >> 40) & 0xff) + 1)
 137 #define cap_pgsel_inv(c)        (((c) >> 39) & 1)
 138
 139 #define cap_super_page_val(c)   (((c) >> 34) & 0xf)
 140 #define cap_super_offset(c)     (((find_first_bit(&cap_super_page_val(c), 4)) \
 141                                         * OFFSET_STRIDE) + 21)
 142
 143 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
 144 #define cap_max_fault_reg_offset(c) \
 145         (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
 146
 147 #define cap_zlr(c)              (((c) >> 22) & 1)
 148 #define cap_isoch(c)            (((c) >> 23) & 1)
 149 #define cap_mgaw(c)             ((((c) >> 16) & 0x3f) + 1)
 150 #define cap_sagaw(c)            (((c) >> 8) & 0x1f)
 151 #define cap_caching_mode(c)     (((c) >> 7) & 1)
 152 #define cap_phmr(c)             (((c) >> 6) & 1)
 153 #define cap_plmr(c)             (((c) >> 5) & 1)
 154 #define cap_rwbf(c)             (((c) >> 4) & 1)
 155 #define cap_afl(c)              (((c) >> 3) & 1)
 156 #define cap_ndoms(c)            (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
 157 /*
 158  * Extended Capability Register
 159  */
 160
 161 #define ecap_smpwc(e)           (((e) >> 48) & 0x1)
 162 #define ecap_flts(e)            (((e) >> 47) & 0x1)
 163 #define ecap_slts(e)            (((e) >> 46) & 0x1)
 164 #define ecap_smts(e)            (((e) >> 43) & 0x1)
 165 #define ecap_dit(e)             ((e >> 41) & 0x1)
 166 #define ecap_pasid(e)           ((e >> 40) & 0x1)
 167 #define ecap_pss(e)             ((e >> 35) & 0x1f)
 168 #define ecap_eafs(e)            ((e >> 34) & 0x1)
 169 #define ecap_nwfs(e)            ((e >> 33) & 0x1)
 170 #define ecap_srs(e)             ((e >> 31) & 0x1)
 171 #define ecap_ers(e)             ((e >> 30) & 0x1)
 172 #define ecap_prs(e)             ((e >> 29) & 0x1)
 173 #define ecap_broken_pasid(e)    ((e >> 28) & 0x1)
 174 #define ecap_dis(e)             ((e >> 27) & 0x1)
 175 #define ecap_nest(e)            ((e >> 26) & 0x1)
 176 #define ecap_mts(e)             ((e >> 25) & 0x1)
 177 #define ecap_ecs(e)             ((e >> 24) & 0x1)
 178 #define ecap_iotlb_offset(e)    ((((e) >> 8) & 0x3ff) * 16)
 179 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
 180 #define ecap_coherent(e)        ((e) & 0x1)
 181 #define ecap_qis(e)             ((e) & 0x2)
 182 #define ecap_pass_through(e)    ((e >> 6) & 0x1)
 183 #define ecap_eim_support(e)     ((e >> 4) & 0x1)
 184 #define ecap_ir_support(e)      ((e >> 3) & 0x1)
 185 #define ecap_dev_iotlb_support(e)       (((e) >> 2) & 0x1)
 186 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
 187 #define ecap_sc_support(e)      ((e >> 7) & 0x1) /* Snooping Control */
 188
 189 /* IOTLB_REG */
 190 #define DMA_TLB_FLUSH_GRANU_OFFSET  60
 191 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
 192 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
 193 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
 194 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
 195 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
 196 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
 197 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
 198 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
 199 #define DMA_TLB_IVT (((u64)1) << 63)
 200 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
 201 #define DMA_TLB_MAX_SIZE (0x3f)
 202
 203 /* INVALID_DESC */
 204 #define DMA_CCMD_INVL_GRANU_OFFSET  61
 205 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
 206 #define DMA_ID_TLB_DSI_FLUSH    (((u64)2) << 4)
 207 #define DMA_ID_TLB_PSI_FLUSH    (((u64)3) << 4)
 208 #define DMA_ID_TLB_READ_DRAIN   (((u64)1) << 7)
 209 #define DMA_ID_TLB_WRITE_DRAIN  (((u64)1) << 6)
 210 #define DMA_ID_TLB_DID(id)      (((u64)((id & 0xffff) << 16)))
 211 #define DMA_ID_TLB_IH_NONLEAF   (((u64)1) << 6)
 212 #define DMA_ID_TLB_ADDR(addr)   (addr)
 213 #define DMA_ID_TLB_ADDR_MASK(mask)      (mask)
 214
 215 /* PMEN_REG */
 216 #define DMA_PMEN_EPM (((u32)1)<<31)
 217 #define DMA_PMEN_PRS (((u32)1)<<0)
 218
 219 /* GCMD_REG */
 220 #define DMA_GCMD_TE (((u32)1) << 31)
 221 #define DMA_GCMD_SRTP (((u32)1) << 30)
 222 #define DMA_GCMD_SFL (((u32)1) << 29)
 223 #define DMA_GCMD_EAFL (((u32)1) << 28)
 224 #define DMA_GCMD_WBF (((u32)1) << 27)
 225 #define DMA_GCMD_QIE (((u32)1) << 26)
 226 #define DMA_GCMD_SIRTP (((u32)1) << 24)
 227 #define DMA_GCMD_IRE (((u32) 1) << 25)
 228 #define DMA_GCMD_CFI (((u32) 1) << 23)
 229
 230 /* GSTS_REG */
 231 #define DMA_GSTS_TES (((u32)1) << 31)
 232 #define DMA_GSTS_RTPS (((u32)1) << 30)
 233 #define DMA_GSTS_FLS (((u32)1) << 29)
 234 #define DMA_GSTS_AFLS (((u32)1) << 28)
 235 #define DMA_GSTS_WBFS (((u32)1) << 27)
 236 #define DMA_GSTS_QIES (((u32)1) << 26)
 237 #define DMA_GSTS_IRTPS (((u32)1) << 24)
 238 #define DMA_GSTS_IRES (((u32)1) << 25)
 239 #define DMA_GSTS_CFIS (((u32)1) << 23)
 240
 241 /* DMA_RTADDR_REG */
 242 #define DMA_RTADDR_RTT (((u64)1) << 11)
 243 #define DMA_RTADDR_SMT (((u64)1) << 10)
 244
 245 /* CCMD_REG */
 246 #define DMA_CCMD_ICC (((u64)1) << 63)
 247 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
 248 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
 249 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
 250 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
 251 #define DMA_CCMD_MASK_NOBIT 0
 252 #define DMA_CCMD_MASK_1BIT 1
 253 #define DMA_CCMD_MASK_2BIT 2
 254 #define DMA_CCMD_MASK_3BIT 3
 255 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
 256 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
 257
 258 /* FECTL_REG */
 259 #define DMA_FECTL_IM (((u32)1) << 31)
 260
 261 /* FSTS_REG */
 262 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
 263 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
 264 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
 265 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
 266 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
 267 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
 268 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
 269
 270 /* FRCD_REG, 32 bits access */
 271 #define DMA_FRCD_F (((u32)1) << 31)
 272 #define dma_frcd_type(d) ((d >> 30) & 1)
 273 #define dma_frcd_fault_reason(c) (c & 0xff)
 274 #define dma_frcd_source_id(c) (c & 0xffff)
 275 /* low 64 bit */
 276 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
 277
 278 /* PRS_REG */
 279 #define DMA_PRS_PPR     ((u32)1)
 280
 281 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)                     \
 282 do {                                                                    \
 283         cycles_t start_time = get_cycles();                             \
 284         while (1) {                                                     \
 285                 sts = op(iommu->reg + offset);                          \
 286                 if (cond)                                               \
 287                         break;                                          \
 288                 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
 289                         panic("DMAR hardware is malfunctioning\n");     \
 290                 cpu_relax();                                            \
 291         }                                                               \
 292 } while (0)
 293
 294 #define QI_LENGTH       256     /* queue length */
 295
 296 enum {
 297         QI_FREE,
 298         QI_IN_USE,
 299         QI_DONE,
 300         QI_ABORT
 301 };
 302
 303 #define QI_CC_TYPE              0x1
 304 #define QI_IOTLB_TYPE           0x2
 305 #define QI_DIOTLB_TYPE          0x3
 306 #define QI_IEC_TYPE             0x4
 307 #define QI_IWD_TYPE             0x5
 308 #define QI_EIOTLB_TYPE          0x6
 309 #define QI_PC_TYPE              0x7
 310 #define QI_DEIOTLB_TYPE         0x8
 311 #define QI_PGRP_RESP_TYPE       0x9
 312 #define QI_PSTRM_RESP_TYPE      0xa
 313
 314 #define QI_IEC_SELECTIVE        (((u64)1) << 4)
 315 #define QI_IEC_IIDEX(idx)       (((u64)(idx & 0xffff) << 32))
 316 #define QI_IEC_IM(m)            (((u64)(m & 0x1f) << 27))
 317
 318 #define QI_IWD_STATUS_DATA(d)   (((u64)d) << 32)
 319 #define QI_IWD_STATUS_WRITE     (((u64)1) << 5)
 320
 321 #define QI_IOTLB_DID(did)       (((u64)did) << 16)
 322 #define QI_IOTLB_DR(dr)         (((u64)dr) << 7)
 323 #define QI_IOTLB_DW(dw)         (((u64)dw) << 6)
 324 #define QI_IOTLB_GRAN(gran)     (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
 325 #define QI_IOTLB_ADDR(addr)     (((u64)addr) & VTD_PAGE_MASK)
 326 #define QI_IOTLB_IH(ih)         (((u64)ih) << 6)
 327 #define QI_IOTLB_AM(am)         (((u8)am))
 328
 329 #define QI_CC_FM(fm)            (((u64)fm) << 48)
 330 #define QI_CC_SID(sid)          (((u64)sid) << 32)
 331 #define QI_CC_DID(did)          (((u64)did) << 16)
 332 #define QI_CC_GRAN(gran)        (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
 333
 334 #define QI_DEV_IOTLB_SID(sid)   ((u64)((sid) & 0xffff) << 32)
 335 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
 336 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
 337 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
 338 #define QI_DEV_IOTLB_SIZE       1
 339 #define QI_DEV_IOTLB_MAX_INVS   32
 340
 341 #define QI_PC_PASID(pasid)      (((u64)pasid) << 32)
 342 #define QI_PC_DID(did)          (((u64)did) << 16)
 343 #define QI_PC_GRAN(gran)        (((u64)gran) << 4)
 344
 345 #define QI_PC_ALL_PASIDS        (QI_PC_TYPE | QI_PC_GRAN(0))
 346 #define QI_PC_PASID_SEL         (QI_PC_TYPE | QI_PC_GRAN(1))
 347
 348 #define QI_EIOTLB_ADDR(addr)    ((u64)(addr) & VTD_PAGE_MASK)
 349 #define QI_EIOTLB_GL(gl)        (((u64)gl) << 7)
 350 #define QI_EIOTLB_IH(ih)        (((u64)ih) << 6)
 351 #define QI_EIOTLB_AM(am)        (((u64)am))
 352 #define QI_EIOTLB_PASID(pasid)  (((u64)pasid) << 32)
 353 #define QI_EIOTLB_DID(did)      (((u64)did) << 16)
 354 #define QI_EIOTLB_GRAN(gran)    (((u64)gran) << 4)
 355
 356 #define QI_DEV_EIOTLB_ADDR(a)   ((u64)(a) & VTD_PAGE_MASK)
 357 #define QI_DEV_EIOTLB_SIZE      (((u64)1) << 11)
 358 #define QI_DEV_EIOTLB_GLOB(g)   ((u64)g)
 359 #define QI_DEV_EIOTLB_PASID(p)  (((u64)p) << 32)
 360 #define QI_DEV_EIOTLB_SID(sid)  ((u64)((sid) & 0xffff) << 16)
 361 #define QI_DEV_EIOTLB_QDEP(qd)  ((u64)((qd) & 0x1f) << 4)
 362 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
 363 #define QI_DEV_EIOTLB_MAX_INVS  32
 364
 365 /* Page group response descriptor QW0 */
 366 #define QI_PGRP_PASID_P(p)      (((u64)(p)) << 4)
 367 #define QI_PGRP_PDP(p)          (((u64)(p)) << 5)
 368 #define QI_PGRP_RESP_CODE(res)  (((u64)(res)) << 12)
 369 #define QI_PGRP_DID(rid)        (((u64)(rid)) << 16)
 370 #define QI_PGRP_PASID(pasid)    (((u64)(pasid)) << 32)
 371
 372 /* Page group response descriptor QW1 */
 373 #define QI_PGRP_LPIG(x)         (((u64)(x)) << 2)
 374 #define QI_PGRP_IDX(idx)        (((u64)(idx)) << 3)
 375
 376
 377 #define QI_RESP_SUCCESS         0x0
 378 #define QI_RESP_INVALID         0x1
 379 #define QI_RESP_FAILURE         0xf
 380
 381 #define QI_GRAN_ALL_ALL                 0
 382 #define QI_GRAN_NONG_ALL                1
 383 #define QI_GRAN_NONG_PASID              2
 384 #define QI_GRAN_PSI_PASID               3
 385
 386 #define qi_shift(iommu)         (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
 387
 388 struct qi_desc {
 389         u64 qw0;
 390         u64 qw1;
 391         u64 qw2;
 392         u64 qw3;
 393 };
 394
 395 struct q_inval {
 396         raw_spinlock_t  q_lock;
 397         void            *desc;          /* invalidation queue */
 398         int             *desc_status;   /* desc status */
 399         int             free_head;      /* first free entry */
 400         int             free_tail;      /* last free entry */
 401         int             free_cnt;
 402 };
 403
 404 #ifdef CONFIG_IRQ_REMAP
 405 /* 1MB - maximum possible interrupt remapping table size */
 406 #define INTR_REMAP_PAGE_ORDER   8
 407 #define INTR_REMAP_TABLE_REG_SIZE       0xf
 408 #define INTR_REMAP_TABLE_REG_SIZE_MASK  0xf
 409
 410 #define INTR_REMAP_TABLE_ENTRIES        65536
 411
 412 struct irq_domain;
 413
 414 struct ir_table {
 415         struct irte *base;
 416         unsigned long *bitmap;
 417 };
 418 #endif
 419
 420 struct iommu_flush {
 421         void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
 422                               u8 fm, u64 type);
 423         void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
 424                             unsigned int size_order, u64 type);
 425 };
 426
 427 enum {
 428         SR_DMAR_FECTL_REG,
 429         SR_DMAR_FEDATA_REG,
 430         SR_DMAR_FEADDR_REG,
 431         SR_DMAR_FEUADDR_REG,
 432         MAX_SR_DMAR_REGS
 433 };
 434
 435 #define VTD_FLAG_TRANS_PRE_ENABLED      (1 << 0)
 436 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED  (1 << 1)
 437
 438 struct pasid_entry;
 439 struct pasid_state_entry;
 440 struct page_req_dsc;
 441
 442 /*
 443  * 0: Present
 444  * 1-11: Reserved
 445  * 12-63: Context Ptr (12 - (haw-1))
 446  * 64-127: Reserved
 447  */
 448 struct root_entry {
 449         u64     lo;
 450         u64     hi;
 451 };
 452
 453 /*
 454  * low 64 bits:
 455  * 0: present
 456  * 1: fault processing disable
 457  * 2-3: translation type
 458  * 12-63: address space root
 459  * high 64 bits:
 460  * 0-2: address width
 461  * 3-6: aval
 462  * 8-23: domain id
 463  */
 464 struct context_entry {
 465         u64 lo;
 466         u64 hi;
 467 };
 468
 469 struct dmar_domain {
 470         int     nid;                    /* node id */
 471
 472         unsigned        iommu_refcnt[DMAR_UNITS_SUPPORTED];
 473                                         /* Refcount of devices per iommu */
 474
 475
 476         u16             iommu_did[DMAR_UNITS_SUPPORTED];
 477                                         /* Domain ids per IOMMU. Use u16 since
 478                                          * domain ids are 16 bit wide according
 479                                          * to VT-d spec, section 9.3 */
 480         unsigned int    auxd_refcnt;    /* Refcount of auxiliary attaching */
 481
 482         bool has_iotlb_device;
 483         struct list_head devices;       /* all devices' list */
 484         struct list_head auxd;          /* link to device's auxiliary list */
 485         struct iova_domain iovad;       /* iova's that belong to this domain */
 486
 487         struct dma_pte  *pgd;           /* virtual address */
 488         int             gaw;            /* max guest address width */
 489
 490         /* adjusted guest address width, 0 is level 2 30-bit */
 491         int             agaw;
 492
 493         int             flags;          /* flags to find out type of domain */
 494
 495         int             iommu_coherency;/* indicate coherency of iommu access */
 496         int             iommu_snooping; /* indicate snooping control feature*/
 497         int             iommu_count;    /* reference count of iommu */
 498         int             iommu_superpage;/* Level of superpages supported:
 499                                            0 == 4KiB (no superpages), 1 == 2MiB,
 500                                            2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
 501         u64             max_addr;       /* maximum mapped address */
 502
 503         int             default_pasid;  /*
 504                                          * The default pasid used for non-SVM
 505                                          * traffic on mediated devices.
 506                                          */
 507
 508         struct iommu_domain domain;     /* generic domain data structure for
 509                                            iommu core */
 510 };
 511
 512 struct intel_iommu {
 513         void __iomem    *reg; /* Pointer to hardware regs, virtual addr */
 514         u64             reg_phys; /* physical address of hw register set */
 515         u64             reg_size; /* size of hw register set */
 516         u64             cap;
 517         u64             ecap;
 518         u32             gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
 519         raw_spinlock_t  register_lock; /* protect register handling */
 520         int             seq_id; /* sequence id of the iommu */
 521         int             agaw; /* agaw of this iommu */
 522         int             msagaw; /* max sagaw of this iommu */
 523         unsigned int    irq, pr_irq;
 524         u16             segment;     /* PCI segment# */
 525         unsigned char   name[13];    /* Device Name */
 526
 527 #ifdef CONFIG_INTEL_IOMMU
 528         unsigned long   *domain_ids; /* bitmap of domains */
 529         struct dmar_domain ***domains; /* ptr to domains */
 530         spinlock_t      lock; /* protect context, domain ids */
 531         struct root_entry *root_entry; /* virtual address */
 532
 533         struct iommu_flush flush;
 534 #endif
 535 #ifdef CONFIG_INTEL_IOMMU_SVM
 536         struct page_req_dsc *prq;
 537         unsigned char prq_name[16];    /* Name for PRQ interrupt */
 538 #endif
 539         struct q_inval  *qi;            /* Queued invalidation info */
 540         u32 *iommu_state; /* Store iommu states between suspend and resume.*/
 541
 542 #ifdef CONFIG_IRQ_REMAP
 543         struct ir_table *ir_table;      /* Interrupt remapping info */
 544         struct irq_domain *ir_domain;
 545         struct irq_domain *ir_msi_domain;
 546 #endif
 547         struct iommu_device iommu;  /* IOMMU core code handle */
 548         int             node;
 549         u32             flags;      /* Software defined flags */
 550 };
 551
 552 /* PCI domain-device relationship */
 553 struct device_domain_info {
 554         struct list_head link;  /* link to domain siblings */
 555         struct list_head global; /* link to global list */
 556         struct list_head table; /* link to pasid table */
 557         struct list_head auxiliary_domains; /* auxiliary domains
 558                                              * attached to this device
 559                                              */
 560         u8 bus;                 /* PCI bus number */
 561         u8 devfn;               /* PCI devfn number */
 562         u16 pfsid;              /* SRIOV physical function source ID */
 563         u8 pasid_supported:3;
 564         u8 pasid_enabled:1;
 565         u8 pri_supported:1;
 566         u8 pri_enabled:1;
 567         u8 ats_supported:1;
 568         u8 ats_enabled:1;
 569         u8 auxd_enabled:1;      /* Multiple domains per device */
 570         u8 ats_qdep;
 571         struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
 572         struct intel_iommu *iommu; /* IOMMU used by this device */
 573         struct dmar_domain *domain; /* pointer to domain */
 574         struct pasid_table *pasid_table; /* pasid table */
 575 };
 576
 577 static inline void __iommu_flush_cache(
 578         struct intel_iommu *iommu, void *addr, int size)
 579 {
 580         if (!ecap_coherent(iommu->ecap))
 581                 clflush_cache_range(addr, size);
 582 }
 583
 584 /*
 585  * 0: readable
 586  * 1: writable
 587  * 2-6: reserved
 588  * 7: super page
 589  * 8-10: available
 590  * 11: snoop behavior
 591  * 12-63: Host physcial address
 592  */
 593 struct dma_pte {
 594         u64 val;
 595 };
 596
 597 static inline void dma_clear_pte(struct dma_pte *pte)
 598 {
 599         pte->val = 0;
 600 }
 601
 602 static inline u64 dma_pte_addr(struct dma_pte *pte)
 603 {
 604 #ifdef CONFIG_64BIT
 605         return pte->val & VTD_PAGE_MASK;
 606 #else
 607         /* Must have a full atomic 64-bit read */
 608         return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
 609 #endif
 610 }
 611
 612 static inline bool dma_pte_present(struct dma_pte *pte)
 613 {
 614         return (pte->val & 3) != 0;
 615 }
 616
 617 static inline bool dma_pte_superpage(struct dma_pte *pte)
 618 {
 619         return (pte->val & DMA_PTE_LARGE_PAGE);
 620 }
 621
 622 static inline int first_pte_in_page(struct dma_pte *pte)
 623 {
 624         return !((unsigned long)pte & ~VTD_PAGE_MASK);
 625 }
 626
 627 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
 628 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
 629
 630 extern int dmar_enable_qi(struct intel_iommu *iommu);
 631 extern void dmar_disable_qi(struct intel_iommu *iommu);
 632 extern int dmar_reenable_qi(struct intel_iommu *iommu);
 633 extern void qi_global_iec(struct intel_iommu *iommu);
 634
 635 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
 636                              u8 fm, u64 type);
 637 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
 638                           unsigned int size_order, u64 type);
 639 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
 640                         u16 qdep, u64 addr, unsigned mask);
 641 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
 642
 643 extern int dmar_ir_support(void);
 644
 645 struct dmar_domain *get_valid_domain_for_dev(struct device *dev);
 646 void *alloc_pgtable_page(int node);
 647 void free_pgtable_page(void *vaddr);
 648 struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
 649 int for_each_device_domain(int (*fn)(struct device_domain_info *info,
 650                                      void *data), void *data);
 651 void iommu_flush_write_buffer(struct intel_iommu *iommu);
 652 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
 653
 654 #ifdef CONFIG_INTEL_IOMMU_SVM
 655 int intel_svm_init(struct intel_iommu *iommu);
 656 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
 657 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
 658
 659 struct svm_dev_ops;
 660
 661 struct intel_svm_dev {
 662         struct list_head list;
 663         struct rcu_head rcu;
 664         struct device *dev;
 665         struct svm_dev_ops *ops;
 666         int users;
 667         u16 did;
 668         u16 dev_iotlb:1;
 669         u16 sid, qdep;
 670 };
 671
 672 struct intel_svm {
 673         struct mmu_notifier notifier;
 674         struct mm_struct *mm;
 675         struct intel_iommu *iommu;
 676         int flags;
 677         int pasid;
 678         struct list_head devs;
 679         struct list_head list;
 680 };
 681
 682 extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
 683 #endif
 684
 685 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
 686 void intel_iommu_debugfs_init(void);
 687 #else
 688 static inline void intel_iommu_debugfs_init(void) {}
 689 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
 690
 691 extern const struct attribute_group *intel_iommu_groups[];
 692 bool context_present(struct context_entry *context);
 693 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
 694                                          u8 devfn, int alloc);
 695
 696 #ifdef CONFIG_INTEL_IOMMU
 697 extern int iommu_calculate_agaw(struct intel_iommu *iommu);
 698 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
 699 extern int dmar_disabled;
 700 extern int intel_iommu_enabled;
 701 extern int intel_iommu_tboot_noforce;
 702 #else
 703 static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
 704 {
 705         return 0;
 706 }
 707 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
 708 {
 709         return 0;
 710 }
 711 #define dmar_disabled   (1)
 712 #define intel_iommu_enabled (0)
 713 #endif
 714
 715 #endif