2 * Copyright © 2006-2015, Intel Corporation.
4 * Authors: Ashok Raj <ashok.raj@intel.com>
5 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
6 * David Woodhouse <David.Woodhouse@intel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
22 #ifndef _INTEL_IOMMU_H_
23 #define _INTEL_IOMMU_H_
25 #include <linux/types.h>
26 #include <linux/iova.h>
28 #include <linux/idr.h>
29 #include <linux/dma_remapping.h>
30 #include <linux/mmu_notifier.h>
31 #include <linux/list.h>
32 #include <linux/iommu.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include <linux/dmar.h>
36 #include <asm/cacheflush.h>
37 #include <asm/iommu.h>
40 * Intel IOMMU register specification per version 1.0 public spec.
43 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
44 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
45 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
46 #define DMAR_GCMD_REG 0x18 /* Global command register */
47 #define DMAR_GSTS_REG 0x1c /* Global status register */
48 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
49 #define DMAR_CCMD_REG 0x28 /* Context command reg */
50 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
51 #define DMAR_FECTL_REG 0x38 /* Fault control register */
52 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
53 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
54 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
55 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
56 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
57 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
58 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
59 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
60 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
61 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
62 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
63 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
64 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
65 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
66 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
67 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
68 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
69 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
70 #define DMAR_PRS_REG 0xdc /* Page request status register */
71 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
72 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
73 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
74 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
75 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
76 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
77 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
78 #define DMAR_MTRR_FIX16K_80000_REG 0x128
79 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
80 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
81 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
82 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
83 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
84 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
85 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
86 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
87 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
88 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
89 #define DMAR_MTRR_PHYSMASK0_REG 0x188
90 #define DMAR_MTRR_PHYSBASE1_REG 0x190
91 #define DMAR_MTRR_PHYSMASK1_REG 0x198
92 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
93 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
94 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
95 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
96 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
97 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
98 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
99 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
100 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
101 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
102 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
103 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
104 #define DMAR_MTRR_PHYSBASE8_REG 0x200
105 #define DMAR_MTRR_PHYSMASK8_REG 0x208
106 #define DMAR_MTRR_PHYSBASE9_REG 0x210
107 #define DMAR_MTRR_PHYSMASK9_REG 0x218
108 #define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */
109 #define DMAR_VCMD_REG 0xe10 /* Virtual command register */
110 #define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */
112 #define OFFSET_STRIDE (9)
114 #define dmar_readq(a) readq(a)
115 #define dmar_writeq(a,v) writeq(v,a)
117 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
118 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
121 * Decoding Capability Register
123 #define cap_5lp_support(c) (((c) >> 60) & 1)
124 #define cap_pi_support(c) (((c) >> 59) & 1)
125 #define cap_fl1gp_support(c) (((c) >> 56) & 1)
126 #define cap_read_drain(c) (((c) >> 55) & 1)
127 #define cap_write_drain(c) (((c) >> 54) & 1)
128 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
129 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
130 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
132 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
133 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
134 * OFFSET_STRIDE) + 21)
136 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
137 #define cap_max_fault_reg_offset(c) \
138 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
140 #define cap_zlr(c) (((c) >> 22) & 1)
141 #define cap_isoch(c) (((c) >> 23) & 1)
142 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
143 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
144 #define cap_caching_mode(c) (((c) >> 7) & 1)
145 #define cap_phmr(c) (((c) >> 6) & 1)
146 #define cap_plmr(c) (((c) >> 5) & 1)
147 #define cap_rwbf(c) (((c) >> 4) & 1)
148 #define cap_afl(c) (((c) >> 3) & 1)
149 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
151 * Extended Capability Register
154 #define ecap_dit(e) ((e >> 41) & 0x1)
155 #define ecap_pasid(e) ((e >> 40) & 0x1)
156 #define ecap_pss(e) ((e >> 35) & 0x1f)
157 #define ecap_eafs(e) ((e >> 34) & 0x1)
158 #define ecap_nwfs(e) ((e >> 33) & 0x1)
159 #define ecap_srs(e) ((e >> 31) & 0x1)
160 #define ecap_ers(e) ((e >> 30) & 0x1)
161 #define ecap_prs(e) ((e >> 29) & 0x1)
162 #define ecap_broken_pasid(e) ((e >> 28) & 0x1)
163 #define ecap_dis(e) ((e >> 27) & 0x1)
164 #define ecap_nest(e) ((e >> 26) & 0x1)
165 #define ecap_mts(e) ((e >> 25) & 0x1)
166 #define ecap_ecs(e) ((e >> 24) & 0x1)
167 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
168 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
169 #define ecap_coherent(e) ((e) & 0x1)
170 #define ecap_qis(e) ((e) & 0x2)
171 #define ecap_pass_through(e) ((e >> 6) & 0x1)
172 #define ecap_eim_support(e) ((e >> 4) & 0x1)
173 #define ecap_ir_support(e) ((e >> 3) & 0x1)
174 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
175 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
176 #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
179 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
180 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
181 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
182 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
183 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
184 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
185 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
186 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
187 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
188 #define DMA_TLB_IVT (((u64)1) << 63)
189 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
190 #define DMA_TLB_MAX_SIZE (0x3f)
193 #define DMA_CCMD_INVL_GRANU_OFFSET 61
194 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
195 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
196 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
197 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
198 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
199 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
200 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
201 #define DMA_ID_TLB_ADDR(addr) (addr)
202 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
205 #define DMA_PMEN_EPM (((u32)1)<<31)
206 #define DMA_PMEN_PRS (((u32)1)<<0)
209 #define DMA_GCMD_TE (((u32)1) << 31)
210 #define DMA_GCMD_SRTP (((u32)1) << 30)
211 #define DMA_GCMD_SFL (((u32)1) << 29)
212 #define DMA_GCMD_EAFL (((u32)1) << 28)
213 #define DMA_GCMD_WBF (((u32)1) << 27)
214 #define DMA_GCMD_QIE (((u32)1) << 26)
215 #define DMA_GCMD_SIRTP (((u32)1) << 24)
216 #define DMA_GCMD_IRE (((u32) 1) << 25)
217 #define DMA_GCMD_CFI (((u32) 1) << 23)
220 #define DMA_GSTS_TES (((u32)1) << 31)
221 #define DMA_GSTS_RTPS (((u32)1) << 30)
222 #define DMA_GSTS_FLS (((u32)1) << 29)
223 #define DMA_GSTS_AFLS (((u32)1) << 28)
224 #define DMA_GSTS_WBFS (((u32)1) << 27)
225 #define DMA_GSTS_QIES (((u32)1) << 26)
226 #define DMA_GSTS_IRTPS (((u32)1) << 24)
227 #define DMA_GSTS_IRES (((u32)1) << 25)
228 #define DMA_GSTS_CFIS (((u32)1) << 23)
231 #define DMA_RTADDR_RTT (((u64)1) << 11)
234 #define DMA_CCMD_ICC (((u64)1) << 63)
235 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
236 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
237 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
238 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
239 #define DMA_CCMD_MASK_NOBIT 0
240 #define DMA_CCMD_MASK_1BIT 1
241 #define DMA_CCMD_MASK_2BIT 2
242 #define DMA_CCMD_MASK_3BIT 3
243 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
244 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
247 #define DMA_FECTL_IM (((u32)1) << 31)
250 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
251 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
252 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
253 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
254 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
255 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
256 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
258 /* FRCD_REG, 32 bits access */
259 #define DMA_FRCD_F (((u32)1) << 31)
260 #define dma_frcd_type(d) ((d >> 30) & 1)
261 #define dma_frcd_fault_reason(c) (c & 0xff)
262 #define dma_frcd_source_id(c) (c & 0xffff)
264 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
267 #define DMA_PRS_PPR ((u32)1)
269 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
271 cycles_t start_time = get_cycles(); \
273 sts = op(iommu->reg + offset); \
276 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
277 panic("DMAR hardware is malfunctioning\n"); \
282 #define QI_LENGTH 256 /* queue length */
291 #define QI_CC_TYPE 0x1
292 #define QI_IOTLB_TYPE 0x2
293 #define QI_DIOTLB_TYPE 0x3
294 #define QI_IEC_TYPE 0x4
295 #define QI_IWD_TYPE 0x5
296 #define QI_EIOTLB_TYPE 0x6
297 #define QI_PC_TYPE 0x7
298 #define QI_DEIOTLB_TYPE 0x8
299 #define QI_PGRP_RESP_TYPE 0x9
300 #define QI_PSTRM_RESP_TYPE 0xa
302 #define QI_IEC_SELECTIVE (((u64)1) << 4)
303 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
304 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
306 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
307 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
309 #define QI_IOTLB_DID(did) (((u64)did) << 16)
310 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
311 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
312 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
313 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
314 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
315 #define QI_IOTLB_AM(am) (((u8)am))
317 #define QI_CC_FM(fm) (((u64)fm) << 48)
318 #define QI_CC_SID(sid) (((u64)sid) << 32)
319 #define QI_CC_DID(did) (((u64)did) << 16)
320 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
322 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
323 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
324 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
325 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
326 #define QI_DEV_IOTLB_SIZE 1
327 #define QI_DEV_IOTLB_MAX_INVS 32
329 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
330 #define QI_PC_DID(did) (((u64)did) << 16)
331 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
333 #define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
334 #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
336 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
337 #define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
338 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
339 #define QI_EIOTLB_AM(am) (((u64)am))
340 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
341 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
342 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
344 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
345 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
346 #define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
347 #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
348 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
349 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
350 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
351 #define QI_DEV_EIOTLB_MAX_INVS 32
353 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
354 #define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
355 #define QI_PGRP_RESP_CODE(res) ((u64)(res))
356 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
357 #define QI_PGRP_DID(did) (((u64)(did)) << 16)
358 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
360 #define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
361 #define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
362 #define QI_PSTRM_RESP_CODE(res) ((u64)(res))
363 #define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
364 #define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
365 #define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
366 #define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
368 #define QI_RESP_SUCCESS 0x0
369 #define QI_RESP_INVALID 0x1
370 #define QI_RESP_FAILURE 0xf
372 #define QI_GRAN_ALL_ALL 0
373 #define QI_GRAN_NONG_ALL 1
374 #define QI_GRAN_NONG_PASID 2
375 #define QI_GRAN_PSI_PASID 3
382 raw_spinlock_t q_lock
;
383 struct qi_desc
*desc
; /* invalidation queue */
384 int *desc_status
; /* desc status */
385 int free_head
; /* first free entry */
386 int free_tail
; /* last free entry */
390 #ifdef CONFIG_IRQ_REMAP
391 /* 1MB - maximum possible interrupt remapping table size */
392 #define INTR_REMAP_PAGE_ORDER 8
393 #define INTR_REMAP_TABLE_REG_SIZE 0xf
394 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
396 #define INTR_REMAP_TABLE_ENTRIES 65536
402 unsigned long *bitmap
;
407 void (*flush_context
)(struct intel_iommu
*iommu
, u16 did
, u16 sid
,
409 void (*flush_iotlb
)(struct intel_iommu
*iommu
, u16 did
, u64 addr
,
410 unsigned int size_order
, u64 type
);
421 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
422 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
425 struct pasid_state_entry
;
431 * 12-63: Context Ptr (12 - (haw-1))
442 * 1: fault processing disable
443 * 2-3: translation type
444 * 12-63: address space root
450 struct context_entry
{
456 int nid
; /* node id */
458 unsigned iommu_refcnt
[DMAR_UNITS_SUPPORTED
];
459 /* Refcount of devices per iommu */
462 u16 iommu_did
[DMAR_UNITS_SUPPORTED
];
463 /* Domain ids per IOMMU. Use u16 since
464 * domain ids are 16 bit wide according
465 * to VT-d spec, section 9.3 */
467 bool has_iotlb_device
;
468 struct list_head devices
; /* all devices' list */
469 struct iova_domain iovad
; /* iova's that belong to this domain */
471 struct dma_pte
*pgd
; /* virtual address */
472 int gaw
; /* max guest address width */
474 /* adjusted guest address width, 0 is level 2 30-bit */
477 int flags
; /* flags to find out type of domain */
479 int iommu_coherency
;/* indicate coherency of iommu access */
480 int iommu_snooping
; /* indicate snooping control feature*/
481 int iommu_count
; /* reference count of iommu */
482 int iommu_superpage
;/* Level of superpages supported:
483 0 == 4KiB (no superpages), 1 == 2MiB,
484 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
485 u64 max_addr
; /* maximum mapped address */
487 struct iommu_domain domain
; /* generic domain data structure for
492 void __iomem
*reg
; /* Pointer to hardware regs, virtual addr */
493 u64 reg_phys
; /* physical address of hw register set */
494 u64 reg_size
; /* size of hw register set */
497 u32 gcmd
; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
498 raw_spinlock_t register_lock
; /* protect register handling */
499 int seq_id
; /* sequence id of the iommu */
500 int agaw
; /* agaw of this iommu */
501 int msagaw
; /* max sagaw of this iommu */
502 unsigned int irq
, pr_irq
;
503 u16 segment
; /* PCI segment# */
504 unsigned char name
[13]; /* Device Name */
506 #ifdef CONFIG_INTEL_IOMMU
507 unsigned long *domain_ids
; /* bitmap of domains */
508 struct dmar_domain
***domains
; /* ptr to domains */
509 spinlock_t lock
; /* protect context, domain ids */
510 struct root_entry
*root_entry
; /* virtual address */
512 struct iommu_flush flush
;
514 #ifdef CONFIG_INTEL_IOMMU_SVM
515 /* These are large and need to be contiguous, so we allocate just
516 * one for now. We'll maybe want to rethink that if we truly give
517 * devices away to userspace processes (e.g. for DPDK) and don't
518 * want to trust that userspace will use *only* the PASID it was
519 * told to. But while it's all driver-arbitrated, we're fine. */
520 struct pasid_state_entry
*pasid_state_table
;
521 struct page_req_dsc
*prq
;
522 unsigned char prq_name
[16]; /* Name for PRQ interrupt */
525 struct q_inval
*qi
; /* Queued invalidation info */
526 u32
*iommu_state
; /* Store iommu states between suspend and resume.*/
528 #ifdef CONFIG_IRQ_REMAP
529 struct ir_table
*ir_table
; /* Interrupt remapping info */
530 struct irq_domain
*ir_domain
;
531 struct irq_domain
*ir_msi_domain
;
533 struct iommu_device iommu
; /* IOMMU core code handle */
535 u32 flags
; /* Software defined flags */
538 /* PCI domain-device relationship */
539 struct device_domain_info
{
540 struct list_head link
; /* link to domain siblings */
541 struct list_head global
; /* link to global list */
542 struct list_head table
; /* link to pasid table */
543 u8 bus
; /* PCI bus number */
544 u8 devfn
; /* PCI devfn number */
545 u16 pfsid
; /* SRIOV physical function source ID */
546 u8 pasid_supported
:3;
553 struct device
*dev
; /* it's NULL for PCIe-to-PCI bridge */
554 struct intel_iommu
*iommu
; /* IOMMU used by this device */
555 struct dmar_domain
*domain
; /* pointer to domain */
556 struct pasid_table
*pasid_table
; /* pasid table */
559 static inline void __iommu_flush_cache(
560 struct intel_iommu
*iommu
, void *addr
, int size
)
562 if (!ecap_coherent(iommu
->ecap
))
563 clflush_cache_range(addr
, size
);
566 extern struct dmar_drhd_unit
* dmar_find_matched_drhd_unit(struct pci_dev
*dev
);
567 extern int dmar_find_matched_atsr_unit(struct pci_dev
*dev
);
569 extern int dmar_enable_qi(struct intel_iommu
*iommu
);
570 extern void dmar_disable_qi(struct intel_iommu
*iommu
);
571 extern int dmar_reenable_qi(struct intel_iommu
*iommu
);
572 extern void qi_global_iec(struct intel_iommu
*iommu
);
574 extern void qi_flush_context(struct intel_iommu
*iommu
, u16 did
, u16 sid
,
576 extern void qi_flush_iotlb(struct intel_iommu
*iommu
, u16 did
, u64 addr
,
577 unsigned int size_order
, u64 type
);
578 extern void qi_flush_dev_iotlb(struct intel_iommu
*iommu
, u16 sid
, u16 pfsid
,
579 u16 qdep
, u64 addr
, unsigned mask
);
580 extern int qi_submit_sync(struct qi_desc
*desc
, struct intel_iommu
*iommu
);
582 extern int dmar_ir_support(void);
584 struct dmar_domain
*get_valid_domain_for_dev(struct device
*dev
);
585 void *alloc_pgtable_page(int node
);
586 void free_pgtable_page(void *vaddr
);
587 struct intel_iommu
*domain_get_iommu(struct dmar_domain
*domain
);
588 int for_each_device_domain(int (*fn
)(struct device_domain_info
*info
,
589 void *data
), void *data
);
591 #ifdef CONFIG_INTEL_IOMMU_SVM
592 int intel_svm_init(struct intel_iommu
*iommu
);
593 int intel_svm_exit(struct intel_iommu
*iommu
);
594 extern int intel_svm_enable_prq(struct intel_iommu
*iommu
);
595 extern int intel_svm_finish_prq(struct intel_iommu
*iommu
);
599 struct intel_svm_dev
{
600 struct list_head list
;
603 struct svm_dev_ops
*ops
;
611 struct mmu_notifier notifier
;
612 struct mm_struct
*mm
;
613 struct intel_iommu
*iommu
;
616 struct list_head devs
;
617 struct list_head list
;
620 extern int intel_iommu_enable_pasid(struct intel_iommu
*iommu
, struct intel_svm_dev
*sdev
);
621 extern struct intel_iommu
*intel_svm_device_to_iommu(struct device
*dev
);
624 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
625 void intel_iommu_debugfs_init(void);
627 static inline void intel_iommu_debugfs_init(void) {}
628 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
630 extern const struct attribute_group
*intel_iommu_groups
[];
631 bool context_present(struct context_entry
*context
);
632 struct context_entry
*iommu_context_addr(struct intel_iommu
*iommu
, u8 bus
,
633 u8 devfn
, int alloc
);