5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
25 #include <linux/slab.h>
28 #include <asm/ptrace.h>
29 #include <asm/irq_regs.h>
34 enum irqchip_irq_state
;
39 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
41 * IRQ_TYPE_NONE - default, unspecified type
42 * IRQ_TYPE_EDGE_RISING - rising edge triggered
43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
45 * IRQ_TYPE_LEVEL_HIGH - high level triggered
46 * IRQ_TYPE_LEVEL_LOW - low level triggered
47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
49 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
50 * to setup the HW to a sane default (used
51 * by irqdomain map() callbacks to synchronize
52 * the HW state and SW flags for a newly
53 * allocated descriptor).
55 * IRQ_TYPE_PROBE - Special flag for probing in progress
57 * Bits which can be modified via irq_set/clear/modify_status_flags()
58 * IRQ_LEVEL - Interrupt is level type. Will be also
59 * updated in the code when the above trigger
60 * bits are modified via irq_set_irq_type()
61 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
62 * it from affinity setting
63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
64 * IRQ_NOREQUEST - Interrupt cannot be requested via
66 * IRQ_NOTHREAD - Interrupt cannot be threaded
67 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
71 * IRQ_NESTED_THREAD - Interrupt nests into another thread
72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
73 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
74 * it from the spurious interrupt detection
75 * mechanism and from core side polling.
76 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
79 IRQ_TYPE_NONE
= 0x00000000,
80 IRQ_TYPE_EDGE_RISING
= 0x00000001,
81 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
82 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
83 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
84 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
85 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
86 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
87 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
89 IRQ_TYPE_PROBE
= 0x00000010,
92 IRQ_PER_CPU
= (1 << 9),
93 IRQ_NOPROBE
= (1 << 10),
94 IRQ_NOREQUEST
= (1 << 11),
95 IRQ_NOAUTOEN
= (1 << 12),
96 IRQ_NO_BALANCING
= (1 << 13),
97 IRQ_MOVE_PCNTXT
= (1 << 14),
98 IRQ_NESTED_THREAD
= (1 << 15),
99 IRQ_NOTHREAD
= (1 << 16),
100 IRQ_PER_CPU_DEVID
= (1 << 17),
101 IRQ_IS_POLLED
= (1 << 18),
102 IRQ_DISABLE_UNLAZY
= (1 << 19),
105 #define IRQF_MODIFY_MASK \
106 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
107 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
108 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
109 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
111 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
114 * Return value for chip->irq_set_affinity()
116 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
117 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
118 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
119 * support stacked irqchips, which indicates skipping
120 * all descendent irqchips.
124 IRQ_SET_MASK_OK_NOCOPY
,
125 IRQ_SET_MASK_OK_DONE
,
132 * struct irq_common_data - per irq data shared by all irqchips
133 * @state_use_accessors: status information for irq chip functions.
134 * Use accessor functions to deal with it
135 * @node: node index useful for balancing
136 * @handler_data: per-IRQ data for the irq_chip methods
137 * @affinity: IRQ affinity on SMP. If this is an IPI
138 * related irq, then this is the mask of the
139 * CPUs to which an IPI can be sent.
140 * @effective_affinity: The effective IRQ affinity on SMP as some irq
141 * chips do not allow multi CPU destinations.
142 * A subset of @affinity.
143 * @msi_desc: MSI descriptor
144 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
146 struct irq_common_data
{
147 unsigned int __private state_use_accessors
;
152 struct msi_desc
*msi_desc
;
153 cpumask_var_t affinity
;
154 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
155 cpumask_var_t effective_affinity
;
157 #ifdef CONFIG_GENERIC_IRQ_IPI
158 unsigned int ipi_offset
;
163 * struct irq_data - per irq chip data passed down to chip functions
164 * @mask: precomputed bitmask for accessing the chip registers
165 * @irq: interrupt number
166 * @hwirq: hardware interrupt number, local to the interrupt domain
167 * @common: point to data shared by all irqchips
168 * @chip: low level interrupt hardware access
169 * @domain: Interrupt translation domain; responsible for mapping
170 * between hwirq number and linux irq number.
171 * @parent_data: pointer to parent struct irq_data to support hierarchy
173 * @chip_data: platform-specific per-chip private data for the chip
174 * methods, to allow shared chip implementations
180 struct irq_common_data
*common
;
181 struct irq_chip
*chip
;
182 struct irq_domain
*domain
;
183 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
184 struct irq_data
*parent_data
;
190 * Bit masks for irq_common_data.state_use_accessors
192 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
193 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
194 * IRQD_ACTIVATED - Interrupt has already been activated
195 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
196 * IRQD_PER_CPU - Interrupt is per cpu
197 * IRQD_AFFINITY_SET - Interrupt affinity was set
198 * IRQD_LEVEL - Interrupt is level triggered
199 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
201 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
203 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
204 * IRQD_IRQ_MASKED - Masked state of the interrupt
205 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
206 * IRQD_WAKEUP_ARMED - Wakeup mode armed
207 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
208 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
209 * IRQD_IRQ_STARTED - Startup state of the interrupt
210 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
211 * mask. Applies only to affinity managed irqs.
212 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
215 IRQD_TRIGGER_MASK
= 0xf,
216 IRQD_SETAFFINITY_PENDING
= (1 << 8),
217 IRQD_ACTIVATED
= (1 << 9),
218 IRQD_NO_BALANCING
= (1 << 10),
219 IRQD_PER_CPU
= (1 << 11),
220 IRQD_AFFINITY_SET
= (1 << 12),
221 IRQD_LEVEL
= (1 << 13),
222 IRQD_WAKEUP_STATE
= (1 << 14),
223 IRQD_MOVE_PCNTXT
= (1 << 15),
224 IRQD_IRQ_DISABLED
= (1 << 16),
225 IRQD_IRQ_MASKED
= (1 << 17),
226 IRQD_IRQ_INPROGRESS
= (1 << 18),
227 IRQD_WAKEUP_ARMED
= (1 << 19),
228 IRQD_FORWARDED_TO_VCPU
= (1 << 20),
229 IRQD_AFFINITY_MANAGED
= (1 << 21),
230 IRQD_IRQ_STARTED
= (1 << 22),
231 IRQD_MANAGED_SHUTDOWN
= (1 << 23),
232 IRQD_SINGLE_TARGET
= (1 << 24),
235 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
237 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
239 return __irqd_to_state(d
) & IRQD_SETAFFINITY_PENDING
;
242 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
244 return __irqd_to_state(d
) & IRQD_PER_CPU
;
247 static inline bool irqd_can_balance(struct irq_data
*d
)
249 return !(__irqd_to_state(d
) & (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
252 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
254 return __irqd_to_state(d
) & IRQD_AFFINITY_SET
;
257 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
259 __irqd_to_state(d
) |= IRQD_AFFINITY_SET
;
262 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
264 return __irqd_to_state(d
) & IRQD_TRIGGER_MASK
;
268 * Must only be called inside irq_chip.irq_set_type() functions.
270 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
272 __irqd_to_state(d
) &= ~IRQD_TRIGGER_MASK
;
273 __irqd_to_state(d
) |= type
& IRQD_TRIGGER_MASK
;
276 static inline bool irqd_is_level_type(struct irq_data
*d
)
278 return __irqd_to_state(d
) & IRQD_LEVEL
;
282 * Must only be called of irqchip.irq_set_affinity() or low level
283 * hieararchy domain allocation functions.
285 static inline void irqd_set_single_target(struct irq_data
*d
)
287 __irqd_to_state(d
) |= IRQD_SINGLE_TARGET
;
290 static inline bool irqd_is_single_target(struct irq_data
*d
)
292 return __irqd_to_state(d
) & IRQD_SINGLE_TARGET
;
295 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
297 return __irqd_to_state(d
) & IRQD_WAKEUP_STATE
;
300 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
302 return __irqd_to_state(d
) & IRQD_MOVE_PCNTXT
;
305 static inline bool irqd_irq_disabled(struct irq_data
*d
)
307 return __irqd_to_state(d
) & IRQD_IRQ_DISABLED
;
310 static inline bool irqd_irq_masked(struct irq_data
*d
)
312 return __irqd_to_state(d
) & IRQD_IRQ_MASKED
;
315 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
317 return __irqd_to_state(d
) & IRQD_IRQ_INPROGRESS
;
320 static inline bool irqd_is_wakeup_armed(struct irq_data
*d
)
322 return __irqd_to_state(d
) & IRQD_WAKEUP_ARMED
;
325 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data
*d
)
327 return __irqd_to_state(d
) & IRQD_FORWARDED_TO_VCPU
;
330 static inline void irqd_set_forwarded_to_vcpu(struct irq_data
*d
)
332 __irqd_to_state(d
) |= IRQD_FORWARDED_TO_VCPU
;
335 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data
*d
)
337 __irqd_to_state(d
) &= ~IRQD_FORWARDED_TO_VCPU
;
340 static inline bool irqd_affinity_is_managed(struct irq_data
*d
)
342 return __irqd_to_state(d
) & IRQD_AFFINITY_MANAGED
;
345 static inline bool irqd_is_activated(struct irq_data
*d
)
347 return __irqd_to_state(d
) & IRQD_ACTIVATED
;
350 static inline void irqd_set_activated(struct irq_data
*d
)
352 __irqd_to_state(d
) |= IRQD_ACTIVATED
;
355 static inline void irqd_clr_activated(struct irq_data
*d
)
357 __irqd_to_state(d
) &= ~IRQD_ACTIVATED
;
360 static inline bool irqd_is_started(struct irq_data
*d
)
362 return __irqd_to_state(d
) & IRQD_IRQ_STARTED
;
365 static inline bool irqd_is_managed_and_shutdown(struct irq_data
*d
)
367 return __irqd_to_state(d
) & IRQD_MANAGED_SHUTDOWN
;
370 #undef __irqd_to_state
372 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
378 * struct irq_chip - hardware interrupt chip descriptor
380 * @parent_device: pointer to parent device for irqchip
381 * @name: name for /proc/interrupts
382 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
383 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
384 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
385 * @irq_disable: disable the interrupt
386 * @irq_ack: start of a new interrupt
387 * @irq_mask: mask an interrupt source
388 * @irq_mask_ack: ack and mask an interrupt source
389 * @irq_unmask: unmask an interrupt source
390 * @irq_eoi: end of interrupt
391 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
392 * argument is true, it tells the driver to
393 * unconditionally apply the affinity setting. Sanity
394 * checks against the supplied affinity mask are not
395 * required. This is used for CPU hotplug where the
396 * target CPU is not yet set in the cpu_online_mask.
397 * @irq_retrigger: resend an IRQ to the CPU
398 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
399 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
400 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
401 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
402 * @irq_cpu_online: configure an interrupt source for a secondary CPU
403 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
404 * @irq_suspend: function called from core code on suspend once per
405 * chip, when one or more interrupts are installed
406 * @irq_resume: function called from core code on resume once per chip,
407 * when one ore more interrupts are installed
408 * @irq_pm_shutdown: function called from core code on shutdown once per chip
409 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
410 * @irq_print_chip: optional to print special chip info in show_interrupts
411 * @irq_request_resources: optional to request resources before calling
412 * any other callback related to this irq
413 * @irq_release_resources: optional to release resources acquired with
414 * irq_request_resources
415 * @irq_compose_msi_msg: optional to compose message content for MSI
416 * @irq_write_msi_msg: optional to write message content for MSI
417 * @irq_get_irqchip_state: return the internal state of an interrupt
418 * @irq_set_irqchip_state: set the internal state of a interrupt
419 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
420 * @ipi_send_single: send a single IPI to destination cpus
421 * @ipi_send_mask: send an IPI to destination cpus in cpumask
422 * @flags: chip specific flags
425 struct device
*parent_device
;
427 unsigned int (*irq_startup
)(struct irq_data
*data
);
428 void (*irq_shutdown
)(struct irq_data
*data
);
429 void (*irq_enable
)(struct irq_data
*data
);
430 void (*irq_disable
)(struct irq_data
*data
);
432 void (*irq_ack
)(struct irq_data
*data
);
433 void (*irq_mask
)(struct irq_data
*data
);
434 void (*irq_mask_ack
)(struct irq_data
*data
);
435 void (*irq_unmask
)(struct irq_data
*data
);
436 void (*irq_eoi
)(struct irq_data
*data
);
438 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
439 int (*irq_retrigger
)(struct irq_data
*data
);
440 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
441 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
443 void (*irq_bus_lock
)(struct irq_data
*data
);
444 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
446 void (*irq_cpu_online
)(struct irq_data
*data
);
447 void (*irq_cpu_offline
)(struct irq_data
*data
);
449 void (*irq_suspend
)(struct irq_data
*data
);
450 void (*irq_resume
)(struct irq_data
*data
);
451 void (*irq_pm_shutdown
)(struct irq_data
*data
);
453 void (*irq_calc_mask
)(struct irq_data
*data
);
455 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
456 int (*irq_request_resources
)(struct irq_data
*data
);
457 void (*irq_release_resources
)(struct irq_data
*data
);
459 void (*irq_compose_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
460 void (*irq_write_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
462 int (*irq_get_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool *state
);
463 int (*irq_set_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool state
);
465 int (*irq_set_vcpu_affinity
)(struct irq_data
*data
, void *vcpu_info
);
467 void (*ipi_send_single
)(struct irq_data
*data
, unsigned int cpu
);
468 void (*ipi_send_mask
)(struct irq_data
*data
, const struct cpumask
*dest
);
474 * irq_chip specific flags
476 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
477 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
478 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
479 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
481 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
482 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
483 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
486 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
487 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
488 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
489 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
490 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
491 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
492 IRQCHIP_EOI_THREADED
= (1 << 6),
495 #include <linux/irqdesc.h>
498 * Pick up the arch-dependent methods:
500 #include <asm/hw_irq.h>
502 #ifndef NR_IRQS_LEGACY
503 # define NR_IRQS_LEGACY 0
506 #ifndef ARCH_IRQ_INIT_FLAGS
507 # define ARCH_IRQ_INIT_FLAGS 0
510 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
513 extern int setup_irq(unsigned int irq
, struct irqaction
*new);
514 extern void remove_irq(unsigned int irq
, struct irqaction
*act
);
515 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
516 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
518 extern void irq_cpu_online(void);
519 extern void irq_cpu_offline(void);
520 extern int irq_set_affinity_locked(struct irq_data
*data
,
521 const struct cpumask
*cpumask
, bool force
);
522 extern int irq_set_vcpu_affinity(unsigned int irq
, void *vcpu_info
);
524 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
525 extern void irq_migrate_all_off_this_cpu(void);
526 extern int irq_affinity_online_cpu(unsigned int cpu
);
528 # define irq_affinity_online_cpu NULL
531 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
532 void irq_move_irq(struct irq_data
*data
);
533 void irq_move_masked_irq(struct irq_data
*data
);
534 void irq_force_complete_move(struct irq_desc
*desc
);
536 static inline void irq_move_irq(struct irq_data
*data
) { }
537 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
538 static inline void irq_force_complete_move(struct irq_desc
*desc
) { }
541 extern int no_irq_affinity
;
543 #ifdef CONFIG_HARDIRQS_SW_RESEND
544 int irq_set_parent(int irq
, int parent_irq
);
546 static inline int irq_set_parent(int irq
, int parent_irq
)
553 * Built-in IRQ handlers for various IRQ types,
554 * callable via desc->handle_irq()
556 extern void handle_level_irq(struct irq_desc
*desc
);
557 extern void handle_fasteoi_irq(struct irq_desc
*desc
);
558 extern void handle_edge_irq(struct irq_desc
*desc
);
559 extern void handle_edge_eoi_irq(struct irq_desc
*desc
);
560 extern void handle_simple_irq(struct irq_desc
*desc
);
561 extern void handle_untracked_irq(struct irq_desc
*desc
);
562 extern void handle_percpu_irq(struct irq_desc
*desc
);
563 extern void handle_percpu_devid_irq(struct irq_desc
*desc
);
564 extern void handle_bad_irq(struct irq_desc
*desc
);
565 extern void handle_nested_irq(unsigned int irq
);
567 extern int irq_chip_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
);
568 extern int irq_chip_pm_get(struct irq_data
*data
);
569 extern int irq_chip_pm_put(struct irq_data
*data
);
570 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
571 extern void handle_fasteoi_ack_irq(struct irq_desc
*desc
);
572 extern void handle_fasteoi_mask_irq(struct irq_desc
*desc
);
573 extern void irq_chip_enable_parent(struct irq_data
*data
);
574 extern void irq_chip_disable_parent(struct irq_data
*data
);
575 extern void irq_chip_ack_parent(struct irq_data
*data
);
576 extern int irq_chip_retrigger_hierarchy(struct irq_data
*data
);
577 extern void irq_chip_mask_parent(struct irq_data
*data
);
578 extern void irq_chip_unmask_parent(struct irq_data
*data
);
579 extern void irq_chip_eoi_parent(struct irq_data
*data
);
580 extern int irq_chip_set_affinity_parent(struct irq_data
*data
,
581 const struct cpumask
*dest
,
583 extern int irq_chip_set_wake_parent(struct irq_data
*data
, unsigned int on
);
584 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data
,
586 extern int irq_chip_set_type_parent(struct irq_data
*data
, unsigned int type
);
589 /* Handling of unhandled and spurious interrupts: */
590 extern void note_interrupt(struct irq_desc
*desc
, irqreturn_t action_ret
);
593 /* Enable/disable irq debugging output: */
594 extern int noirqdebug_setup(char *str
);
596 /* Checks whether the interrupt can be requested by request_irq(): */
597 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
599 /* Dummy irq-chip implementations: */
600 extern struct irq_chip no_irq_chip
;
601 extern struct irq_chip dummy_irq_chip
;
604 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
605 irq_flow_handler_t handle
, const char *name
);
607 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
608 irq_flow_handler_t handle
)
610 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
613 extern int irq_set_percpu_devid(unsigned int irq
);
614 extern int irq_set_percpu_devid_partition(unsigned int irq
,
615 const struct cpumask
*affinity
);
616 extern int irq_get_percpu_devid_partition(unsigned int irq
,
617 struct cpumask
*affinity
);
620 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
624 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
626 __irq_set_handler(irq
, handle
, 0, NULL
);
630 * Set a highlevel chained flow handler for a given IRQ.
631 * (a chained handler is automatically enabled and set to
632 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
635 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
637 __irq_set_handler(irq
, handle
, 1, NULL
);
641 * Set a highlevel chained flow handler and its data for a given IRQ.
642 * (a chained handler is automatically enabled and set to
643 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
646 irq_set_chained_handler_and_data(unsigned int irq
, irq_flow_handler_t handle
,
649 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
651 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
653 irq_modify_status(irq
, 0, set
);
656 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
658 irq_modify_status(irq
, clr
, 0);
661 static inline void irq_set_noprobe(unsigned int irq
)
663 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
666 static inline void irq_set_probe(unsigned int irq
)
668 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
671 static inline void irq_set_nothread(unsigned int irq
)
673 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
676 static inline void irq_set_thread(unsigned int irq
)
678 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
681 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
684 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
686 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
689 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
691 irq_set_status_flags(irq
,
692 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
693 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
696 /* Set/get chip/data for an IRQ: */
697 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
698 extern int irq_set_handler_data(unsigned int irq
, void *data
);
699 extern int irq_set_chip_data(unsigned int irq
, void *data
);
700 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
701 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
702 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
703 struct msi_desc
*entry
);
704 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
706 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
708 struct irq_data
*d
= irq_get_irq_data(irq
);
709 return d
? d
->chip
: NULL
;
712 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
717 static inline void *irq_get_chip_data(unsigned int irq
)
719 struct irq_data
*d
= irq_get_irq_data(irq
);
720 return d
? d
->chip_data
: NULL
;
723 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
728 static inline void *irq_get_handler_data(unsigned int irq
)
730 struct irq_data
*d
= irq_get_irq_data(irq
);
731 return d
? d
->common
->handler_data
: NULL
;
734 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
736 return d
->common
->handler_data
;
739 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
741 struct irq_data
*d
= irq_get_irq_data(irq
);
742 return d
? d
->common
->msi_desc
: NULL
;
745 static inline struct msi_desc
*irq_data_get_msi_desc(struct irq_data
*d
)
747 return d
->common
->msi_desc
;
750 static inline u32
irq_get_trigger_type(unsigned int irq
)
752 struct irq_data
*d
= irq_get_irq_data(irq
);
753 return d
? irqd_get_trigger_type(d
) : 0;
756 static inline int irq_common_data_get_node(struct irq_common_data
*d
)
765 static inline int irq_data_get_node(struct irq_data
*d
)
767 return irq_common_data_get_node(d
->common
);
770 static inline struct cpumask
*irq_get_affinity_mask(int irq
)
772 struct irq_data
*d
= irq_get_irq_data(irq
);
774 return d
? d
->common
->affinity
: NULL
;
777 static inline struct cpumask
*irq_data_get_affinity_mask(struct irq_data
*d
)
779 return d
->common
->affinity
;
782 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
784 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
786 if (!cpumask_empty(d
->common
->effective_affinity
))
787 return d
->common
->effective_affinity
;
789 return d
->common
->affinity
;
791 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
792 const struct cpumask
*m
)
794 cpumask_copy(d
->common
->effective_affinity
, m
);
797 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
798 const struct cpumask
*m
)
802 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
804 return d
->common
->affinity
;
808 unsigned int arch_dynirq_lower_bound(unsigned int from
);
810 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
811 struct module
*owner
, const struct cpumask
*affinity
);
813 int __devm_irq_alloc_descs(struct device
*dev
, int irq
, unsigned int from
,
814 unsigned int cnt
, int node
, struct module
*owner
,
815 const struct cpumask
*affinity
);
817 /* use macros to avoid needing export.h for THIS_MODULE */
818 #define irq_alloc_descs(irq, from, cnt, node) \
819 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
821 #define irq_alloc_desc(node) \
822 irq_alloc_descs(-1, 0, 1, node)
824 #define irq_alloc_desc_at(at, node) \
825 irq_alloc_descs(at, at, 1, node)
827 #define irq_alloc_desc_from(from, node) \
828 irq_alloc_descs(-1, from, 1, node)
830 #define irq_alloc_descs_from(from, cnt, node) \
831 irq_alloc_descs(-1, from, cnt, node)
833 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
834 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
836 #define devm_irq_alloc_desc(dev, node) \
837 devm_irq_alloc_descs(dev, -1, 0, 1, node)
839 #define devm_irq_alloc_desc_at(dev, at, node) \
840 devm_irq_alloc_descs(dev, at, at, 1, node)
842 #define devm_irq_alloc_desc_from(dev, from, node) \
843 devm_irq_alloc_descs(dev, -1, from, 1, node)
845 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
846 devm_irq_alloc_descs(dev, -1, from, cnt, node)
848 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
849 static inline void irq_free_desc(unsigned int irq
)
851 irq_free_descs(irq
, 1);
854 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
855 unsigned int irq_alloc_hwirqs(int cnt
, int node
);
856 static inline unsigned int irq_alloc_hwirq(int node
)
858 return irq_alloc_hwirqs(1, node
);
860 void irq_free_hwirqs(unsigned int from
, int cnt
);
861 static inline void irq_free_hwirq(unsigned int irq
)
863 return irq_free_hwirqs(irq
, 1);
865 int arch_setup_hwirq(unsigned int irq
, int node
);
866 void arch_teardown_hwirq(unsigned int irq
);
869 #ifdef CONFIG_GENERIC_IRQ_LEGACY
870 void irq_init_desc(unsigned int irq
);
874 * struct irq_chip_regs - register offsets for struct irq_gci
875 * @enable: Enable register offset to reg_base
876 * @disable: Disable register offset to reg_base
877 * @mask: Mask register offset to reg_base
878 * @ack: Ack register offset to reg_base
879 * @eoi: Eoi register offset to reg_base
880 * @type: Type configuration register offset to reg_base
881 * @polarity: Polarity configuration register offset to reg_base
883 struct irq_chip_regs
{
884 unsigned long enable
;
885 unsigned long disable
;
890 unsigned long polarity
;
894 * struct irq_chip_type - Generic interrupt chip instance for a flow type
895 * @chip: The real interrupt chip which provides the callbacks
896 * @regs: Register offsets for this chip
897 * @handler: Flow handler associated with this chip
898 * @type: Chip can handle these flow types
899 * @mask_cache_priv: Cached mask register private to the chip type
900 * @mask_cache: Pointer to cached mask register
902 * A irq_generic_chip can have several instances of irq_chip_type when
903 * it requires different functions and register offsets for different
906 struct irq_chip_type
{
907 struct irq_chip chip
;
908 struct irq_chip_regs regs
;
909 irq_flow_handler_t handler
;
916 * struct irq_chip_generic - Generic irq chip data structure
917 * @lock: Lock to protect register and cache data access
918 * @reg_base: Register base address (virtual)
919 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
920 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
921 * @suspend: Function called from core code on suspend once per
922 * chip; can be useful instead of irq_chip::suspend to
923 * handle chip details even when no interrupts are in use
924 * @resume: Function called from core code on resume once per chip;
925 * can be useful instead of irq_chip::suspend to handle
926 * chip details even when no interrupts are in use
927 * @irq_base: Interrupt base nr for this chip
928 * @irq_cnt: Number of interrupts handled by this chip
929 * @mask_cache: Cached mask register shared between all chip types
930 * @type_cache: Cached type register
931 * @polarity_cache: Cached polarity register
932 * @wake_enabled: Interrupt can wakeup from suspend
933 * @wake_active: Interrupt is marked as an wakeup from suspend source
934 * @num_ct: Number of available irq_chip_type instances (usually 1)
935 * @private: Private data for non generic chip callbacks
936 * @installed: bitfield to denote installed interrupts
937 * @unused: bitfield to denote unused interrupts
938 * @domain: irq domain pointer
939 * @list: List head for keeping track of instances
940 * @chip_types: Array of interrupt irq_chip_types
942 * Note, that irq_chip_generic can have multiple irq_chip_type
943 * implementations which can be associated to a particular irq line of
944 * an irq_chip_generic instance. That allows to share and protect
945 * state in an irq_chip_generic instance when we need to implement
946 * different flow mechanisms (level/edge) for it.
948 struct irq_chip_generic
{
950 void __iomem
*reg_base
;
951 u32 (*reg_readl
)(void __iomem
*addr
);
952 void (*reg_writel
)(u32 val
, void __iomem
*addr
);
953 void (*suspend
)(struct irq_chip_generic
*gc
);
954 void (*resume
)(struct irq_chip_generic
*gc
);
955 unsigned int irq_base
;
956 unsigned int irq_cnt
;
964 unsigned long installed
;
965 unsigned long unused
;
966 struct irq_domain
*domain
;
967 struct list_head list
;
968 struct irq_chip_type chip_types
[0];
972 * enum irq_gc_flags - Initialization flags for generic irq chips
973 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
974 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
975 * irq chips which need to call irq_set_wake() on
976 * the parent irq. Usually GPIO implementations
977 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
978 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
979 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
982 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
983 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
984 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
985 IRQ_GC_NO_MASK
= 1 << 3,
986 IRQ_GC_BE_IO
= 1 << 4,
990 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
991 * @irqs_per_chip: Number of interrupts per chip
992 * @num_chips: Number of chips
993 * @irq_flags_to_set: IRQ* flags to set on irq setup
994 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
995 * @gc_flags: Generic chip specific setup flags
996 * @gc: Array of pointers to generic interrupt chips
998 struct irq_domain_chip_generic
{
999 unsigned int irqs_per_chip
;
1000 unsigned int num_chips
;
1001 unsigned int irq_flags_to_clear
;
1002 unsigned int irq_flags_to_set
;
1003 enum irq_gc_flags gc_flags
;
1004 struct irq_chip_generic
*gc
[0];
1007 /* Generic chip callback functions */
1008 void irq_gc_noop(struct irq_data
*d
);
1009 void irq_gc_mask_disable_reg(struct irq_data
*d
);
1010 void irq_gc_mask_set_bit(struct irq_data
*d
);
1011 void irq_gc_mask_clr_bit(struct irq_data
*d
);
1012 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
1013 void irq_gc_ack_set_bit(struct irq_data
*d
);
1014 void irq_gc_ack_clr_bit(struct irq_data
*d
);
1015 void irq_gc_mask_disable_reg_and_ack(struct irq_data
*d
);
1016 void irq_gc_eoi(struct irq_data
*d
);
1017 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
1019 /* Setup functions for irq_chip_generic */
1020 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
1021 irq_hw_number_t hw_irq
);
1022 struct irq_chip_generic
*
1023 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
1024 void __iomem
*reg_base
, irq_flow_handler_t handler
);
1025 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1026 enum irq_gc_flags flags
, unsigned int clr
,
1028 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
1029 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1030 unsigned int clr
, unsigned int set
);
1032 struct irq_chip_generic
*
1033 devm_irq_alloc_generic_chip(struct device
*dev
, const char *name
, int num_ct
,
1034 unsigned int irq_base
, void __iomem
*reg_base
,
1035 irq_flow_handler_t handler
);
1036 int devm_irq_setup_generic_chip(struct device
*dev
, struct irq_chip_generic
*gc
,
1037 u32 msk
, enum irq_gc_flags flags
,
1038 unsigned int clr
, unsigned int set
);
1040 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
1042 int __irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
1043 int num_ct
, const char *name
,
1044 irq_flow_handler_t handler
,
1045 unsigned int clr
, unsigned int set
,
1046 enum irq_gc_flags flags
);
1048 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1049 handler, clr, set, flags) \
1051 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1052 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1053 handler, clr, set, flags); \
1056 static inline void irq_free_generic_chip(struct irq_chip_generic
*gc
)
1061 static inline void irq_destroy_generic_chip(struct irq_chip_generic
*gc
,
1062 u32 msk
, unsigned int clr
,
1065 irq_remove_generic_chip(gc
, msk
, clr
, set
);
1066 irq_free_generic_chip(gc
);
1069 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
1071 return container_of(d
->chip
, struct irq_chip_type
, chip
);
1074 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1077 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
1079 raw_spin_lock(&gc
->lock
);
1082 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
1084 raw_spin_unlock(&gc
->lock
);
1087 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
1088 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
1092 * The irqsave variants are for usage in non interrupt code. Do not use
1093 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1095 #define irq_gc_lock_irqsave(gc, flags) \
1096 raw_spin_lock_irqsave(&(gc)->lock, flags)
1098 #define irq_gc_unlock_irqrestore(gc, flags) \
1099 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1101 static inline void irq_reg_writel(struct irq_chip_generic
*gc
,
1102 u32 val
, int reg_offset
)
1105 gc
->reg_writel(val
, gc
->reg_base
+ reg_offset
);
1107 writel(val
, gc
->reg_base
+ reg_offset
);
1110 static inline u32
irq_reg_readl(struct irq_chip_generic
*gc
,
1114 return gc
->reg_readl(gc
->reg_base
+ reg_offset
);
1116 return readl(gc
->reg_base
+ reg_offset
);
1119 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1120 #define INVALID_HWIRQ (~0UL)
1121 irq_hw_number_t
ipi_get_hwirq(unsigned int irq
, unsigned int cpu
);
1122 int __ipi_send_single(struct irq_desc
*desc
, unsigned int cpu
);
1123 int __ipi_send_mask(struct irq_desc
*desc
, const struct cpumask
*dest
);
1124 int ipi_send_single(unsigned int virq
, unsigned int cpu
);
1125 int ipi_send_mask(unsigned int virq
, const struct cpumask
*dest
);
1127 #endif /* _LINUX_IRQ_H */