1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
13 #include <linux/smp.h>
14 #include <linux/linkage.h>
15 #include <linux/cache.h>
16 #include <linux/spinlock.h>
17 #include <linux/cpumask.h>
18 #include <linux/gfp.h>
19 #include <linux/irqhandler.h>
20 #include <linux/irqreturn.h>
21 #include <linux/irqnr.h>
22 #include <linux/errno.h>
23 #include <linux/topology.h>
24 #include <linux/wait.h>
26 #include <linux/slab.h>
29 #include <asm/ptrace.h>
30 #include <asm/irq_regs.h>
35 enum irqchip_irq_state
;
40 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
42 * IRQ_TYPE_NONE - default, unspecified type
43 * IRQ_TYPE_EDGE_RISING - rising edge triggered
44 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
45 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
46 * IRQ_TYPE_LEVEL_HIGH - high level triggered
47 * IRQ_TYPE_LEVEL_LOW - low level triggered
48 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
49 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
50 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
51 * to setup the HW to a sane default (used
52 * by irqdomain map() callbacks to synchronize
53 * the HW state and SW flags for a newly
54 * allocated descriptor).
56 * IRQ_TYPE_PROBE - Special flag for probing in progress
58 * Bits which can be modified via irq_set/clear/modify_status_flags()
59 * IRQ_LEVEL - Interrupt is level type. Will be also
60 * updated in the code when the above trigger
61 * bits are modified via irq_set_irq_type()
62 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
63 * it from affinity setting
64 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
65 * IRQ_NOREQUEST - Interrupt cannot be requested via
67 * IRQ_NOTHREAD - Interrupt cannot be threaded
68 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
70 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
71 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
72 * IRQ_NESTED_THREAD - Interrupt nests into another thread
73 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
74 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
75 * it from the spurious interrupt detection
76 * mechanism and from core side polling.
77 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
80 IRQ_TYPE_NONE
= 0x00000000,
81 IRQ_TYPE_EDGE_RISING
= 0x00000001,
82 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
83 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
84 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
85 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
86 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
87 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
88 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
90 IRQ_TYPE_PROBE
= 0x00000010,
93 IRQ_PER_CPU
= (1 << 9),
94 IRQ_NOPROBE
= (1 << 10),
95 IRQ_NOREQUEST
= (1 << 11),
96 IRQ_NOAUTOEN
= (1 << 12),
97 IRQ_NO_BALANCING
= (1 << 13),
98 IRQ_MOVE_PCNTXT
= (1 << 14),
99 IRQ_NESTED_THREAD
= (1 << 15),
100 IRQ_NOTHREAD
= (1 << 16),
101 IRQ_PER_CPU_DEVID
= (1 << 17),
102 IRQ_IS_POLLED
= (1 << 18),
103 IRQ_DISABLE_UNLAZY
= (1 << 19),
106 #define IRQF_MODIFY_MASK \
107 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
112 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
115 * Return value for chip->irq_set_affinity()
117 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
118 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
119 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
120 * support stacked irqchips, which indicates skipping
121 * all descendent irqchips.
125 IRQ_SET_MASK_OK_NOCOPY
,
126 IRQ_SET_MASK_OK_DONE
,
133 * struct irq_common_data - per irq data shared by all irqchips
134 * @state_use_accessors: status information for irq chip functions.
135 * Use accessor functions to deal with it
136 * @node: node index useful for balancing
137 * @handler_data: per-IRQ data for the irq_chip methods
138 * @affinity: IRQ affinity on SMP. If this is an IPI
139 * related irq, then this is the mask of the
140 * CPUs to which an IPI can be sent.
141 * @effective_affinity: The effective IRQ affinity on SMP as some irq
142 * chips do not allow multi CPU destinations.
143 * A subset of @affinity.
144 * @msi_desc: MSI descriptor
145 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
147 struct irq_common_data
{
148 unsigned int __private state_use_accessors
;
153 struct msi_desc
*msi_desc
;
154 cpumask_var_t affinity
;
155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
156 cpumask_var_t effective_affinity
;
158 #ifdef CONFIG_GENERIC_IRQ_IPI
159 unsigned int ipi_offset
;
164 * struct irq_data - per irq chip data passed down to chip functions
165 * @mask: precomputed bitmask for accessing the chip registers
166 * @irq: interrupt number
167 * @hwirq: hardware interrupt number, local to the interrupt domain
168 * @common: point to data shared by all irqchips
169 * @chip: low level interrupt hardware access
170 * @domain: Interrupt translation domain; responsible for mapping
171 * between hwirq number and linux irq number.
172 * @parent_data: pointer to parent struct irq_data to support hierarchy
174 * @chip_data: platform-specific per-chip private data for the chip
175 * methods, to allow shared chip implementations
181 struct irq_common_data
*common
;
182 struct irq_chip
*chip
;
183 struct irq_domain
*domain
;
184 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
185 struct irq_data
*parent_data
;
191 * Bit masks for irq_common_data.state_use_accessors
193 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
194 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
195 * IRQD_ACTIVATED - Interrupt has already been activated
196 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
197 * IRQD_PER_CPU - Interrupt is per cpu
198 * IRQD_AFFINITY_SET - Interrupt affinity was set
199 * IRQD_LEVEL - Interrupt is level triggered
200 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
202 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
204 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
205 * IRQD_IRQ_MASKED - Masked state of the interrupt
206 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
207 * IRQD_WAKEUP_ARMED - Wakeup mode armed
208 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
209 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
210 * IRQD_IRQ_STARTED - Startup state of the interrupt
211 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
212 * mask. Applies only to affinity managed irqs.
213 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
214 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
217 IRQD_TRIGGER_MASK
= 0xf,
218 IRQD_SETAFFINITY_PENDING
= (1 << 8),
219 IRQD_ACTIVATED
= (1 << 9),
220 IRQD_NO_BALANCING
= (1 << 10),
221 IRQD_PER_CPU
= (1 << 11),
222 IRQD_AFFINITY_SET
= (1 << 12),
223 IRQD_LEVEL
= (1 << 13),
224 IRQD_WAKEUP_STATE
= (1 << 14),
225 IRQD_MOVE_PCNTXT
= (1 << 15),
226 IRQD_IRQ_DISABLED
= (1 << 16),
227 IRQD_IRQ_MASKED
= (1 << 17),
228 IRQD_IRQ_INPROGRESS
= (1 << 18),
229 IRQD_WAKEUP_ARMED
= (1 << 19),
230 IRQD_FORWARDED_TO_VCPU
= (1 << 20),
231 IRQD_AFFINITY_MANAGED
= (1 << 21),
232 IRQD_IRQ_STARTED
= (1 << 22),
233 IRQD_MANAGED_SHUTDOWN
= (1 << 23),
234 IRQD_SINGLE_TARGET
= (1 << 24),
235 IRQD_DEFAULT_TRIGGER_SET
= (1 << 25),
238 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
240 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
242 return __irqd_to_state(d
) & IRQD_SETAFFINITY_PENDING
;
245 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
247 return __irqd_to_state(d
) & IRQD_PER_CPU
;
250 static inline bool irqd_can_balance(struct irq_data
*d
)
252 return !(__irqd_to_state(d
) & (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
255 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
257 return __irqd_to_state(d
) & IRQD_AFFINITY_SET
;
260 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
262 __irqd_to_state(d
) |= IRQD_AFFINITY_SET
;
265 static inline bool irqd_trigger_type_was_set(struct irq_data
*d
)
267 return __irqd_to_state(d
) & IRQD_DEFAULT_TRIGGER_SET
;
270 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
272 return __irqd_to_state(d
) & IRQD_TRIGGER_MASK
;
276 * Must only be called inside irq_chip.irq_set_type() functions or
277 * from the DT/ACPI setup code.
279 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
281 __irqd_to_state(d
) &= ~IRQD_TRIGGER_MASK
;
282 __irqd_to_state(d
) |= type
& IRQD_TRIGGER_MASK
;
283 __irqd_to_state(d
) |= IRQD_DEFAULT_TRIGGER_SET
;
286 static inline bool irqd_is_level_type(struct irq_data
*d
)
288 return __irqd_to_state(d
) & IRQD_LEVEL
;
292 * Must only be called of irqchip.irq_set_affinity() or low level
293 * hieararchy domain allocation functions.
295 static inline void irqd_set_single_target(struct irq_data
*d
)
297 __irqd_to_state(d
) |= IRQD_SINGLE_TARGET
;
300 static inline bool irqd_is_single_target(struct irq_data
*d
)
302 return __irqd_to_state(d
) & IRQD_SINGLE_TARGET
;
305 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
307 return __irqd_to_state(d
) & IRQD_WAKEUP_STATE
;
310 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
312 return __irqd_to_state(d
) & IRQD_MOVE_PCNTXT
;
315 static inline bool irqd_irq_disabled(struct irq_data
*d
)
317 return __irqd_to_state(d
) & IRQD_IRQ_DISABLED
;
320 static inline bool irqd_irq_masked(struct irq_data
*d
)
322 return __irqd_to_state(d
) & IRQD_IRQ_MASKED
;
325 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
327 return __irqd_to_state(d
) & IRQD_IRQ_INPROGRESS
;
330 static inline bool irqd_is_wakeup_armed(struct irq_data
*d
)
332 return __irqd_to_state(d
) & IRQD_WAKEUP_ARMED
;
335 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data
*d
)
337 return __irqd_to_state(d
) & IRQD_FORWARDED_TO_VCPU
;
340 static inline void irqd_set_forwarded_to_vcpu(struct irq_data
*d
)
342 __irqd_to_state(d
) |= IRQD_FORWARDED_TO_VCPU
;
345 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data
*d
)
347 __irqd_to_state(d
) &= ~IRQD_FORWARDED_TO_VCPU
;
350 static inline bool irqd_affinity_is_managed(struct irq_data
*d
)
352 return __irqd_to_state(d
) & IRQD_AFFINITY_MANAGED
;
355 static inline bool irqd_is_activated(struct irq_data
*d
)
357 return __irqd_to_state(d
) & IRQD_ACTIVATED
;
360 static inline void irqd_set_activated(struct irq_data
*d
)
362 __irqd_to_state(d
) |= IRQD_ACTIVATED
;
365 static inline void irqd_clr_activated(struct irq_data
*d
)
367 __irqd_to_state(d
) &= ~IRQD_ACTIVATED
;
370 static inline bool irqd_is_started(struct irq_data
*d
)
372 return __irqd_to_state(d
) & IRQD_IRQ_STARTED
;
375 static inline bool irqd_is_managed_and_shutdown(struct irq_data
*d
)
377 return __irqd_to_state(d
) & IRQD_MANAGED_SHUTDOWN
;
380 #undef __irqd_to_state
382 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
388 * struct irq_chip - hardware interrupt chip descriptor
390 * @parent_device: pointer to parent device for irqchip
391 * @name: name for /proc/interrupts
392 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
393 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
394 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
395 * @irq_disable: disable the interrupt
396 * @irq_ack: start of a new interrupt
397 * @irq_mask: mask an interrupt source
398 * @irq_mask_ack: ack and mask an interrupt source
399 * @irq_unmask: unmask an interrupt source
400 * @irq_eoi: end of interrupt
401 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
402 * argument is true, it tells the driver to
403 * unconditionally apply the affinity setting. Sanity
404 * checks against the supplied affinity mask are not
405 * required. This is used for CPU hotplug where the
406 * target CPU is not yet set in the cpu_online_mask.
407 * @irq_retrigger: resend an IRQ to the CPU
408 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
409 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
410 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
411 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
412 * @irq_cpu_online: configure an interrupt source for a secondary CPU
413 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
414 * @irq_suspend: function called from core code on suspend once per
415 * chip, when one or more interrupts are installed
416 * @irq_resume: function called from core code on resume once per chip,
417 * when one ore more interrupts are installed
418 * @irq_pm_shutdown: function called from core code on shutdown once per chip
419 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
420 * @irq_print_chip: optional to print special chip info in show_interrupts
421 * @irq_request_resources: optional to request resources before calling
422 * any other callback related to this irq
423 * @irq_release_resources: optional to release resources acquired with
424 * irq_request_resources
425 * @irq_compose_msi_msg: optional to compose message content for MSI
426 * @irq_write_msi_msg: optional to write message content for MSI
427 * @irq_get_irqchip_state: return the internal state of an interrupt
428 * @irq_set_irqchip_state: set the internal state of a interrupt
429 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
430 * @ipi_send_single: send a single IPI to destination cpus
431 * @ipi_send_mask: send an IPI to destination cpus in cpumask
432 * @flags: chip specific flags
435 struct device
*parent_device
;
437 unsigned int (*irq_startup
)(struct irq_data
*data
);
438 void (*irq_shutdown
)(struct irq_data
*data
);
439 void (*irq_enable
)(struct irq_data
*data
);
440 void (*irq_disable
)(struct irq_data
*data
);
442 void (*irq_ack
)(struct irq_data
*data
);
443 void (*irq_mask
)(struct irq_data
*data
);
444 void (*irq_mask_ack
)(struct irq_data
*data
);
445 void (*irq_unmask
)(struct irq_data
*data
);
446 void (*irq_eoi
)(struct irq_data
*data
);
448 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
449 int (*irq_retrigger
)(struct irq_data
*data
);
450 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
451 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
453 void (*irq_bus_lock
)(struct irq_data
*data
);
454 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
456 void (*irq_cpu_online
)(struct irq_data
*data
);
457 void (*irq_cpu_offline
)(struct irq_data
*data
);
459 void (*irq_suspend
)(struct irq_data
*data
);
460 void (*irq_resume
)(struct irq_data
*data
);
461 void (*irq_pm_shutdown
)(struct irq_data
*data
);
463 void (*irq_calc_mask
)(struct irq_data
*data
);
465 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
466 int (*irq_request_resources
)(struct irq_data
*data
);
467 void (*irq_release_resources
)(struct irq_data
*data
);
469 void (*irq_compose_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
470 void (*irq_write_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
472 int (*irq_get_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool *state
);
473 int (*irq_set_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool state
);
475 int (*irq_set_vcpu_affinity
)(struct irq_data
*data
, void *vcpu_info
);
477 void (*ipi_send_single
)(struct irq_data
*data
, unsigned int cpu
);
478 void (*ipi_send_mask
)(struct irq_data
*data
, const struct cpumask
*dest
);
484 * irq_chip specific flags
486 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
487 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
488 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
489 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
491 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
492 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
493 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
496 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
497 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
498 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
499 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
500 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
501 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
502 IRQCHIP_EOI_THREADED
= (1 << 6),
505 #include <linux/irqdesc.h>
508 * Pick up the arch-dependent methods:
510 #include <asm/hw_irq.h>
512 #ifndef NR_IRQS_LEGACY
513 # define NR_IRQS_LEGACY 0
516 #ifndef ARCH_IRQ_INIT_FLAGS
517 # define ARCH_IRQ_INIT_FLAGS 0
520 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
523 extern int setup_irq(unsigned int irq
, struct irqaction
*new);
524 extern void remove_irq(unsigned int irq
, struct irqaction
*act
);
525 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
526 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
528 extern void irq_cpu_online(void);
529 extern void irq_cpu_offline(void);
530 extern int irq_set_affinity_locked(struct irq_data
*data
,
531 const struct cpumask
*cpumask
, bool force
);
532 extern int irq_set_vcpu_affinity(unsigned int irq
, void *vcpu_info
);
534 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
535 extern void irq_migrate_all_off_this_cpu(void);
536 extern int irq_affinity_online_cpu(unsigned int cpu
);
538 # define irq_affinity_online_cpu NULL
541 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
542 void irq_move_irq(struct irq_data
*data
);
543 void irq_move_masked_irq(struct irq_data
*data
);
544 void irq_force_complete_move(struct irq_desc
*desc
);
546 static inline void irq_move_irq(struct irq_data
*data
) { }
547 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
548 static inline void irq_force_complete_move(struct irq_desc
*desc
) { }
551 extern int no_irq_affinity
;
553 #ifdef CONFIG_HARDIRQS_SW_RESEND
554 int irq_set_parent(int irq
, int parent_irq
);
556 static inline int irq_set_parent(int irq
, int parent_irq
)
563 * Built-in IRQ handlers for various IRQ types,
564 * callable via desc->handle_irq()
566 extern void handle_level_irq(struct irq_desc
*desc
);
567 extern void handle_fasteoi_irq(struct irq_desc
*desc
);
568 extern void handle_edge_irq(struct irq_desc
*desc
);
569 extern void handle_edge_eoi_irq(struct irq_desc
*desc
);
570 extern void handle_simple_irq(struct irq_desc
*desc
);
571 extern void handle_untracked_irq(struct irq_desc
*desc
);
572 extern void handle_percpu_irq(struct irq_desc
*desc
);
573 extern void handle_percpu_devid_irq(struct irq_desc
*desc
);
574 extern void handle_bad_irq(struct irq_desc
*desc
);
575 extern void handle_nested_irq(unsigned int irq
);
577 extern int irq_chip_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
);
578 extern int irq_chip_pm_get(struct irq_data
*data
);
579 extern int irq_chip_pm_put(struct irq_data
*data
);
580 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
581 extern void handle_fasteoi_ack_irq(struct irq_desc
*desc
);
582 extern void handle_fasteoi_mask_irq(struct irq_desc
*desc
);
583 extern void irq_chip_enable_parent(struct irq_data
*data
);
584 extern void irq_chip_disable_parent(struct irq_data
*data
);
585 extern void irq_chip_ack_parent(struct irq_data
*data
);
586 extern int irq_chip_retrigger_hierarchy(struct irq_data
*data
);
587 extern void irq_chip_mask_parent(struct irq_data
*data
);
588 extern void irq_chip_unmask_parent(struct irq_data
*data
);
589 extern void irq_chip_eoi_parent(struct irq_data
*data
);
590 extern int irq_chip_set_affinity_parent(struct irq_data
*data
,
591 const struct cpumask
*dest
,
593 extern int irq_chip_set_wake_parent(struct irq_data
*data
, unsigned int on
);
594 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data
,
596 extern int irq_chip_set_type_parent(struct irq_data
*data
, unsigned int type
);
599 /* Handling of unhandled and spurious interrupts: */
600 extern void note_interrupt(struct irq_desc
*desc
, irqreturn_t action_ret
);
603 /* Enable/disable irq debugging output: */
604 extern int noirqdebug_setup(char *str
);
606 /* Checks whether the interrupt can be requested by request_irq(): */
607 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
609 /* Dummy irq-chip implementations: */
610 extern struct irq_chip no_irq_chip
;
611 extern struct irq_chip dummy_irq_chip
;
614 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
615 irq_flow_handler_t handle
, const char *name
);
617 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
618 irq_flow_handler_t handle
)
620 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
623 extern int irq_set_percpu_devid(unsigned int irq
);
624 extern int irq_set_percpu_devid_partition(unsigned int irq
,
625 const struct cpumask
*affinity
);
626 extern int irq_get_percpu_devid_partition(unsigned int irq
,
627 struct cpumask
*affinity
);
630 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
634 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
636 __irq_set_handler(irq
, handle
, 0, NULL
);
640 * Set a highlevel chained flow handler for a given IRQ.
641 * (a chained handler is automatically enabled and set to
642 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
645 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
647 __irq_set_handler(irq
, handle
, 1, NULL
);
651 * Set a highlevel chained flow handler and its data for a given IRQ.
652 * (a chained handler is automatically enabled and set to
653 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
656 irq_set_chained_handler_and_data(unsigned int irq
, irq_flow_handler_t handle
,
659 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
661 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
663 irq_modify_status(irq
, 0, set
);
666 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
668 irq_modify_status(irq
, clr
, 0);
671 static inline void irq_set_noprobe(unsigned int irq
)
673 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
676 static inline void irq_set_probe(unsigned int irq
)
678 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
681 static inline void irq_set_nothread(unsigned int irq
)
683 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
686 static inline void irq_set_thread(unsigned int irq
)
688 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
691 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
694 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
696 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
699 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
701 irq_set_status_flags(irq
,
702 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
703 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
706 /* Set/get chip/data for an IRQ: */
707 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
708 extern int irq_set_handler_data(unsigned int irq
, void *data
);
709 extern int irq_set_chip_data(unsigned int irq
, void *data
);
710 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
711 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
712 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
713 struct msi_desc
*entry
);
714 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
716 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
718 struct irq_data
*d
= irq_get_irq_data(irq
);
719 return d
? d
->chip
: NULL
;
722 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
727 static inline void *irq_get_chip_data(unsigned int irq
)
729 struct irq_data
*d
= irq_get_irq_data(irq
);
730 return d
? d
->chip_data
: NULL
;
733 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
738 static inline void *irq_get_handler_data(unsigned int irq
)
740 struct irq_data
*d
= irq_get_irq_data(irq
);
741 return d
? d
->common
->handler_data
: NULL
;
744 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
746 return d
->common
->handler_data
;
749 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
751 struct irq_data
*d
= irq_get_irq_data(irq
);
752 return d
? d
->common
->msi_desc
: NULL
;
755 static inline struct msi_desc
*irq_data_get_msi_desc(struct irq_data
*d
)
757 return d
->common
->msi_desc
;
760 static inline u32
irq_get_trigger_type(unsigned int irq
)
762 struct irq_data
*d
= irq_get_irq_data(irq
);
763 return d
? irqd_get_trigger_type(d
) : 0;
766 static inline int irq_common_data_get_node(struct irq_common_data
*d
)
775 static inline int irq_data_get_node(struct irq_data
*d
)
777 return irq_common_data_get_node(d
->common
);
780 static inline struct cpumask
*irq_get_affinity_mask(int irq
)
782 struct irq_data
*d
= irq_get_irq_data(irq
);
784 return d
? d
->common
->affinity
: NULL
;
787 static inline struct cpumask
*irq_data_get_affinity_mask(struct irq_data
*d
)
789 return d
->common
->affinity
;
792 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
794 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
796 return d
->common
->effective_affinity
;
798 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
799 const struct cpumask
*m
)
801 cpumask_copy(d
->common
->effective_affinity
, m
);
804 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
805 const struct cpumask
*m
)
809 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
811 return d
->common
->affinity
;
815 unsigned int arch_dynirq_lower_bound(unsigned int from
);
817 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
818 struct module
*owner
, const struct cpumask
*affinity
);
820 int __devm_irq_alloc_descs(struct device
*dev
, int irq
, unsigned int from
,
821 unsigned int cnt
, int node
, struct module
*owner
,
822 const struct cpumask
*affinity
);
824 /* use macros to avoid needing export.h for THIS_MODULE */
825 #define irq_alloc_descs(irq, from, cnt, node) \
826 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
828 #define irq_alloc_desc(node) \
829 irq_alloc_descs(-1, 0, 1, node)
831 #define irq_alloc_desc_at(at, node) \
832 irq_alloc_descs(at, at, 1, node)
834 #define irq_alloc_desc_from(from, node) \
835 irq_alloc_descs(-1, from, 1, node)
837 #define irq_alloc_descs_from(from, cnt, node) \
838 irq_alloc_descs(-1, from, cnt, node)
840 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
841 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
843 #define devm_irq_alloc_desc(dev, node) \
844 devm_irq_alloc_descs(dev, -1, 0, 1, node)
846 #define devm_irq_alloc_desc_at(dev, at, node) \
847 devm_irq_alloc_descs(dev, at, at, 1, node)
849 #define devm_irq_alloc_desc_from(dev, from, node) \
850 devm_irq_alloc_descs(dev, -1, from, 1, node)
852 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
853 devm_irq_alloc_descs(dev, -1, from, cnt, node)
855 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
856 static inline void irq_free_desc(unsigned int irq
)
858 irq_free_descs(irq
, 1);
861 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
862 unsigned int irq_alloc_hwirqs(int cnt
, int node
);
863 static inline unsigned int irq_alloc_hwirq(int node
)
865 return irq_alloc_hwirqs(1, node
);
867 void irq_free_hwirqs(unsigned int from
, int cnt
);
868 static inline void irq_free_hwirq(unsigned int irq
)
870 return irq_free_hwirqs(irq
, 1);
872 int arch_setup_hwirq(unsigned int irq
, int node
);
873 void arch_teardown_hwirq(unsigned int irq
);
876 #ifdef CONFIG_GENERIC_IRQ_LEGACY
877 void irq_init_desc(unsigned int irq
);
881 * struct irq_chip_regs - register offsets for struct irq_gci
882 * @enable: Enable register offset to reg_base
883 * @disable: Disable register offset to reg_base
884 * @mask: Mask register offset to reg_base
885 * @ack: Ack register offset to reg_base
886 * @eoi: Eoi register offset to reg_base
887 * @type: Type configuration register offset to reg_base
888 * @polarity: Polarity configuration register offset to reg_base
890 struct irq_chip_regs
{
891 unsigned long enable
;
892 unsigned long disable
;
897 unsigned long polarity
;
901 * struct irq_chip_type - Generic interrupt chip instance for a flow type
902 * @chip: The real interrupt chip which provides the callbacks
903 * @regs: Register offsets for this chip
904 * @handler: Flow handler associated with this chip
905 * @type: Chip can handle these flow types
906 * @mask_cache_priv: Cached mask register private to the chip type
907 * @mask_cache: Pointer to cached mask register
909 * A irq_generic_chip can have several instances of irq_chip_type when
910 * it requires different functions and register offsets for different
913 struct irq_chip_type
{
914 struct irq_chip chip
;
915 struct irq_chip_regs regs
;
916 irq_flow_handler_t handler
;
923 * struct irq_chip_generic - Generic irq chip data structure
924 * @lock: Lock to protect register and cache data access
925 * @reg_base: Register base address (virtual)
926 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
927 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
928 * @suspend: Function called from core code on suspend once per
929 * chip; can be useful instead of irq_chip::suspend to
930 * handle chip details even when no interrupts are in use
931 * @resume: Function called from core code on resume once per chip;
932 * can be useful instead of irq_chip::suspend to handle
933 * chip details even when no interrupts are in use
934 * @irq_base: Interrupt base nr for this chip
935 * @irq_cnt: Number of interrupts handled by this chip
936 * @mask_cache: Cached mask register shared between all chip types
937 * @type_cache: Cached type register
938 * @polarity_cache: Cached polarity register
939 * @wake_enabled: Interrupt can wakeup from suspend
940 * @wake_active: Interrupt is marked as an wakeup from suspend source
941 * @num_ct: Number of available irq_chip_type instances (usually 1)
942 * @private: Private data for non generic chip callbacks
943 * @installed: bitfield to denote installed interrupts
944 * @unused: bitfield to denote unused interrupts
945 * @domain: irq domain pointer
946 * @list: List head for keeping track of instances
947 * @chip_types: Array of interrupt irq_chip_types
949 * Note, that irq_chip_generic can have multiple irq_chip_type
950 * implementations which can be associated to a particular irq line of
951 * an irq_chip_generic instance. That allows to share and protect
952 * state in an irq_chip_generic instance when we need to implement
953 * different flow mechanisms (level/edge) for it.
955 struct irq_chip_generic
{
957 void __iomem
*reg_base
;
958 u32 (*reg_readl
)(void __iomem
*addr
);
959 void (*reg_writel
)(u32 val
, void __iomem
*addr
);
960 void (*suspend
)(struct irq_chip_generic
*gc
);
961 void (*resume
)(struct irq_chip_generic
*gc
);
962 unsigned int irq_base
;
963 unsigned int irq_cnt
;
971 unsigned long installed
;
972 unsigned long unused
;
973 struct irq_domain
*domain
;
974 struct list_head list
;
975 struct irq_chip_type chip_types
[0];
979 * enum irq_gc_flags - Initialization flags for generic irq chips
980 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
981 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
982 * irq chips which need to call irq_set_wake() on
983 * the parent irq. Usually GPIO implementations
984 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
985 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
986 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
989 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
990 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
991 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
992 IRQ_GC_NO_MASK
= 1 << 3,
993 IRQ_GC_BE_IO
= 1 << 4,
997 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
998 * @irqs_per_chip: Number of interrupts per chip
999 * @num_chips: Number of chips
1000 * @irq_flags_to_set: IRQ* flags to set on irq setup
1001 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1002 * @gc_flags: Generic chip specific setup flags
1003 * @gc: Array of pointers to generic interrupt chips
1005 struct irq_domain_chip_generic
{
1006 unsigned int irqs_per_chip
;
1007 unsigned int num_chips
;
1008 unsigned int irq_flags_to_clear
;
1009 unsigned int irq_flags_to_set
;
1010 enum irq_gc_flags gc_flags
;
1011 struct irq_chip_generic
*gc
[0];
1014 /* Generic chip callback functions */
1015 void irq_gc_noop(struct irq_data
*d
);
1016 void irq_gc_mask_disable_reg(struct irq_data
*d
);
1017 void irq_gc_mask_set_bit(struct irq_data
*d
);
1018 void irq_gc_mask_clr_bit(struct irq_data
*d
);
1019 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
1020 void irq_gc_ack_set_bit(struct irq_data
*d
);
1021 void irq_gc_ack_clr_bit(struct irq_data
*d
);
1022 void irq_gc_mask_disable_and_ack_set(struct irq_data
*d
);
1023 void irq_gc_eoi(struct irq_data
*d
);
1024 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
1026 /* Setup functions for irq_chip_generic */
1027 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
1028 irq_hw_number_t hw_irq
);
1029 struct irq_chip_generic
*
1030 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
1031 void __iomem
*reg_base
, irq_flow_handler_t handler
);
1032 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1033 enum irq_gc_flags flags
, unsigned int clr
,
1035 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
1036 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1037 unsigned int clr
, unsigned int set
);
1039 struct irq_chip_generic
*
1040 devm_irq_alloc_generic_chip(struct device
*dev
, const char *name
, int num_ct
,
1041 unsigned int irq_base
, void __iomem
*reg_base
,
1042 irq_flow_handler_t handler
);
1043 int devm_irq_setup_generic_chip(struct device
*dev
, struct irq_chip_generic
*gc
,
1044 u32 msk
, enum irq_gc_flags flags
,
1045 unsigned int clr
, unsigned int set
);
1047 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
1049 int __irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
1050 int num_ct
, const char *name
,
1051 irq_flow_handler_t handler
,
1052 unsigned int clr
, unsigned int set
,
1053 enum irq_gc_flags flags
);
1055 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1056 handler, clr, set, flags) \
1058 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1059 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1060 handler, clr, set, flags); \
1063 static inline void irq_free_generic_chip(struct irq_chip_generic
*gc
)
1068 static inline void irq_destroy_generic_chip(struct irq_chip_generic
*gc
,
1069 u32 msk
, unsigned int clr
,
1072 irq_remove_generic_chip(gc
, msk
, clr
, set
);
1073 irq_free_generic_chip(gc
);
1076 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
1078 return container_of(d
->chip
, struct irq_chip_type
, chip
);
1081 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1084 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
1086 raw_spin_lock(&gc
->lock
);
1089 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
1091 raw_spin_unlock(&gc
->lock
);
1094 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
1095 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
1099 * The irqsave variants are for usage in non interrupt code. Do not use
1100 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1102 #define irq_gc_lock_irqsave(gc, flags) \
1103 raw_spin_lock_irqsave(&(gc)->lock, flags)
1105 #define irq_gc_unlock_irqrestore(gc, flags) \
1106 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1108 static inline void irq_reg_writel(struct irq_chip_generic
*gc
,
1109 u32 val
, int reg_offset
)
1112 gc
->reg_writel(val
, gc
->reg_base
+ reg_offset
);
1114 writel(val
, gc
->reg_base
+ reg_offset
);
1117 static inline u32
irq_reg_readl(struct irq_chip_generic
*gc
,
1121 return gc
->reg_readl(gc
->reg_base
+ reg_offset
);
1123 return readl(gc
->reg_base
+ reg_offset
);
1127 struct irq_matrix
*irq_alloc_matrix(unsigned int matrix_bits
,
1128 unsigned int alloc_start
,
1129 unsigned int alloc_end
);
1130 void irq_matrix_online(struct irq_matrix
*m
);
1131 void irq_matrix_offline(struct irq_matrix
*m
);
1132 void irq_matrix_assign_system(struct irq_matrix
*m
, unsigned int bit
, bool replace
);
1133 int irq_matrix_reserve_managed(struct irq_matrix
*m
, const struct cpumask
*msk
);
1134 void irq_matrix_remove_managed(struct irq_matrix
*m
, const struct cpumask
*msk
);
1135 int irq_matrix_alloc_managed(struct irq_matrix
*m
, unsigned int cpu
);
1136 void irq_matrix_reserve(struct irq_matrix
*m
);
1137 void irq_matrix_remove_reserved(struct irq_matrix
*m
);
1138 int irq_matrix_alloc(struct irq_matrix
*m
, const struct cpumask
*msk
,
1139 bool reserved
, unsigned int *mapped_cpu
);
1140 void irq_matrix_free(struct irq_matrix
*m
, unsigned int cpu
,
1141 unsigned int bit
, bool managed
);
1142 void irq_matrix_assign(struct irq_matrix
*m
, unsigned int bit
);
1143 unsigned int irq_matrix_available(struct irq_matrix
*m
, bool cpudown
);
1144 unsigned int irq_matrix_allocated(struct irq_matrix
*m
);
1145 unsigned int irq_matrix_reserved(struct irq_matrix
*m
);
1146 void irq_matrix_debug_show(struct seq_file
*sf
, struct irq_matrix
*m
, int ind
);
1148 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1149 #define INVALID_HWIRQ (~0UL)
1150 irq_hw_number_t
ipi_get_hwirq(unsigned int irq
, unsigned int cpu
);
1151 int __ipi_send_single(struct irq_desc
*desc
, unsigned int cpu
);
1152 int __ipi_send_mask(struct irq_desc
*desc
, const struct cpumask
*dest
);
1153 int ipi_send_single(unsigned int virq
, unsigned int cpu
);
1154 int ipi_send_mask(unsigned int virq
, const struct cpumask
*dest
);
1156 #endif /* _LINUX_IRQ_H */