1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
21 #include <linux/slab.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
30 struct irq_affinity_desc
;
31 enum irqchip_irq_state
;
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
57 * bits are modified via irq_set_irq_type()
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
72 * mechanism and from core side polling.
73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
76 IRQ_TYPE_NONE
= 0x00000000,
77 IRQ_TYPE_EDGE_RISING
= 0x00000001,
78 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
79 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
80 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
81 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
82 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
83 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
84 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
86 IRQ_TYPE_PROBE
= 0x00000010,
89 IRQ_PER_CPU
= (1 << 9),
90 IRQ_NOPROBE
= (1 << 10),
91 IRQ_NOREQUEST
= (1 << 11),
92 IRQ_NOAUTOEN
= (1 << 12),
93 IRQ_NO_BALANCING
= (1 << 13),
94 IRQ_MOVE_PCNTXT
= (1 << 14),
95 IRQ_NESTED_THREAD
= (1 << 15),
96 IRQ_NOTHREAD
= (1 << 16),
97 IRQ_PER_CPU_DEVID
= (1 << 17),
98 IRQ_IS_POLLED
= (1 << 18),
99 IRQ_DISABLE_UNLAZY
= (1 << 19),
102 #define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
106 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
111 * Return value for chip->irq_set_affinity()
113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116 * support stacked irqchips, which indicates skipping
117 * all descendent irqchips.
121 IRQ_SET_MASK_OK_NOCOPY
,
122 IRQ_SET_MASK_OK_DONE
,
129 * struct irq_common_data - per irq data shared by all irqchips
130 * @state_use_accessors: status information for irq chip functions.
131 * Use accessor functions to deal with it
132 * @node: node index useful for balancing
133 * @handler_data: per-IRQ data for the irq_chip methods
134 * @affinity: IRQ affinity on SMP. If this is an IPI
135 * related irq, then this is the mask of the
136 * CPUs to which an IPI can be sent.
137 * @effective_affinity: The effective IRQ affinity on SMP as some irq
138 * chips do not allow multi CPU destinations.
139 * A subset of @affinity.
140 * @msi_desc: MSI descriptor
141 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
143 struct irq_common_data
{
144 unsigned int __private state_use_accessors
;
149 struct msi_desc
*msi_desc
;
150 cpumask_var_t affinity
;
151 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
152 cpumask_var_t effective_affinity
;
154 #ifdef CONFIG_GENERIC_IRQ_IPI
155 unsigned int ipi_offset
;
160 * struct irq_data - per irq chip data passed down to chip functions
161 * @mask: precomputed bitmask for accessing the chip registers
162 * @irq: interrupt number
163 * @hwirq: hardware interrupt number, local to the interrupt domain
164 * @common: point to data shared by all irqchips
165 * @chip: low level interrupt hardware access
166 * @domain: Interrupt translation domain; responsible for mapping
167 * between hwirq number and linux irq number.
168 * @parent_data: pointer to parent struct irq_data to support hierarchy
170 * @chip_data: platform-specific per-chip private data for the chip
171 * methods, to allow shared chip implementations
177 struct irq_common_data
*common
;
178 struct irq_chip
*chip
;
179 struct irq_domain
*domain
;
180 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
181 struct irq_data
*parent_data
;
187 * Bit masks for irq_common_data.state_use_accessors
189 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
190 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
191 * IRQD_ACTIVATED - Interrupt has already been activated
192 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
193 * IRQD_PER_CPU - Interrupt is per cpu
194 * IRQD_AFFINITY_SET - Interrupt affinity was set
195 * IRQD_LEVEL - Interrupt is level triggered
196 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
198 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
200 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
201 * IRQD_IRQ_MASKED - Masked state of the interrupt
202 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
203 * IRQD_WAKEUP_ARMED - Wakeup mode armed
204 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
205 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
206 * IRQD_IRQ_STARTED - Startup state of the interrupt
207 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
208 * mask. Applies only to affinity managed irqs.
209 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
210 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
211 * IRQD_CAN_RESERVE - Can use reservation mode
212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
214 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
215 * from actual interrupt context.
218 IRQD_TRIGGER_MASK
= 0xf,
219 IRQD_SETAFFINITY_PENDING
= (1 << 8),
220 IRQD_ACTIVATED
= (1 << 9),
221 IRQD_NO_BALANCING
= (1 << 10),
222 IRQD_PER_CPU
= (1 << 11),
223 IRQD_AFFINITY_SET
= (1 << 12),
224 IRQD_LEVEL
= (1 << 13),
225 IRQD_WAKEUP_STATE
= (1 << 14),
226 IRQD_MOVE_PCNTXT
= (1 << 15),
227 IRQD_IRQ_DISABLED
= (1 << 16),
228 IRQD_IRQ_MASKED
= (1 << 17),
229 IRQD_IRQ_INPROGRESS
= (1 << 18),
230 IRQD_WAKEUP_ARMED
= (1 << 19),
231 IRQD_FORWARDED_TO_VCPU
= (1 << 20),
232 IRQD_AFFINITY_MANAGED
= (1 << 21),
233 IRQD_IRQ_STARTED
= (1 << 22),
234 IRQD_MANAGED_SHUTDOWN
= (1 << 23),
235 IRQD_SINGLE_TARGET
= (1 << 24),
236 IRQD_DEFAULT_TRIGGER_SET
= (1 << 25),
237 IRQD_CAN_RESERVE
= (1 << 26),
238 IRQD_MSI_NOMASK_QUIRK
= (1 << 27),
239 IRQD_HANDLE_ENFORCE_IRQCTX
= (1 << 28),
242 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
244 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
246 return __irqd_to_state(d
) & IRQD_SETAFFINITY_PENDING
;
249 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
251 return __irqd_to_state(d
) & IRQD_PER_CPU
;
254 static inline bool irqd_can_balance(struct irq_data
*d
)
256 return !(__irqd_to_state(d
) & (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
259 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
261 return __irqd_to_state(d
) & IRQD_AFFINITY_SET
;
264 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
266 __irqd_to_state(d
) |= IRQD_AFFINITY_SET
;
269 static inline bool irqd_trigger_type_was_set(struct irq_data
*d
)
271 return __irqd_to_state(d
) & IRQD_DEFAULT_TRIGGER_SET
;
274 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
276 return __irqd_to_state(d
) & IRQD_TRIGGER_MASK
;
280 * Must only be called inside irq_chip.irq_set_type() functions or
281 * from the DT/ACPI setup code.
283 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
285 __irqd_to_state(d
) &= ~IRQD_TRIGGER_MASK
;
286 __irqd_to_state(d
) |= type
& IRQD_TRIGGER_MASK
;
287 __irqd_to_state(d
) |= IRQD_DEFAULT_TRIGGER_SET
;
290 static inline bool irqd_is_level_type(struct irq_data
*d
)
292 return __irqd_to_state(d
) & IRQD_LEVEL
;
296 * Must only be called of irqchip.irq_set_affinity() or low level
297 * hieararchy domain allocation functions.
299 static inline void irqd_set_single_target(struct irq_data
*d
)
301 __irqd_to_state(d
) |= IRQD_SINGLE_TARGET
;
304 static inline bool irqd_is_single_target(struct irq_data
*d
)
306 return __irqd_to_state(d
) & IRQD_SINGLE_TARGET
;
309 static inline void irqd_set_handle_enforce_irqctx(struct irq_data
*d
)
311 __irqd_to_state(d
) |= IRQD_HANDLE_ENFORCE_IRQCTX
;
314 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data
*d
)
316 return __irqd_to_state(d
) & IRQD_HANDLE_ENFORCE_IRQCTX
;
319 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
321 return __irqd_to_state(d
) & IRQD_WAKEUP_STATE
;
324 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
326 return __irqd_to_state(d
) & IRQD_MOVE_PCNTXT
;
329 static inline bool irqd_irq_disabled(struct irq_data
*d
)
331 return __irqd_to_state(d
) & IRQD_IRQ_DISABLED
;
334 static inline bool irqd_irq_masked(struct irq_data
*d
)
336 return __irqd_to_state(d
) & IRQD_IRQ_MASKED
;
339 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
341 return __irqd_to_state(d
) & IRQD_IRQ_INPROGRESS
;
344 static inline bool irqd_is_wakeup_armed(struct irq_data
*d
)
346 return __irqd_to_state(d
) & IRQD_WAKEUP_ARMED
;
349 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data
*d
)
351 return __irqd_to_state(d
) & IRQD_FORWARDED_TO_VCPU
;
354 static inline void irqd_set_forwarded_to_vcpu(struct irq_data
*d
)
356 __irqd_to_state(d
) |= IRQD_FORWARDED_TO_VCPU
;
359 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data
*d
)
361 __irqd_to_state(d
) &= ~IRQD_FORWARDED_TO_VCPU
;
364 static inline bool irqd_affinity_is_managed(struct irq_data
*d
)
366 return __irqd_to_state(d
) & IRQD_AFFINITY_MANAGED
;
369 static inline bool irqd_is_activated(struct irq_data
*d
)
371 return __irqd_to_state(d
) & IRQD_ACTIVATED
;
374 static inline void irqd_set_activated(struct irq_data
*d
)
376 __irqd_to_state(d
) |= IRQD_ACTIVATED
;
379 static inline void irqd_clr_activated(struct irq_data
*d
)
381 __irqd_to_state(d
) &= ~IRQD_ACTIVATED
;
384 static inline bool irqd_is_started(struct irq_data
*d
)
386 return __irqd_to_state(d
) & IRQD_IRQ_STARTED
;
389 static inline bool irqd_is_managed_and_shutdown(struct irq_data
*d
)
391 return __irqd_to_state(d
) & IRQD_MANAGED_SHUTDOWN
;
394 static inline void irqd_set_can_reserve(struct irq_data
*d
)
396 __irqd_to_state(d
) |= IRQD_CAN_RESERVE
;
399 static inline void irqd_clr_can_reserve(struct irq_data
*d
)
401 __irqd_to_state(d
) &= ~IRQD_CAN_RESERVE
;
404 static inline bool irqd_can_reserve(struct irq_data
*d
)
406 return __irqd_to_state(d
) & IRQD_CAN_RESERVE
;
409 static inline void irqd_set_msi_nomask_quirk(struct irq_data
*d
)
411 __irqd_to_state(d
) |= IRQD_MSI_NOMASK_QUIRK
;
414 static inline void irqd_clr_msi_nomask_quirk(struct irq_data
*d
)
416 __irqd_to_state(d
) &= ~IRQD_MSI_NOMASK_QUIRK
;
419 static inline bool irqd_msi_nomask_quirk(struct irq_data
*d
)
421 return __irqd_to_state(d
) & IRQD_MSI_NOMASK_QUIRK
;
424 #undef __irqd_to_state
426 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
432 * struct irq_chip - hardware interrupt chip descriptor
434 * @parent_device: pointer to parent device for irqchip
435 * @name: name for /proc/interrupts
436 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
437 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
438 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
439 * @irq_disable: disable the interrupt
440 * @irq_ack: start of a new interrupt
441 * @irq_mask: mask an interrupt source
442 * @irq_mask_ack: ack and mask an interrupt source
443 * @irq_unmask: unmask an interrupt source
444 * @irq_eoi: end of interrupt
445 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
446 * argument is true, it tells the driver to
447 * unconditionally apply the affinity setting. Sanity
448 * checks against the supplied affinity mask are not
449 * required. This is used for CPU hotplug where the
450 * target CPU is not yet set in the cpu_online_mask.
451 * @irq_retrigger: resend an IRQ to the CPU
452 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
453 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
454 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
455 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
456 * @irq_cpu_online: configure an interrupt source for a secondary CPU
457 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
458 * @irq_suspend: function called from core code on suspend once per
459 * chip, when one or more interrupts are installed
460 * @irq_resume: function called from core code on resume once per chip,
461 * when one ore more interrupts are installed
462 * @irq_pm_shutdown: function called from core code on shutdown once per chip
463 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
464 * @irq_print_chip: optional to print special chip info in show_interrupts
465 * @irq_request_resources: optional to request resources before calling
466 * any other callback related to this irq
467 * @irq_release_resources: optional to release resources acquired with
468 * irq_request_resources
469 * @irq_compose_msi_msg: optional to compose message content for MSI
470 * @irq_write_msi_msg: optional to write message content for MSI
471 * @irq_get_irqchip_state: return the internal state of an interrupt
472 * @irq_set_irqchip_state: set the internal state of a interrupt
473 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
474 * @ipi_send_single: send a single IPI to destination cpus
475 * @ipi_send_mask: send an IPI to destination cpus in cpumask
476 * @irq_nmi_setup: function called from core code before enabling an NMI
477 * @irq_nmi_teardown: function called from core code after disabling an NMI
478 * @flags: chip specific flags
481 struct device
*parent_device
;
483 unsigned int (*irq_startup
)(struct irq_data
*data
);
484 void (*irq_shutdown
)(struct irq_data
*data
);
485 void (*irq_enable
)(struct irq_data
*data
);
486 void (*irq_disable
)(struct irq_data
*data
);
488 void (*irq_ack
)(struct irq_data
*data
);
489 void (*irq_mask
)(struct irq_data
*data
);
490 void (*irq_mask_ack
)(struct irq_data
*data
);
491 void (*irq_unmask
)(struct irq_data
*data
);
492 void (*irq_eoi
)(struct irq_data
*data
);
494 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
495 int (*irq_retrigger
)(struct irq_data
*data
);
496 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
497 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
499 void (*irq_bus_lock
)(struct irq_data
*data
);
500 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
502 void (*irq_cpu_online
)(struct irq_data
*data
);
503 void (*irq_cpu_offline
)(struct irq_data
*data
);
505 void (*irq_suspend
)(struct irq_data
*data
);
506 void (*irq_resume
)(struct irq_data
*data
);
507 void (*irq_pm_shutdown
)(struct irq_data
*data
);
509 void (*irq_calc_mask
)(struct irq_data
*data
);
511 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
512 int (*irq_request_resources
)(struct irq_data
*data
);
513 void (*irq_release_resources
)(struct irq_data
*data
);
515 void (*irq_compose_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
516 void (*irq_write_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
518 int (*irq_get_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool *state
);
519 int (*irq_set_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool state
);
521 int (*irq_set_vcpu_affinity
)(struct irq_data
*data
, void *vcpu_info
);
523 void (*ipi_send_single
)(struct irq_data
*data
, unsigned int cpu
);
524 void (*ipi_send_mask
)(struct irq_data
*data
, const struct cpumask
*dest
);
526 int (*irq_nmi_setup
)(struct irq_data
*data
);
527 void (*irq_nmi_teardown
)(struct irq_data
*data
);
533 * irq_chip specific flags
535 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
536 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
537 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
538 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
540 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
541 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
542 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
543 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs
544 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
547 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
548 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
549 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
550 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
551 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
552 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
553 IRQCHIP_EOI_THREADED
= (1 << 6),
554 IRQCHIP_SUPPORTS_LEVEL_MSI
= (1 << 7),
555 IRQCHIP_SUPPORTS_NMI
= (1 << 8),
558 #include <linux/irqdesc.h>
561 * Pick up the arch-dependent methods:
563 #include <asm/hw_irq.h>
565 #ifndef NR_IRQS_LEGACY
566 # define NR_IRQS_LEGACY 0
569 #ifndef ARCH_IRQ_INIT_FLAGS
570 # define ARCH_IRQ_INIT_FLAGS 0
573 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
576 extern int setup_irq(unsigned int irq
, struct irqaction
*new);
577 extern void remove_irq(unsigned int irq
, struct irqaction
*act
);
578 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
579 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
581 extern void irq_cpu_online(void);
582 extern void irq_cpu_offline(void);
583 extern int irq_set_affinity_locked(struct irq_data
*data
,
584 const struct cpumask
*cpumask
, bool force
);
585 extern int irq_set_vcpu_affinity(unsigned int irq
, void *vcpu_info
);
587 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
588 extern void irq_migrate_all_off_this_cpu(void);
589 extern int irq_affinity_online_cpu(unsigned int cpu
);
591 # define irq_affinity_online_cpu NULL
594 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
595 void __irq_move_irq(struct irq_data
*data
);
596 static inline void irq_move_irq(struct irq_data
*data
)
598 if (unlikely(irqd_is_setaffinity_pending(data
)))
599 __irq_move_irq(data
);
601 void irq_move_masked_irq(struct irq_data
*data
);
602 void irq_force_complete_move(struct irq_desc
*desc
);
604 static inline void irq_move_irq(struct irq_data
*data
) { }
605 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
606 static inline void irq_force_complete_move(struct irq_desc
*desc
) { }
609 extern int no_irq_affinity
;
611 #ifdef CONFIG_HARDIRQS_SW_RESEND
612 int irq_set_parent(int irq
, int parent_irq
);
614 static inline int irq_set_parent(int irq
, int parent_irq
)
621 * Built-in IRQ handlers for various IRQ types,
622 * callable via desc->handle_irq()
624 extern void handle_level_irq(struct irq_desc
*desc
);
625 extern void handle_fasteoi_irq(struct irq_desc
*desc
);
626 extern void handle_edge_irq(struct irq_desc
*desc
);
627 extern void handle_edge_eoi_irq(struct irq_desc
*desc
);
628 extern void handle_simple_irq(struct irq_desc
*desc
);
629 extern void handle_untracked_irq(struct irq_desc
*desc
);
630 extern void handle_percpu_irq(struct irq_desc
*desc
);
631 extern void handle_percpu_devid_irq(struct irq_desc
*desc
);
632 extern void handle_bad_irq(struct irq_desc
*desc
);
633 extern void handle_nested_irq(unsigned int irq
);
635 extern void handle_fasteoi_nmi(struct irq_desc
*desc
);
636 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc
*desc
);
638 extern int irq_chip_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
);
639 extern int irq_chip_pm_get(struct irq_data
*data
);
640 extern int irq_chip_pm_put(struct irq_data
*data
);
641 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
642 extern void handle_fasteoi_ack_irq(struct irq_desc
*desc
);
643 extern void handle_fasteoi_mask_irq(struct irq_desc
*desc
);
644 extern int irq_chip_set_parent_state(struct irq_data
*data
,
645 enum irqchip_irq_state which
,
647 extern int irq_chip_get_parent_state(struct irq_data
*data
,
648 enum irqchip_irq_state which
,
650 extern void irq_chip_enable_parent(struct irq_data
*data
);
651 extern void irq_chip_disable_parent(struct irq_data
*data
);
652 extern void irq_chip_ack_parent(struct irq_data
*data
);
653 extern int irq_chip_retrigger_hierarchy(struct irq_data
*data
);
654 extern void irq_chip_mask_parent(struct irq_data
*data
);
655 extern void irq_chip_mask_ack_parent(struct irq_data
*data
);
656 extern void irq_chip_unmask_parent(struct irq_data
*data
);
657 extern void irq_chip_eoi_parent(struct irq_data
*data
);
658 extern int irq_chip_set_affinity_parent(struct irq_data
*data
,
659 const struct cpumask
*dest
,
661 extern int irq_chip_set_wake_parent(struct irq_data
*data
, unsigned int on
);
662 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data
,
664 extern int irq_chip_set_type_parent(struct irq_data
*data
, unsigned int type
);
665 extern int irq_chip_request_resources_parent(struct irq_data
*data
);
666 extern void irq_chip_release_resources_parent(struct irq_data
*data
);
669 /* Handling of unhandled and spurious interrupts: */
670 extern void note_interrupt(struct irq_desc
*desc
, irqreturn_t action_ret
);
673 /* Enable/disable irq debugging output: */
674 extern int noirqdebug_setup(char *str
);
676 /* Checks whether the interrupt can be requested by request_irq(): */
677 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
679 /* Dummy irq-chip implementations: */
680 extern struct irq_chip no_irq_chip
;
681 extern struct irq_chip dummy_irq_chip
;
684 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
685 irq_flow_handler_t handle
, const char *name
);
687 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
688 irq_flow_handler_t handle
)
690 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
693 extern int irq_set_percpu_devid(unsigned int irq
);
694 extern int irq_set_percpu_devid_partition(unsigned int irq
,
695 const struct cpumask
*affinity
);
696 extern int irq_get_percpu_devid_partition(unsigned int irq
,
697 struct cpumask
*affinity
);
700 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
704 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
706 __irq_set_handler(irq
, handle
, 0, NULL
);
710 * Set a highlevel chained flow handler for a given IRQ.
711 * (a chained handler is automatically enabled and set to
712 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
715 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
717 __irq_set_handler(irq
, handle
, 1, NULL
);
721 * Set a highlevel chained flow handler and its data for a given IRQ.
722 * (a chained handler is automatically enabled and set to
723 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
726 irq_set_chained_handler_and_data(unsigned int irq
, irq_flow_handler_t handle
,
729 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
731 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
733 irq_modify_status(irq
, 0, set
);
736 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
738 irq_modify_status(irq
, clr
, 0);
741 static inline void irq_set_noprobe(unsigned int irq
)
743 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
746 static inline void irq_set_probe(unsigned int irq
)
748 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
751 static inline void irq_set_nothread(unsigned int irq
)
753 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
756 static inline void irq_set_thread(unsigned int irq
)
758 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
761 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
764 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
766 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
769 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
771 irq_set_status_flags(irq
,
772 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
773 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
776 /* Set/get chip/data for an IRQ: */
777 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
778 extern int irq_set_handler_data(unsigned int irq
, void *data
);
779 extern int irq_set_chip_data(unsigned int irq
, void *data
);
780 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
781 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
782 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
783 struct msi_desc
*entry
);
784 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
786 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
788 struct irq_data
*d
= irq_get_irq_data(irq
);
789 return d
? d
->chip
: NULL
;
792 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
797 static inline void *irq_get_chip_data(unsigned int irq
)
799 struct irq_data
*d
= irq_get_irq_data(irq
);
800 return d
? d
->chip_data
: NULL
;
803 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
808 static inline void *irq_get_handler_data(unsigned int irq
)
810 struct irq_data
*d
= irq_get_irq_data(irq
);
811 return d
? d
->common
->handler_data
: NULL
;
814 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
816 return d
->common
->handler_data
;
819 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
821 struct irq_data
*d
= irq_get_irq_data(irq
);
822 return d
? d
->common
->msi_desc
: NULL
;
825 static inline struct msi_desc
*irq_data_get_msi_desc(struct irq_data
*d
)
827 return d
->common
->msi_desc
;
830 static inline u32
irq_get_trigger_type(unsigned int irq
)
832 struct irq_data
*d
= irq_get_irq_data(irq
);
833 return d
? irqd_get_trigger_type(d
) : 0;
836 static inline int irq_common_data_get_node(struct irq_common_data
*d
)
845 static inline int irq_data_get_node(struct irq_data
*d
)
847 return irq_common_data_get_node(d
->common
);
850 static inline struct cpumask
*irq_get_affinity_mask(int irq
)
852 struct irq_data
*d
= irq_get_irq_data(irq
);
854 return d
? d
->common
->affinity
: NULL
;
857 static inline struct cpumask
*irq_data_get_affinity_mask(struct irq_data
*d
)
859 return d
->common
->affinity
;
862 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
864 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
866 return d
->common
->effective_affinity
;
868 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
869 const struct cpumask
*m
)
871 cpumask_copy(d
->common
->effective_affinity
, m
);
874 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
875 const struct cpumask
*m
)
879 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
881 return d
->common
->affinity
;
885 unsigned int arch_dynirq_lower_bound(unsigned int from
);
887 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
888 struct module
*owner
,
889 const struct irq_affinity_desc
*affinity
);
891 int __devm_irq_alloc_descs(struct device
*dev
, int irq
, unsigned int from
,
892 unsigned int cnt
, int node
, struct module
*owner
,
893 const struct irq_affinity_desc
*affinity
);
895 /* use macros to avoid needing export.h for THIS_MODULE */
896 #define irq_alloc_descs(irq, from, cnt, node) \
897 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
899 #define irq_alloc_desc(node) \
900 irq_alloc_descs(-1, 0, 1, node)
902 #define irq_alloc_desc_at(at, node) \
903 irq_alloc_descs(at, at, 1, node)
905 #define irq_alloc_desc_from(from, node) \
906 irq_alloc_descs(-1, from, 1, node)
908 #define irq_alloc_descs_from(from, cnt, node) \
909 irq_alloc_descs(-1, from, cnt, node)
911 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
912 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
914 #define devm_irq_alloc_desc(dev, node) \
915 devm_irq_alloc_descs(dev, -1, 0, 1, node)
917 #define devm_irq_alloc_desc_at(dev, at, node) \
918 devm_irq_alloc_descs(dev, at, at, 1, node)
920 #define devm_irq_alloc_desc_from(dev, from, node) \
921 devm_irq_alloc_descs(dev, -1, from, 1, node)
923 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
924 devm_irq_alloc_descs(dev, -1, from, cnt, node)
926 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
927 static inline void irq_free_desc(unsigned int irq
)
929 irq_free_descs(irq
, 1);
932 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
933 unsigned int irq_alloc_hwirqs(int cnt
, int node
);
934 static inline unsigned int irq_alloc_hwirq(int node
)
936 return irq_alloc_hwirqs(1, node
);
938 void irq_free_hwirqs(unsigned int from
, int cnt
);
939 static inline void irq_free_hwirq(unsigned int irq
)
941 return irq_free_hwirqs(irq
, 1);
943 int arch_setup_hwirq(unsigned int irq
, int node
);
944 void arch_teardown_hwirq(unsigned int irq
);
947 #ifdef CONFIG_GENERIC_IRQ_LEGACY
948 void irq_init_desc(unsigned int irq
);
952 * struct irq_chip_regs - register offsets for struct irq_gci
953 * @enable: Enable register offset to reg_base
954 * @disable: Disable register offset to reg_base
955 * @mask: Mask register offset to reg_base
956 * @ack: Ack register offset to reg_base
957 * @eoi: Eoi register offset to reg_base
958 * @type: Type configuration register offset to reg_base
959 * @polarity: Polarity configuration register offset to reg_base
961 struct irq_chip_regs
{
962 unsigned long enable
;
963 unsigned long disable
;
968 unsigned long polarity
;
972 * struct irq_chip_type - Generic interrupt chip instance for a flow type
973 * @chip: The real interrupt chip which provides the callbacks
974 * @regs: Register offsets for this chip
975 * @handler: Flow handler associated with this chip
976 * @type: Chip can handle these flow types
977 * @mask_cache_priv: Cached mask register private to the chip type
978 * @mask_cache: Pointer to cached mask register
980 * A irq_generic_chip can have several instances of irq_chip_type when
981 * it requires different functions and register offsets for different
984 struct irq_chip_type
{
985 struct irq_chip chip
;
986 struct irq_chip_regs regs
;
987 irq_flow_handler_t handler
;
994 * struct irq_chip_generic - Generic irq chip data structure
995 * @lock: Lock to protect register and cache data access
996 * @reg_base: Register base address (virtual)
997 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
998 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
999 * @suspend: Function called from core code on suspend once per
1000 * chip; can be useful instead of irq_chip::suspend to
1001 * handle chip details even when no interrupts are in use
1002 * @resume: Function called from core code on resume once per chip;
1003 * can be useful instead of irq_chip::suspend to handle
1004 * chip details even when no interrupts are in use
1005 * @irq_base: Interrupt base nr for this chip
1006 * @irq_cnt: Number of interrupts handled by this chip
1007 * @mask_cache: Cached mask register shared between all chip types
1008 * @type_cache: Cached type register
1009 * @polarity_cache: Cached polarity register
1010 * @wake_enabled: Interrupt can wakeup from suspend
1011 * @wake_active: Interrupt is marked as an wakeup from suspend source
1012 * @num_ct: Number of available irq_chip_type instances (usually 1)
1013 * @private: Private data for non generic chip callbacks
1014 * @installed: bitfield to denote installed interrupts
1015 * @unused: bitfield to denote unused interrupts
1016 * @domain: irq domain pointer
1017 * @list: List head for keeping track of instances
1018 * @chip_types: Array of interrupt irq_chip_types
1020 * Note, that irq_chip_generic can have multiple irq_chip_type
1021 * implementations which can be associated to a particular irq line of
1022 * an irq_chip_generic instance. That allows to share and protect
1023 * state in an irq_chip_generic instance when we need to implement
1024 * different flow mechanisms (level/edge) for it.
1026 struct irq_chip_generic
{
1027 raw_spinlock_t lock
;
1028 void __iomem
*reg_base
;
1029 u32 (*reg_readl
)(void __iomem
*addr
);
1030 void (*reg_writel
)(u32 val
, void __iomem
*addr
);
1031 void (*suspend
)(struct irq_chip_generic
*gc
);
1032 void (*resume
)(struct irq_chip_generic
*gc
);
1033 unsigned int irq_base
;
1034 unsigned int irq_cnt
;
1040 unsigned int num_ct
;
1042 unsigned long installed
;
1043 unsigned long unused
;
1044 struct irq_domain
*domain
;
1045 struct list_head list
;
1046 struct irq_chip_type chip_types
[];
1050 * enum irq_gc_flags - Initialization flags for generic irq chips
1051 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1052 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1053 * irq chips which need to call irq_set_wake() on
1054 * the parent irq. Usually GPIO implementations
1055 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1056 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1057 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1060 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
1061 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
1062 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
1063 IRQ_GC_NO_MASK
= 1 << 3,
1064 IRQ_GC_BE_IO
= 1 << 4,
1068 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1069 * @irqs_per_chip: Number of interrupts per chip
1070 * @num_chips: Number of chips
1071 * @irq_flags_to_set: IRQ* flags to set on irq setup
1072 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1073 * @gc_flags: Generic chip specific setup flags
1074 * @gc: Array of pointers to generic interrupt chips
1076 struct irq_domain_chip_generic
{
1077 unsigned int irqs_per_chip
;
1078 unsigned int num_chips
;
1079 unsigned int irq_flags_to_clear
;
1080 unsigned int irq_flags_to_set
;
1081 enum irq_gc_flags gc_flags
;
1082 struct irq_chip_generic
*gc
[];
1085 /* Generic chip callback functions */
1086 void irq_gc_noop(struct irq_data
*d
);
1087 void irq_gc_mask_disable_reg(struct irq_data
*d
);
1088 void irq_gc_mask_set_bit(struct irq_data
*d
);
1089 void irq_gc_mask_clr_bit(struct irq_data
*d
);
1090 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
1091 void irq_gc_ack_set_bit(struct irq_data
*d
);
1092 void irq_gc_ack_clr_bit(struct irq_data
*d
);
1093 void irq_gc_mask_disable_and_ack_set(struct irq_data
*d
);
1094 void irq_gc_eoi(struct irq_data
*d
);
1095 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
1097 /* Setup functions for irq_chip_generic */
1098 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
1099 irq_hw_number_t hw_irq
);
1100 struct irq_chip_generic
*
1101 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
1102 void __iomem
*reg_base
, irq_flow_handler_t handler
);
1103 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1104 enum irq_gc_flags flags
, unsigned int clr
,
1106 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
1107 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1108 unsigned int clr
, unsigned int set
);
1110 struct irq_chip_generic
*
1111 devm_irq_alloc_generic_chip(struct device
*dev
, const char *name
, int num_ct
,
1112 unsigned int irq_base
, void __iomem
*reg_base
,
1113 irq_flow_handler_t handler
);
1114 int devm_irq_setup_generic_chip(struct device
*dev
, struct irq_chip_generic
*gc
,
1115 u32 msk
, enum irq_gc_flags flags
,
1116 unsigned int clr
, unsigned int set
);
1118 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
1120 int __irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
1121 int num_ct
, const char *name
,
1122 irq_flow_handler_t handler
,
1123 unsigned int clr
, unsigned int set
,
1124 enum irq_gc_flags flags
);
1126 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1127 handler, clr, set, flags) \
1129 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1130 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1131 handler, clr, set, flags); \
1134 static inline void irq_free_generic_chip(struct irq_chip_generic
*gc
)
1139 static inline void irq_destroy_generic_chip(struct irq_chip_generic
*gc
,
1140 u32 msk
, unsigned int clr
,
1143 irq_remove_generic_chip(gc
, msk
, clr
, set
);
1144 irq_free_generic_chip(gc
);
1147 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
1149 return container_of(d
->chip
, struct irq_chip_type
, chip
);
1152 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1155 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
1157 raw_spin_lock(&gc
->lock
);
1160 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
1162 raw_spin_unlock(&gc
->lock
);
1165 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
1166 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
1170 * The irqsave variants are for usage in non interrupt code. Do not use
1171 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1173 #define irq_gc_lock_irqsave(gc, flags) \
1174 raw_spin_lock_irqsave(&(gc)->lock, flags)
1176 #define irq_gc_unlock_irqrestore(gc, flags) \
1177 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1179 static inline void irq_reg_writel(struct irq_chip_generic
*gc
,
1180 u32 val
, int reg_offset
)
1183 gc
->reg_writel(val
, gc
->reg_base
+ reg_offset
);
1185 writel(val
, gc
->reg_base
+ reg_offset
);
1188 static inline u32
irq_reg_readl(struct irq_chip_generic
*gc
,
1192 return gc
->reg_readl(gc
->reg_base
+ reg_offset
);
1194 return readl(gc
->reg_base
+ reg_offset
);
1198 struct irq_matrix
*irq_alloc_matrix(unsigned int matrix_bits
,
1199 unsigned int alloc_start
,
1200 unsigned int alloc_end
);
1201 void irq_matrix_online(struct irq_matrix
*m
);
1202 void irq_matrix_offline(struct irq_matrix
*m
);
1203 void irq_matrix_assign_system(struct irq_matrix
*m
, unsigned int bit
, bool replace
);
1204 int irq_matrix_reserve_managed(struct irq_matrix
*m
, const struct cpumask
*msk
);
1205 void irq_matrix_remove_managed(struct irq_matrix
*m
, const struct cpumask
*msk
);
1206 int irq_matrix_alloc_managed(struct irq_matrix
*m
, const struct cpumask
*msk
,
1207 unsigned int *mapped_cpu
);
1208 void irq_matrix_reserve(struct irq_matrix
*m
);
1209 void irq_matrix_remove_reserved(struct irq_matrix
*m
);
1210 int irq_matrix_alloc(struct irq_matrix
*m
, const struct cpumask
*msk
,
1211 bool reserved
, unsigned int *mapped_cpu
);
1212 void irq_matrix_free(struct irq_matrix
*m
, unsigned int cpu
,
1213 unsigned int bit
, bool managed
);
1214 void irq_matrix_assign(struct irq_matrix
*m
, unsigned int bit
);
1215 unsigned int irq_matrix_available(struct irq_matrix
*m
, bool cpudown
);
1216 unsigned int irq_matrix_allocated(struct irq_matrix
*m
);
1217 unsigned int irq_matrix_reserved(struct irq_matrix
*m
);
1218 void irq_matrix_debug_show(struct seq_file
*sf
, struct irq_matrix
*m
, int ind
);
1220 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1221 #define INVALID_HWIRQ (~0UL)
1222 irq_hw_number_t
ipi_get_hwirq(unsigned int irq
, unsigned int cpu
);
1223 int __ipi_send_single(struct irq_desc
*desc
, unsigned int cpu
);
1224 int __ipi_send_mask(struct irq_desc
*desc
, const struct cpumask
*dest
);
1225 int ipi_send_single(unsigned int virq
, unsigned int cpu
);
1226 int ipi_send_mask(unsigned int virq
, const struct cpumask
*dest
);
1228 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1230 * Registers a generic IRQ handling function as the top-level IRQ handler in
1231 * the system, which is generally the first C code called from an assembly
1232 * architecture-specific interrupt handler.
1234 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1237 int __init
set_handle_irq(void (*handle_irq
)(struct pt_regs
*));
1240 * Allows interrupt handlers to find the irqchip that's been registered as the
1241 * top-level IRQ handler.
1243 extern void (*handle_arch_irq
)(struct pt_regs
*) __ro_after_init
;
1246 #endif /* _LINUX_IRQ_H */