1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
21 #include <linux/slab.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
30 struct irq_affinity_desc
;
31 enum irqchip_irq_state
;
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
57 * bits are modified via irq_set_irq_type()
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
72 * mechanism and from core side polling.
73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
74 * IRQ_HIDDEN - Don't show up in /proc/interrupts
75 * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging
78 IRQ_TYPE_NONE
= 0x00000000,
79 IRQ_TYPE_EDGE_RISING
= 0x00000001,
80 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
81 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
82 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
83 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
84 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
85 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
86 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
88 IRQ_TYPE_PROBE
= 0x00000010,
91 IRQ_PER_CPU
= (1 << 9),
92 IRQ_NOPROBE
= (1 << 10),
93 IRQ_NOREQUEST
= (1 << 11),
94 IRQ_NOAUTOEN
= (1 << 12),
95 IRQ_NO_BALANCING
= (1 << 13),
96 IRQ_MOVE_PCNTXT
= (1 << 14),
97 IRQ_NESTED_THREAD
= (1 << 15),
98 IRQ_NOTHREAD
= (1 << 16),
99 IRQ_PER_CPU_DEVID
= (1 << 17),
100 IRQ_IS_POLLED
= (1 << 18),
101 IRQ_DISABLE_UNLAZY
= (1 << 19),
102 IRQ_HIDDEN
= (1 << 20),
103 IRQ_NO_DEBUG
= (1 << 21),
106 #define IRQF_MODIFY_MASK \
107 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
112 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
115 * Return value for chip->irq_set_affinity()
117 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
118 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
119 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
120 * support stacked irqchips, which indicates skipping
121 * all descendant irqchips.
125 IRQ_SET_MASK_OK_NOCOPY
,
126 IRQ_SET_MASK_OK_DONE
,
133 * struct irq_common_data - per irq data shared by all irqchips
134 * @state_use_accessors: status information for irq chip functions.
135 * Use accessor functions to deal with it
136 * @node: node index useful for balancing
137 * @handler_data: per-IRQ data for the irq_chip methods
138 * @affinity: IRQ affinity on SMP. If this is an IPI
139 * related irq, then this is the mask of the
140 * CPUs to which an IPI can be sent.
141 * @effective_affinity: The effective IRQ affinity on SMP as some irq
142 * chips do not allow multi CPU destinations.
143 * A subset of @affinity.
144 * @msi_desc: MSI descriptor
145 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
147 struct irq_common_data
{
148 unsigned int __private state_use_accessors
;
153 struct msi_desc
*msi_desc
;
154 cpumask_var_t affinity
;
155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
156 cpumask_var_t effective_affinity
;
158 #ifdef CONFIG_GENERIC_IRQ_IPI
159 unsigned int ipi_offset
;
164 * struct irq_data - per irq chip data passed down to chip functions
165 * @mask: precomputed bitmask for accessing the chip registers
166 * @irq: interrupt number
167 * @hwirq: hardware interrupt number, local to the interrupt domain
168 * @common: point to data shared by all irqchips
169 * @chip: low level interrupt hardware access
170 * @domain: Interrupt translation domain; responsible for mapping
171 * between hwirq number and linux irq number.
172 * @parent_data: pointer to parent struct irq_data to support hierarchy
174 * @chip_data: platform-specific per-chip private data for the chip
175 * methods, to allow shared chip implementations
181 struct irq_common_data
*common
;
182 struct irq_chip
*chip
;
183 struct irq_domain
*domain
;
184 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
185 struct irq_data
*parent_data
;
191 * Bit masks for irq_common_data.state_use_accessors
193 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
194 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
195 * IRQD_ACTIVATED - Interrupt has already been activated
196 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
197 * IRQD_PER_CPU - Interrupt is per cpu
198 * IRQD_AFFINITY_SET - Interrupt affinity was set
199 * IRQD_LEVEL - Interrupt is level triggered
200 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
202 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
204 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
205 * IRQD_IRQ_MASKED - Masked state of the interrupt
206 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
207 * IRQD_WAKEUP_ARMED - Wakeup mode armed
208 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
209 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
210 * IRQD_IRQ_STARTED - Startup state of the interrupt
211 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
212 * mask. Applies only to affinity managed irqs.
213 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
214 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
215 * IRQD_CAN_RESERVE - Can use reservation mode
216 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
218 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
219 * from actual interrupt context.
220 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
221 * irq_chip::irq_set_affinity() when deactivated.
222 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
223 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
226 IRQD_TRIGGER_MASK
= 0xf,
227 IRQD_SETAFFINITY_PENDING
= (1 << 8),
228 IRQD_ACTIVATED
= (1 << 9),
229 IRQD_NO_BALANCING
= (1 << 10),
230 IRQD_PER_CPU
= (1 << 11),
231 IRQD_AFFINITY_SET
= (1 << 12),
232 IRQD_LEVEL
= (1 << 13),
233 IRQD_WAKEUP_STATE
= (1 << 14),
234 IRQD_MOVE_PCNTXT
= (1 << 15),
235 IRQD_IRQ_DISABLED
= (1 << 16),
236 IRQD_IRQ_MASKED
= (1 << 17),
237 IRQD_IRQ_INPROGRESS
= (1 << 18),
238 IRQD_WAKEUP_ARMED
= (1 << 19),
239 IRQD_FORWARDED_TO_VCPU
= (1 << 20),
240 IRQD_AFFINITY_MANAGED
= (1 << 21),
241 IRQD_IRQ_STARTED
= (1 << 22),
242 IRQD_MANAGED_SHUTDOWN
= (1 << 23),
243 IRQD_SINGLE_TARGET
= (1 << 24),
244 IRQD_DEFAULT_TRIGGER_SET
= (1 << 25),
245 IRQD_CAN_RESERVE
= (1 << 26),
246 IRQD_MSI_NOMASK_QUIRK
= (1 << 27),
247 IRQD_HANDLE_ENFORCE_IRQCTX
= (1 << 28),
248 IRQD_AFFINITY_ON_ACTIVATE
= (1 << 29),
249 IRQD_IRQ_ENABLED_ON_SUSPEND
= (1 << 30),
252 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
254 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
256 return __irqd_to_state(d
) & IRQD_SETAFFINITY_PENDING
;
259 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
261 return __irqd_to_state(d
) & IRQD_PER_CPU
;
264 static inline bool irqd_can_balance(struct irq_data
*d
)
266 return !(__irqd_to_state(d
) & (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
269 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
271 return __irqd_to_state(d
) & IRQD_AFFINITY_SET
;
274 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
276 __irqd_to_state(d
) |= IRQD_AFFINITY_SET
;
279 static inline bool irqd_trigger_type_was_set(struct irq_data
*d
)
281 return __irqd_to_state(d
) & IRQD_DEFAULT_TRIGGER_SET
;
284 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
286 return __irqd_to_state(d
) & IRQD_TRIGGER_MASK
;
290 * Must only be called inside irq_chip.irq_set_type() functions or
291 * from the DT/ACPI setup code.
293 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
295 __irqd_to_state(d
) &= ~IRQD_TRIGGER_MASK
;
296 __irqd_to_state(d
) |= type
& IRQD_TRIGGER_MASK
;
297 __irqd_to_state(d
) |= IRQD_DEFAULT_TRIGGER_SET
;
300 static inline bool irqd_is_level_type(struct irq_data
*d
)
302 return __irqd_to_state(d
) & IRQD_LEVEL
;
306 * Must only be called of irqchip.irq_set_affinity() or low level
307 * hierarchy domain allocation functions.
309 static inline void irqd_set_single_target(struct irq_data
*d
)
311 __irqd_to_state(d
) |= IRQD_SINGLE_TARGET
;
314 static inline bool irqd_is_single_target(struct irq_data
*d
)
316 return __irqd_to_state(d
) & IRQD_SINGLE_TARGET
;
319 static inline void irqd_set_handle_enforce_irqctx(struct irq_data
*d
)
321 __irqd_to_state(d
) |= IRQD_HANDLE_ENFORCE_IRQCTX
;
324 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data
*d
)
326 return __irqd_to_state(d
) & IRQD_HANDLE_ENFORCE_IRQCTX
;
329 static inline bool irqd_is_enabled_on_suspend(struct irq_data
*d
)
331 return __irqd_to_state(d
) & IRQD_IRQ_ENABLED_ON_SUSPEND
;
334 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
336 return __irqd_to_state(d
) & IRQD_WAKEUP_STATE
;
339 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
341 return __irqd_to_state(d
) & IRQD_MOVE_PCNTXT
;
344 static inline bool irqd_irq_disabled(struct irq_data
*d
)
346 return __irqd_to_state(d
) & IRQD_IRQ_DISABLED
;
349 static inline bool irqd_irq_masked(struct irq_data
*d
)
351 return __irqd_to_state(d
) & IRQD_IRQ_MASKED
;
354 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
356 return __irqd_to_state(d
) & IRQD_IRQ_INPROGRESS
;
359 static inline bool irqd_is_wakeup_armed(struct irq_data
*d
)
361 return __irqd_to_state(d
) & IRQD_WAKEUP_ARMED
;
364 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data
*d
)
366 return __irqd_to_state(d
) & IRQD_FORWARDED_TO_VCPU
;
369 static inline void irqd_set_forwarded_to_vcpu(struct irq_data
*d
)
371 __irqd_to_state(d
) |= IRQD_FORWARDED_TO_VCPU
;
374 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data
*d
)
376 __irqd_to_state(d
) &= ~IRQD_FORWARDED_TO_VCPU
;
379 static inline bool irqd_affinity_is_managed(struct irq_data
*d
)
381 return __irqd_to_state(d
) & IRQD_AFFINITY_MANAGED
;
384 static inline bool irqd_is_activated(struct irq_data
*d
)
386 return __irqd_to_state(d
) & IRQD_ACTIVATED
;
389 static inline void irqd_set_activated(struct irq_data
*d
)
391 __irqd_to_state(d
) |= IRQD_ACTIVATED
;
394 static inline void irqd_clr_activated(struct irq_data
*d
)
396 __irqd_to_state(d
) &= ~IRQD_ACTIVATED
;
399 static inline bool irqd_is_started(struct irq_data
*d
)
401 return __irqd_to_state(d
) & IRQD_IRQ_STARTED
;
404 static inline bool irqd_is_managed_and_shutdown(struct irq_data
*d
)
406 return __irqd_to_state(d
) & IRQD_MANAGED_SHUTDOWN
;
409 static inline void irqd_set_can_reserve(struct irq_data
*d
)
411 __irqd_to_state(d
) |= IRQD_CAN_RESERVE
;
414 static inline void irqd_clr_can_reserve(struct irq_data
*d
)
416 __irqd_to_state(d
) &= ~IRQD_CAN_RESERVE
;
419 static inline bool irqd_can_reserve(struct irq_data
*d
)
421 return __irqd_to_state(d
) & IRQD_CAN_RESERVE
;
424 static inline void irqd_set_msi_nomask_quirk(struct irq_data
*d
)
426 __irqd_to_state(d
) |= IRQD_MSI_NOMASK_QUIRK
;
429 static inline void irqd_clr_msi_nomask_quirk(struct irq_data
*d
)
431 __irqd_to_state(d
) &= ~IRQD_MSI_NOMASK_QUIRK
;
434 static inline bool irqd_msi_nomask_quirk(struct irq_data
*d
)
436 return __irqd_to_state(d
) & IRQD_MSI_NOMASK_QUIRK
;
439 static inline void irqd_set_affinity_on_activate(struct irq_data
*d
)
441 __irqd_to_state(d
) |= IRQD_AFFINITY_ON_ACTIVATE
;
444 static inline bool irqd_affinity_on_activate(struct irq_data
*d
)
446 return __irqd_to_state(d
) & IRQD_AFFINITY_ON_ACTIVATE
;
449 #undef __irqd_to_state
451 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
457 * struct irq_chip - hardware interrupt chip descriptor
459 * @parent_device: pointer to parent device for irqchip
460 * @name: name for /proc/interrupts
461 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
462 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
463 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
464 * @irq_disable: disable the interrupt
465 * @irq_ack: start of a new interrupt
466 * @irq_mask: mask an interrupt source
467 * @irq_mask_ack: ack and mask an interrupt source
468 * @irq_unmask: unmask an interrupt source
469 * @irq_eoi: end of interrupt
470 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
471 * argument is true, it tells the driver to
472 * unconditionally apply the affinity setting. Sanity
473 * checks against the supplied affinity mask are not
474 * required. This is used for CPU hotplug where the
475 * target CPU is not yet set in the cpu_online_mask.
476 * @irq_retrigger: resend an IRQ to the CPU
477 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
478 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
479 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
480 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
481 * @irq_cpu_online: configure an interrupt source for a secondary CPU
482 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
483 * @irq_suspend: function called from core code on suspend once per
484 * chip, when one or more interrupts are installed
485 * @irq_resume: function called from core code on resume once per chip,
486 * when one ore more interrupts are installed
487 * @irq_pm_shutdown: function called from core code on shutdown once per chip
488 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
489 * @irq_print_chip: optional to print special chip info in show_interrupts
490 * @irq_request_resources: optional to request resources before calling
491 * any other callback related to this irq
492 * @irq_release_resources: optional to release resources acquired with
493 * irq_request_resources
494 * @irq_compose_msi_msg: optional to compose message content for MSI
495 * @irq_write_msi_msg: optional to write message content for MSI
496 * @irq_get_irqchip_state: return the internal state of an interrupt
497 * @irq_set_irqchip_state: set the internal state of a interrupt
498 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
499 * @ipi_send_single: send a single IPI to destination cpus
500 * @ipi_send_mask: send an IPI to destination cpus in cpumask
501 * @irq_nmi_setup: function called from core code before enabling an NMI
502 * @irq_nmi_teardown: function called from core code after disabling an NMI
503 * @flags: chip specific flags
506 struct device
*parent_device
;
508 unsigned int (*irq_startup
)(struct irq_data
*data
);
509 void (*irq_shutdown
)(struct irq_data
*data
);
510 void (*irq_enable
)(struct irq_data
*data
);
511 void (*irq_disable
)(struct irq_data
*data
);
513 void (*irq_ack
)(struct irq_data
*data
);
514 void (*irq_mask
)(struct irq_data
*data
);
515 void (*irq_mask_ack
)(struct irq_data
*data
);
516 void (*irq_unmask
)(struct irq_data
*data
);
517 void (*irq_eoi
)(struct irq_data
*data
);
519 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
520 int (*irq_retrigger
)(struct irq_data
*data
);
521 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
522 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
524 void (*irq_bus_lock
)(struct irq_data
*data
);
525 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
527 void (*irq_cpu_online
)(struct irq_data
*data
);
528 void (*irq_cpu_offline
)(struct irq_data
*data
);
530 void (*irq_suspend
)(struct irq_data
*data
);
531 void (*irq_resume
)(struct irq_data
*data
);
532 void (*irq_pm_shutdown
)(struct irq_data
*data
);
534 void (*irq_calc_mask
)(struct irq_data
*data
);
536 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
537 int (*irq_request_resources
)(struct irq_data
*data
);
538 void (*irq_release_resources
)(struct irq_data
*data
);
540 void (*irq_compose_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
541 void (*irq_write_msi_msg
)(struct irq_data
*data
, struct msi_msg
*msg
);
543 int (*irq_get_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool *state
);
544 int (*irq_set_irqchip_state
)(struct irq_data
*data
, enum irqchip_irq_state which
, bool state
);
546 int (*irq_set_vcpu_affinity
)(struct irq_data
*data
, void *vcpu_info
);
548 void (*ipi_send_single
)(struct irq_data
*data
, unsigned int cpu
);
549 void (*ipi_send_mask
)(struct irq_data
*data
, const struct cpumask
*dest
);
551 int (*irq_nmi_setup
)(struct irq_data
*data
);
552 void (*irq_nmi_teardown
)(struct irq_data
*data
);
558 * irq_chip specific flags
560 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
561 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
562 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
563 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
565 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
566 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
567 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
568 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
569 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
570 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
571 * in the suspend path if they are in disabled state
572 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
575 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
576 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
577 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
578 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
579 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
580 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
581 IRQCHIP_EOI_THREADED
= (1 << 6),
582 IRQCHIP_SUPPORTS_LEVEL_MSI
= (1 << 7),
583 IRQCHIP_SUPPORTS_NMI
= (1 << 8),
584 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND
= (1 << 9),
585 IRQCHIP_AFFINITY_PRE_STARTUP
= (1 << 10),
588 #include <linux/irqdesc.h>
591 * Pick up the arch-dependent methods:
593 #include <asm/hw_irq.h>
595 #ifndef NR_IRQS_LEGACY
596 # define NR_IRQS_LEGACY 0
599 #ifndef ARCH_IRQ_INIT_FLAGS
600 # define ARCH_IRQ_INIT_FLAGS 0
603 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
606 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
607 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
609 extern void irq_cpu_online(void);
610 extern void irq_cpu_offline(void);
611 extern int irq_set_affinity_locked(struct irq_data
*data
,
612 const struct cpumask
*cpumask
, bool force
);
613 extern int irq_set_vcpu_affinity(unsigned int irq
, void *vcpu_info
);
615 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
616 extern void irq_migrate_all_off_this_cpu(void);
617 extern int irq_affinity_online_cpu(unsigned int cpu
);
619 # define irq_affinity_online_cpu NULL
622 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
623 void __irq_move_irq(struct irq_data
*data
);
624 static inline void irq_move_irq(struct irq_data
*data
)
626 if (unlikely(irqd_is_setaffinity_pending(data
)))
627 __irq_move_irq(data
);
629 void irq_move_masked_irq(struct irq_data
*data
);
630 void irq_force_complete_move(struct irq_desc
*desc
);
632 static inline void irq_move_irq(struct irq_data
*data
) { }
633 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
634 static inline void irq_force_complete_move(struct irq_desc
*desc
) { }
637 extern int no_irq_affinity
;
639 #ifdef CONFIG_HARDIRQS_SW_RESEND
640 int irq_set_parent(int irq
, int parent_irq
);
642 static inline int irq_set_parent(int irq
, int parent_irq
)
649 * Built-in IRQ handlers for various IRQ types,
650 * callable via desc->handle_irq()
652 extern void handle_level_irq(struct irq_desc
*desc
);
653 extern void handle_fasteoi_irq(struct irq_desc
*desc
);
654 extern void handle_edge_irq(struct irq_desc
*desc
);
655 extern void handle_edge_eoi_irq(struct irq_desc
*desc
);
656 extern void handle_simple_irq(struct irq_desc
*desc
);
657 extern void handle_untracked_irq(struct irq_desc
*desc
);
658 extern void handle_percpu_irq(struct irq_desc
*desc
);
659 extern void handle_percpu_devid_irq(struct irq_desc
*desc
);
660 extern void handle_bad_irq(struct irq_desc
*desc
);
661 extern void handle_nested_irq(unsigned int irq
);
663 extern void handle_fasteoi_nmi(struct irq_desc
*desc
);
664 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc
*desc
);
666 extern int irq_chip_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
);
667 extern int irq_chip_pm_get(struct irq_data
*data
);
668 extern int irq_chip_pm_put(struct irq_data
*data
);
669 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
670 extern void handle_fasteoi_ack_irq(struct irq_desc
*desc
);
671 extern void handle_fasteoi_mask_irq(struct irq_desc
*desc
);
672 extern int irq_chip_set_parent_state(struct irq_data
*data
,
673 enum irqchip_irq_state which
,
675 extern int irq_chip_get_parent_state(struct irq_data
*data
,
676 enum irqchip_irq_state which
,
678 extern void irq_chip_enable_parent(struct irq_data
*data
);
679 extern void irq_chip_disable_parent(struct irq_data
*data
);
680 extern void irq_chip_ack_parent(struct irq_data
*data
);
681 extern int irq_chip_retrigger_hierarchy(struct irq_data
*data
);
682 extern void irq_chip_mask_parent(struct irq_data
*data
);
683 extern void irq_chip_mask_ack_parent(struct irq_data
*data
);
684 extern void irq_chip_unmask_parent(struct irq_data
*data
);
685 extern void irq_chip_eoi_parent(struct irq_data
*data
);
686 extern int irq_chip_set_affinity_parent(struct irq_data
*data
,
687 const struct cpumask
*dest
,
689 extern int irq_chip_set_wake_parent(struct irq_data
*data
, unsigned int on
);
690 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data
*data
,
692 extern int irq_chip_set_type_parent(struct irq_data
*data
, unsigned int type
);
693 extern int irq_chip_request_resources_parent(struct irq_data
*data
);
694 extern void irq_chip_release_resources_parent(struct irq_data
*data
);
697 /* Handling of unhandled and spurious interrupts: */
698 extern void note_interrupt(struct irq_desc
*desc
, irqreturn_t action_ret
);
701 /* Enable/disable irq debugging output: */
702 extern int noirqdebug_setup(char *str
);
704 /* Checks whether the interrupt can be requested by request_irq(): */
705 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
707 /* Dummy irq-chip implementations: */
708 extern struct irq_chip no_irq_chip
;
709 extern struct irq_chip dummy_irq_chip
;
712 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
713 irq_flow_handler_t handle
, const char *name
);
715 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
716 irq_flow_handler_t handle
)
718 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
721 extern int irq_set_percpu_devid(unsigned int irq
);
722 extern int irq_set_percpu_devid_partition(unsigned int irq
,
723 const struct cpumask
*affinity
);
724 extern int irq_get_percpu_devid_partition(unsigned int irq
,
725 struct cpumask
*affinity
);
728 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
732 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
734 __irq_set_handler(irq
, handle
, 0, NULL
);
738 * Set a highlevel chained flow handler for a given IRQ.
739 * (a chained handler is automatically enabled and set to
740 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
743 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
745 __irq_set_handler(irq
, handle
, 1, NULL
);
749 * Set a highlevel chained flow handler and its data for a given IRQ.
750 * (a chained handler is automatically enabled and set to
751 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
754 irq_set_chained_handler_and_data(unsigned int irq
, irq_flow_handler_t handle
,
757 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
759 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
761 irq_modify_status(irq
, 0, set
);
764 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
766 irq_modify_status(irq
, clr
, 0);
769 static inline void irq_set_noprobe(unsigned int irq
)
771 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
774 static inline void irq_set_probe(unsigned int irq
)
776 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
779 static inline void irq_set_nothread(unsigned int irq
)
781 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
784 static inline void irq_set_thread(unsigned int irq
)
786 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
789 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
792 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
794 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
797 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
799 irq_set_status_flags(irq
,
800 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
801 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
804 /* Set/get chip/data for an IRQ: */
805 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
806 extern int irq_set_handler_data(unsigned int irq
, void *data
);
807 extern int irq_set_chip_data(unsigned int irq
, void *data
);
808 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
809 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
810 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
811 struct msi_desc
*entry
);
812 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
814 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
816 struct irq_data
*d
= irq_get_irq_data(irq
);
817 return d
? d
->chip
: NULL
;
820 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
825 static inline void *irq_get_chip_data(unsigned int irq
)
827 struct irq_data
*d
= irq_get_irq_data(irq
);
828 return d
? d
->chip_data
: NULL
;
831 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
836 static inline void *irq_get_handler_data(unsigned int irq
)
838 struct irq_data
*d
= irq_get_irq_data(irq
);
839 return d
? d
->common
->handler_data
: NULL
;
842 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
844 return d
->common
->handler_data
;
847 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
849 struct irq_data
*d
= irq_get_irq_data(irq
);
850 return d
? d
->common
->msi_desc
: NULL
;
853 static inline struct msi_desc
*irq_data_get_msi_desc(struct irq_data
*d
)
855 return d
->common
->msi_desc
;
858 static inline u32
irq_get_trigger_type(unsigned int irq
)
860 struct irq_data
*d
= irq_get_irq_data(irq
);
861 return d
? irqd_get_trigger_type(d
) : 0;
864 static inline int irq_common_data_get_node(struct irq_common_data
*d
)
873 static inline int irq_data_get_node(struct irq_data
*d
)
875 return irq_common_data_get_node(d
->common
);
878 static inline struct cpumask
*irq_get_affinity_mask(int irq
)
880 struct irq_data
*d
= irq_get_irq_data(irq
);
882 return d
? d
->common
->affinity
: NULL
;
885 static inline struct cpumask
*irq_data_get_affinity_mask(struct irq_data
*d
)
887 return d
->common
->affinity
;
890 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
892 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
894 return d
->common
->effective_affinity
;
896 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
897 const struct cpumask
*m
)
899 cpumask_copy(d
->common
->effective_affinity
, m
);
902 static inline void irq_data_update_effective_affinity(struct irq_data
*d
,
903 const struct cpumask
*m
)
907 struct cpumask
*irq_data_get_effective_affinity_mask(struct irq_data
*d
)
909 return d
->common
->affinity
;
913 static inline struct cpumask
*irq_get_effective_affinity_mask(unsigned int irq
)
915 struct irq_data
*d
= irq_get_irq_data(irq
);
917 return d
? irq_data_get_effective_affinity_mask(d
) : NULL
;
920 unsigned int arch_dynirq_lower_bound(unsigned int from
);
922 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
923 struct module
*owner
,
924 const struct irq_affinity_desc
*affinity
);
926 int __devm_irq_alloc_descs(struct device
*dev
, int irq
, unsigned int from
,
927 unsigned int cnt
, int node
, struct module
*owner
,
928 const struct irq_affinity_desc
*affinity
);
930 /* use macros to avoid needing export.h for THIS_MODULE */
931 #define irq_alloc_descs(irq, from, cnt, node) \
932 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
934 #define irq_alloc_desc(node) \
935 irq_alloc_descs(-1, 1, 1, node)
937 #define irq_alloc_desc_at(at, node) \
938 irq_alloc_descs(at, at, 1, node)
940 #define irq_alloc_desc_from(from, node) \
941 irq_alloc_descs(-1, from, 1, node)
943 #define irq_alloc_descs_from(from, cnt, node) \
944 irq_alloc_descs(-1, from, cnt, node)
946 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
947 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
949 #define devm_irq_alloc_desc(dev, node) \
950 devm_irq_alloc_descs(dev, -1, 1, 1, node)
952 #define devm_irq_alloc_desc_at(dev, at, node) \
953 devm_irq_alloc_descs(dev, at, at, 1, node)
955 #define devm_irq_alloc_desc_from(dev, from, node) \
956 devm_irq_alloc_descs(dev, -1, from, 1, node)
958 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
959 devm_irq_alloc_descs(dev, -1, from, cnt, node)
961 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
962 static inline void irq_free_desc(unsigned int irq
)
964 irq_free_descs(irq
, 1);
967 #ifdef CONFIG_GENERIC_IRQ_LEGACY
968 void irq_init_desc(unsigned int irq
);
972 * struct irq_chip_regs - register offsets for struct irq_gci
973 * @enable: Enable register offset to reg_base
974 * @disable: Disable register offset to reg_base
975 * @mask: Mask register offset to reg_base
976 * @ack: Ack register offset to reg_base
977 * @eoi: Eoi register offset to reg_base
978 * @type: Type configuration register offset to reg_base
979 * @polarity: Polarity configuration register offset to reg_base
981 struct irq_chip_regs
{
982 unsigned long enable
;
983 unsigned long disable
;
988 unsigned long polarity
;
992 * struct irq_chip_type - Generic interrupt chip instance for a flow type
993 * @chip: The real interrupt chip which provides the callbacks
994 * @regs: Register offsets for this chip
995 * @handler: Flow handler associated with this chip
996 * @type: Chip can handle these flow types
997 * @mask_cache_priv: Cached mask register private to the chip type
998 * @mask_cache: Pointer to cached mask register
1000 * A irq_generic_chip can have several instances of irq_chip_type when
1001 * it requires different functions and register offsets for different
1004 struct irq_chip_type
{
1005 struct irq_chip chip
;
1006 struct irq_chip_regs regs
;
1007 irq_flow_handler_t handler
;
1009 u32 mask_cache_priv
;
1014 * struct irq_chip_generic - Generic irq chip data structure
1015 * @lock: Lock to protect register and cache data access
1016 * @reg_base: Register base address (virtual)
1017 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
1018 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
1019 * @suspend: Function called from core code on suspend once per
1020 * chip; can be useful instead of irq_chip::suspend to
1021 * handle chip details even when no interrupts are in use
1022 * @resume: Function called from core code on resume once per chip;
1023 * can be useful instead of irq_chip::suspend to handle
1024 * chip details even when no interrupts are in use
1025 * @irq_base: Interrupt base nr for this chip
1026 * @irq_cnt: Number of interrupts handled by this chip
1027 * @mask_cache: Cached mask register shared between all chip types
1028 * @type_cache: Cached type register
1029 * @polarity_cache: Cached polarity register
1030 * @wake_enabled: Interrupt can wakeup from suspend
1031 * @wake_active: Interrupt is marked as an wakeup from suspend source
1032 * @num_ct: Number of available irq_chip_type instances (usually 1)
1033 * @private: Private data for non generic chip callbacks
1034 * @installed: bitfield to denote installed interrupts
1035 * @unused: bitfield to denote unused interrupts
1036 * @domain: irq domain pointer
1037 * @list: List head for keeping track of instances
1038 * @chip_types: Array of interrupt irq_chip_types
1040 * Note, that irq_chip_generic can have multiple irq_chip_type
1041 * implementations which can be associated to a particular irq line of
1042 * an irq_chip_generic instance. That allows to share and protect
1043 * state in an irq_chip_generic instance when we need to implement
1044 * different flow mechanisms (level/edge) for it.
1046 struct irq_chip_generic
{
1047 raw_spinlock_t lock
;
1048 void __iomem
*reg_base
;
1049 u32 (*reg_readl
)(void __iomem
*addr
);
1050 void (*reg_writel
)(u32 val
, void __iomem
*addr
);
1051 void (*suspend
)(struct irq_chip_generic
*gc
);
1052 void (*resume
)(struct irq_chip_generic
*gc
);
1053 unsigned int irq_base
;
1054 unsigned int irq_cnt
;
1060 unsigned int num_ct
;
1062 unsigned long installed
;
1063 unsigned long unused
;
1064 struct irq_domain
*domain
;
1065 struct list_head list
;
1066 struct irq_chip_type chip_types
[];
1070 * enum irq_gc_flags - Initialization flags for generic irq chips
1071 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1072 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1073 * irq chips which need to call irq_set_wake() on
1074 * the parent irq. Usually GPIO implementations
1075 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1076 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1077 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1080 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
1081 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
1082 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
1083 IRQ_GC_NO_MASK
= 1 << 3,
1084 IRQ_GC_BE_IO
= 1 << 4,
1088 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1089 * @irqs_per_chip: Number of interrupts per chip
1090 * @num_chips: Number of chips
1091 * @irq_flags_to_set: IRQ* flags to set on irq setup
1092 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1093 * @gc_flags: Generic chip specific setup flags
1094 * @gc: Array of pointers to generic interrupt chips
1096 struct irq_domain_chip_generic
{
1097 unsigned int irqs_per_chip
;
1098 unsigned int num_chips
;
1099 unsigned int irq_flags_to_clear
;
1100 unsigned int irq_flags_to_set
;
1101 enum irq_gc_flags gc_flags
;
1102 struct irq_chip_generic
*gc
[];
1105 /* Generic chip callback functions */
1106 void irq_gc_noop(struct irq_data
*d
);
1107 void irq_gc_mask_disable_reg(struct irq_data
*d
);
1108 void irq_gc_mask_set_bit(struct irq_data
*d
);
1109 void irq_gc_mask_clr_bit(struct irq_data
*d
);
1110 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
1111 void irq_gc_ack_set_bit(struct irq_data
*d
);
1112 void irq_gc_ack_clr_bit(struct irq_data
*d
);
1113 void irq_gc_mask_disable_and_ack_set(struct irq_data
*d
);
1114 void irq_gc_eoi(struct irq_data
*d
);
1115 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
1117 /* Setup functions for irq_chip_generic */
1118 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
1119 irq_hw_number_t hw_irq
);
1120 struct irq_chip_generic
*
1121 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
1122 void __iomem
*reg_base
, irq_flow_handler_t handler
);
1123 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1124 enum irq_gc_flags flags
, unsigned int clr
,
1126 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
1127 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
1128 unsigned int clr
, unsigned int set
);
1130 struct irq_chip_generic
*
1131 devm_irq_alloc_generic_chip(struct device
*dev
, const char *name
, int num_ct
,
1132 unsigned int irq_base
, void __iomem
*reg_base
,
1133 irq_flow_handler_t handler
);
1134 int devm_irq_setup_generic_chip(struct device
*dev
, struct irq_chip_generic
*gc
,
1135 u32 msk
, enum irq_gc_flags flags
,
1136 unsigned int clr
, unsigned int set
);
1138 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
1140 int __irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
1141 int num_ct
, const char *name
,
1142 irq_flow_handler_t handler
,
1143 unsigned int clr
, unsigned int set
,
1144 enum irq_gc_flags flags
);
1146 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1147 handler, clr, set, flags) \
1149 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1150 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1151 handler, clr, set, flags); \
1154 static inline void irq_free_generic_chip(struct irq_chip_generic
*gc
)
1159 static inline void irq_destroy_generic_chip(struct irq_chip_generic
*gc
,
1160 u32 msk
, unsigned int clr
,
1163 irq_remove_generic_chip(gc
, msk
, clr
, set
);
1164 irq_free_generic_chip(gc
);
1167 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
1169 return container_of(d
->chip
, struct irq_chip_type
, chip
);
1172 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1175 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
1177 raw_spin_lock(&gc
->lock
);
1180 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
1182 raw_spin_unlock(&gc
->lock
);
1185 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
1186 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
1190 * The irqsave variants are for usage in non interrupt code. Do not use
1191 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1193 #define irq_gc_lock_irqsave(gc, flags) \
1194 raw_spin_lock_irqsave(&(gc)->lock, flags)
1196 #define irq_gc_unlock_irqrestore(gc, flags) \
1197 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1199 static inline void irq_reg_writel(struct irq_chip_generic
*gc
,
1200 u32 val
, int reg_offset
)
1203 gc
->reg_writel(val
, gc
->reg_base
+ reg_offset
);
1205 writel(val
, gc
->reg_base
+ reg_offset
);
1208 static inline u32
irq_reg_readl(struct irq_chip_generic
*gc
,
1212 return gc
->reg_readl(gc
->reg_base
+ reg_offset
);
1214 return readl(gc
->reg_base
+ reg_offset
);
1218 struct irq_matrix
*irq_alloc_matrix(unsigned int matrix_bits
,
1219 unsigned int alloc_start
,
1220 unsigned int alloc_end
);
1221 void irq_matrix_online(struct irq_matrix
*m
);
1222 void irq_matrix_offline(struct irq_matrix
*m
);
1223 void irq_matrix_assign_system(struct irq_matrix
*m
, unsigned int bit
, bool replace
);
1224 int irq_matrix_reserve_managed(struct irq_matrix
*m
, const struct cpumask
*msk
);
1225 void irq_matrix_remove_managed(struct irq_matrix
*m
, const struct cpumask
*msk
);
1226 int irq_matrix_alloc_managed(struct irq_matrix
*m
, const struct cpumask
*msk
,
1227 unsigned int *mapped_cpu
);
1228 void irq_matrix_reserve(struct irq_matrix
*m
);
1229 void irq_matrix_remove_reserved(struct irq_matrix
*m
);
1230 int irq_matrix_alloc(struct irq_matrix
*m
, const struct cpumask
*msk
,
1231 bool reserved
, unsigned int *mapped_cpu
);
1232 void irq_matrix_free(struct irq_matrix
*m
, unsigned int cpu
,
1233 unsigned int bit
, bool managed
);
1234 void irq_matrix_assign(struct irq_matrix
*m
, unsigned int bit
);
1235 unsigned int irq_matrix_available(struct irq_matrix
*m
, bool cpudown
);
1236 unsigned int irq_matrix_allocated(struct irq_matrix
*m
);
1237 unsigned int irq_matrix_reserved(struct irq_matrix
*m
);
1238 void irq_matrix_debug_show(struct seq_file
*sf
, struct irq_matrix
*m
, int ind
);
1240 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1241 #define INVALID_HWIRQ (~0UL)
1242 irq_hw_number_t
ipi_get_hwirq(unsigned int irq
, unsigned int cpu
);
1243 int __ipi_send_single(struct irq_desc
*desc
, unsigned int cpu
);
1244 int __ipi_send_mask(struct irq_desc
*desc
, const struct cpumask
*dest
);
1245 int ipi_send_single(unsigned int virq
, unsigned int cpu
);
1246 int ipi_send_mask(unsigned int virq
, const struct cpumask
*dest
);
1248 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1250 * Registers a generic IRQ handling function as the top-level IRQ handler in
1251 * the system, which is generally the first C code called from an assembly
1252 * architecture-specific interrupt handler.
1254 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1257 int __init
set_handle_irq(void (*handle_irq
)(struct pt_regs
*));
1260 * Allows interrupt handlers to find the irqchip that's been registered as the
1261 * top-level IRQ handler.
1263 extern void (*handle_arch_irq
)(struct pt_regs
*) __ro_after_init
;
1265 #ifndef set_handle_irq
1266 #define set_handle_irq(handle_irq) \
1274 #endif /* _LINUX_IRQ_H */