]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - include/linux/irqchip/arm-gic-v3.h
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
22 * Distributor registers. We assume we're running non-secure, with ARE
23 * being set. Secure-only and non-ARE registers are not described.
25 #define GICD_CTLR 0x0000
26 #define GICD_TYPER 0x0004
27 #define GICD_IIDR 0x0008
28 #define GICD_STATUSR 0x0010
29 #define GICD_SETSPI_NSR 0x0040
30 #define GICD_CLRSPI_NSR 0x0048
31 #define GICD_SETSPI_SR 0x0050
32 #define GICD_CLRSPI_SR 0x0058
33 #define GICD_SEIR 0x0068
34 #define GICD_IGROUPR 0x0080
35 #define GICD_ISENABLER 0x0100
36 #define GICD_ICENABLER 0x0180
37 #define GICD_ISPENDR 0x0200
38 #define GICD_ICPENDR 0x0280
39 #define GICD_ISACTIVER 0x0300
40 #define GICD_ICACTIVER 0x0380
41 #define GICD_IPRIORITYR 0x0400
42 #define GICD_ICFGR 0x0C00
43 #define GICD_IGRPMODR 0x0D00
44 #define GICD_NSACR 0x0E00
45 #define GICD_IROUTER 0x6000
46 #define GICD_IDREGS 0xFFD0
47 #define GICD_PIDR2 0xFFE8
50 * Those registers are actually from GICv2, but the spec demands that they
51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
53 #define GICD_ITARGETSR 0x0800
54 #define GICD_SGIR 0x0F00
55 #define GICD_CPENDSGIR 0x0F10
56 #define GICD_SPENDSGIR 0x0F20
58 #define GICD_CTLR_RWP (1U << 31)
59 #define GICD_CTLR_DS (1U << 6)
60 #define GICD_CTLR_ARE_NS (1U << 4)
61 #define GICD_CTLR_ENABLE_G1A (1U << 1)
62 #define GICD_CTLR_ENABLE_G1 (1U << 0)
65 * In systems with a single security state (what we emulate in KVM)
66 * the meaning of the interrupt group enable bits is slightly different
68 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
69 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
71 #define GICD_TYPER_LPIS (1U << 17)
72 #define GICD_TYPER_MBIS (1U << 16)
74 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
75 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
77 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
78 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
80 #define GIC_PIDR2_ARCH_MASK 0xf0
81 #define GIC_PIDR2_ARCH_GICv3 0x30
82 #define GIC_PIDR2_ARCH_GICv4 0x40
84 #define GIC_V3_DIST_SIZE 0x10000
87 * Re-Distributor registers, offsets from RD_base
89 #define GICR_CTLR GICD_CTLR
90 #define GICR_IIDR 0x0004
91 #define GICR_TYPER 0x0008
92 #define GICR_STATUSR GICD_STATUSR
93 #define GICR_WAKER 0x0014
94 #define GICR_SETLPIR 0x0040
95 #define GICR_CLRLPIR 0x0048
96 #define GICR_SEIR GICD_SEIR
97 #define GICR_PROPBASER 0x0070
98 #define GICR_PENDBASER 0x0078
99 #define GICR_INVLPIR 0x00A0
100 #define GICR_INVALLR 0x00B0
101 #define GICR_SYNCR 0x00C0
102 #define GICR_MOVLPIR 0x0100
103 #define GICR_MOVALLR 0x0110
104 #define GICR_IDREGS GICD_IDREGS
105 #define GICR_PIDR2 GICD_PIDR2
107 #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
109 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
111 #define GICR_WAKER_ProcessorSleep (1U << 1)
112 #define GICR_WAKER_ChildrenAsleep (1U << 2)
114 #define GIC_BASER_CACHE_nCnB 0ULL
115 #define GIC_BASER_CACHE_SameAsInner 0ULL
116 #define GIC_BASER_CACHE_nC 1ULL
117 #define GIC_BASER_CACHE_RaWt 2ULL
118 #define GIC_BASER_CACHE_RaWb 3ULL
119 #define GIC_BASER_CACHE_WaWt 4ULL
120 #define GIC_BASER_CACHE_WaWb 5ULL
121 #define GIC_BASER_CACHE_RaWaWt 6ULL
122 #define GIC_BASER_CACHE_RaWaWb 7ULL
123 #define GIC_BASER_CACHE_MASK 7ULL
124 #define GIC_BASER_NonShareable 0ULL
125 #define GIC_BASER_InnerShareable 1ULL
126 #define GIC_BASER_OuterShareable 2ULL
127 #define GIC_BASER_SHAREABILITY_MASK 3ULL
129 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
130 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
132 #define GIC_BASER_SHAREABILITY(reg, type) \
133 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
135 /* encode a size field of width @w containing @n - 1 units */
136 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
138 #define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
139 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
140 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
141 #define GICR_PROPBASER_SHAREABILITY_MASK \
142 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
143 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
144 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
145 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
146 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
147 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
149 #define GICR_PROPBASER_InnerShareable \
150 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
152 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
153 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
154 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
155 #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
156 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
157 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
158 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
159 #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
161 #define GICR_PROPBASER_IDBITS_MASK (0x1f)
162 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
163 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
165 #define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
166 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
167 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
168 #define GICR_PENDBASER_SHAREABILITY_MASK \
169 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
170 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
171 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
172 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
173 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
174 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
176 #define GICR_PENDBASER_InnerShareable \
177 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
179 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
180 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
181 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
182 #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
183 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
184 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
185 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
186 #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
188 #define GICR_PENDBASER_PTZ BIT_ULL(62)
191 * Re-Distributor registers, offsets from SGI_base
193 #define GICR_IGROUPR0 GICD_IGROUPR
194 #define GICR_ISENABLER0 GICD_ISENABLER
195 #define GICR_ICENABLER0 GICD_ICENABLER
196 #define GICR_ISPENDR0 GICD_ISPENDR
197 #define GICR_ICPENDR0 GICD_ICPENDR
198 #define GICR_ISACTIVER0 GICD_ISACTIVER
199 #define GICR_ICACTIVER0 GICD_ICACTIVER
200 #define GICR_IPRIORITYR0 GICD_IPRIORITYR
201 #define GICR_ICFGR0 GICD_ICFGR
202 #define GICR_IGRPMODR0 GICD_IGRPMODR
203 #define GICR_NSACR GICD_NSACR
205 #define GICR_TYPER_PLPIS (1U << 0)
206 #define GICR_TYPER_VLPIS (1U << 1)
207 #define GICR_TYPER_LAST (1U << 4)
209 #define GIC_V3_REDIST_SIZE 0x20000
211 #define LPI_PROP_GROUP1 (1 << 1)
212 #define LPI_PROP_ENABLED (1 << 0)
215 * ITS registers, offsets from ITS_base
217 #define GITS_CTLR 0x0000
218 #define GITS_IIDR 0x0004
219 #define GITS_TYPER 0x0008
220 #define GITS_CBASER 0x0080
221 #define GITS_CWRITER 0x0088
222 #define GITS_CREADR 0x0090
223 #define GITS_BASER 0x0100
224 #define GITS_IDREGS_BASE 0xffd0
225 #define GITS_PIDR0 0xffe0
226 #define GITS_PIDR1 0xffe4
227 #define GITS_PIDR2 GICR_PIDR2
228 #define GITS_PIDR4 0xffd0
229 #define GITS_CIDR0 0xfff0
230 #define GITS_CIDR1 0xfff4
231 #define GITS_CIDR2 0xfff8
232 #define GITS_CIDR3 0xfffc
234 #define GITS_TRANSLATER 0x10040
236 #define GITS_CTLR_ENABLE (1U << 0)
237 #define GITS_CTLR_QUIESCENT (1U << 31)
239 #define GITS_TYPER_PLPIS (1UL << 0)
240 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
241 #define GITS_TYPER_IDBITS_SHIFT 8
242 #define GITS_TYPER_DEVBITS_SHIFT 13
243 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
244 #define GITS_TYPER_PTA (1UL << 19)
245 #define GITS_TYPER_HWCOLLCNT_SHIFT 24
247 #define GITS_IIDR_REV_SHIFT 12
248 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
249 #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
250 #define GITS_IIDR_PRODUCTID_SHIFT 24
252 #define GITS_CBASER_VALID (1ULL << 63)
253 #define GITS_CBASER_SHAREABILITY_SHIFT (10)
254 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
255 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
256 #define GITS_CBASER_SHAREABILITY_MASK \
257 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
258 #define GITS_CBASER_INNER_CACHEABILITY_MASK \
259 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
260 #define GITS_CBASER_OUTER_CACHEABILITY_MASK \
261 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
262 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
264 #define GITS_CBASER_InnerShareable \
265 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
267 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
268 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
269 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
270 #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
271 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
272 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
273 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
274 #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
276 #define GITS_BASER_NR_REGS 8
278 #define GITS_BASER_VALID (1ULL << 63)
279 #define GITS_BASER_INDIRECT (1ULL << 62)
281 #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
282 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
283 #define GITS_BASER_INNER_CACHEABILITY_MASK \
284 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
285 #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
286 #define GITS_BASER_OUTER_CACHEABILITY_MASK \
287 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
288 #define GITS_BASER_SHAREABILITY_MASK \
289 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
291 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
292 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
293 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
294 #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
295 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
296 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
297 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
298 #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
300 #define GITS_BASER_TYPE_SHIFT (56)
301 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
302 #define GITS_BASER_ENTRY_SIZE_SHIFT (48)
303 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
304 #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
305 #define GITS_BASER_SHAREABILITY_SHIFT (10)
306 #define GITS_BASER_InnerShareable \
307 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
308 #define GITS_BASER_PAGE_SIZE_SHIFT (8)
309 #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
310 #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
311 #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
312 #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
313 #define GITS_BASER_PAGES_MAX 256
314 #define GITS_BASER_PAGES_SHIFT (0)
315 #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
317 #define GITS_BASER_TYPE_NONE 0
318 #define GITS_BASER_TYPE_DEVICE 1
319 #define GITS_BASER_TYPE_VCPU 2
320 #define GITS_BASER_TYPE_RESERVED3 3
321 #define GITS_BASER_TYPE_COLLECTION 4
322 #define GITS_BASER_TYPE_RESERVED5 5
323 #define GITS_BASER_TYPE_RESERVED6 6
324 #define GITS_BASER_TYPE_RESERVED7 7
326 #define GITS_LVL1_ENTRY_SIZE (8UL)
331 #define GITS_CMD_MAPD 0x08
332 #define GITS_CMD_MAPC 0x09
333 #define GITS_CMD_MAPTI 0x0a
334 #define GITS_CMD_MAPI 0x0b
335 #define GITS_CMD_MOVI 0x01
336 #define GITS_CMD_DISCARD 0x0f
337 #define GITS_CMD_INV 0x0c
338 #define GITS_CMD_MOVALL 0x0e
339 #define GITS_CMD_INVALL 0x0d
340 #define GITS_CMD_INT 0x03
341 #define GITS_CMD_CLEAR 0x04
342 #define GITS_CMD_SYNC 0x05
347 #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
348 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
349 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
350 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
351 #define E_ITS_MAPD_DEVICE_OOR 0x010801
352 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802
353 #define E_ITS_MAPC_PROCNUM_OOR 0x010902
354 #define E_ITS_MAPC_COLLECTION_OOR 0x010903
355 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
356 #define E_ITS_MAPTI_ID_OOR 0x010a05
357 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
358 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
359 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
360 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
361 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
364 * CPU interface registers
366 #define ICC_CTLR_EL1_EOImode_SHIFT (1)
367 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
368 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
369 #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
370 #define ICC_CTLR_EL1_CBPR_SHIFT 0
371 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
372 #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
373 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
374 #define ICC_CTLR_EL1_ID_BITS_SHIFT 11
375 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
376 #define ICC_CTLR_EL1_SEIS_SHIFT 14
377 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
378 #define ICC_CTLR_EL1_A3V_SHIFT 15
379 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
380 #define ICC_PMR_EL1_SHIFT 0
381 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
382 #define ICC_BPR0_EL1_SHIFT 0
383 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
384 #define ICC_BPR1_EL1_SHIFT 0
385 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
386 #define ICC_IGRPEN0_EL1_SHIFT 0
387 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
388 #define ICC_IGRPEN1_EL1_SHIFT 0
389 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
390 #define ICC_SRE_EL1_DIB (1U << 2)
391 #define ICC_SRE_EL1_DFB (1U << 1)
392 #define ICC_SRE_EL1_SRE (1U << 0)
395 * Hypervisor interface registers (SRE only)
397 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
399 #define ICH_LR_EOI (1ULL << 41)
400 #define ICH_LR_GROUP (1ULL << 60)
401 #define ICH_LR_HW (1ULL << 61)
402 #define ICH_LR_STATE (3ULL << 62)
403 #define ICH_LR_PENDING_BIT (1ULL << 62)
404 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
405 #define ICH_LR_PHYS_ID_SHIFT 32
406 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
407 #define ICH_LR_PRIORITY_SHIFT 48
409 /* These are for GICv2 emulation only */
410 #define GICH_LR_VIRTUALID (0x3ffUL << 0)
411 #define GICH_LR_PHYSID_CPUID_SHIFT (10)
412 #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
414 #define ICH_MISR_EOI (1 << 0)
415 #define ICH_MISR_U (1 << 1)
417 #define ICH_HCR_EN (1 << 0)
418 #define ICH_HCR_UIE (1 << 1)
420 #define ICH_VMCR_CBPR_SHIFT 4
421 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
422 #define ICH_VMCR_EOIM_SHIFT 9
423 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
424 #define ICH_VMCR_BPR1_SHIFT 18
425 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
426 #define ICH_VMCR_BPR0_SHIFT 21
427 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
428 #define ICH_VMCR_PMR_SHIFT 24
429 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
430 #define ICH_VMCR_ENG0_SHIFT 0
431 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
432 #define ICH_VMCR_ENG1_SHIFT 1
433 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
435 #define ICH_VTR_PRI_BITS_SHIFT 29
436 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
437 #define ICH_VTR_ID_BITS_SHIFT 23
438 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
439 #define ICH_VTR_SEIS_SHIFT 22
440 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
441 #define ICH_VTR_A3V_SHIFT 21
442 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
444 #define ICC_IAR1_EL1_SPURIOUS 0x3ff
446 #define ICC_SRE_EL2_SRE (1 << 0)
447 #define ICC_SRE_EL2_ENABLE (1 << 3)
449 #define ICC_SGI1R_TARGET_LIST_SHIFT 0
450 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
451 #define ICC_SGI1R_AFFINITY_1_SHIFT 16
452 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
453 #define ICC_SGI1R_SGI_ID_SHIFT 24
454 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
455 #define ICC_SGI1R_AFFINITY_2_SHIFT 32
456 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
457 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
458 #define ICC_SGI1R_AFFINITY_3_SHIFT 48
459 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
461 #include <asm/arch_gicv3.h>
466 * We need a value to serve as a irq-type for LPIs. Choose one that will
467 * hopefully pique the interest of the reviewer.
469 #define GIC_IRQ_TYPE_LPI 0xa110c8ed
473 void __iomem
*rd_base
;
474 struct page
*pend_page
;
475 phys_addr_t phys_base
;
477 struct page
*prop_page
;
483 struct fwnode_handle
;
484 int its_cpu_init(void);
485 int its_init(struct fwnode_handle
*handle
, struct rdists
*rdists
,
486 struct irq_domain
*domain
);
488 static inline bool gic_enable_sre(void)
492 val
= gic_read_sre();
493 if (val
& ICC_SRE_EL1_SRE
)
496 val
|= ICC_SRE_EL1_SRE
;
498 val
= gic_read_sre();
500 return !!(val
& ICC_SRE_EL1_SRE
);