include/linux/lightnvm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef NVM_H
   3 #define NVM_H
   4
   5 #include <linux/blkdev.h>
   6 #include <linux/types.h>
   7 #include <uapi/linux/lightnvm.h>
   8
   9 enum {
  10         NVM_IO_OK = 0,
  11         NVM_IO_REQUEUE = 1,
  12         NVM_IO_DONE = 2,
  13         NVM_IO_ERR = 3,
  14
  15         NVM_IOTYPE_NONE = 0,
  16         NVM_IOTYPE_GC = 1,
  17 };
  18
  19 /* common format */
  20 #define NVM_GEN_CH_BITS  (8)
  21 #define NVM_GEN_LUN_BITS (8)
  22 #define NVM_GEN_BLK_BITS (16)
  23 #define NVM_GEN_RESERVED (32)
  24
  25 /* 1.2 format */
  26 #define NVM_12_PG_BITS  (16)
  27 #define NVM_12_PL_BITS  (4)
  28 #define NVM_12_SEC_BITS (4)
  29 #define NVM_12_RESERVED (8)
  30
  31 /* 2.0 format */
  32 #define NVM_20_SEC_BITS (24)
  33 #define NVM_20_RESERVED (8)
  34
  35 enum {
  36         NVM_OCSSD_SPEC_12 = 12,
  37         NVM_OCSSD_SPEC_20 = 20,
  38 };
  39
  40 struct ppa_addr {
  41         /* Generic structure for all addresses */
  42         union {
  43                 /* generic device format */
  44                 struct {
  45                         u64 ch          : NVM_GEN_CH_BITS;
  46                         u64 lun         : NVM_GEN_LUN_BITS;
  47                         u64 blk         : NVM_GEN_BLK_BITS;
  48                         u64 reserved    : NVM_GEN_RESERVED;
  49                 } a;
  50
  51                 /* 1.2 device format */
  52                 struct {
  53                         u64 ch          : NVM_GEN_CH_BITS;
  54                         u64 lun         : NVM_GEN_LUN_BITS;
  55                         u64 blk         : NVM_GEN_BLK_BITS;
  56                         u64 pg          : NVM_12_PG_BITS;
  57                         u64 pl          : NVM_12_PL_BITS;
  58                         u64 sec         : NVM_12_SEC_BITS;
  59                         u64 reserved    : NVM_12_RESERVED;
  60                 } g;
  61
  62                 /* 2.0 device format */
  63                 struct {
  64                         u64 grp         : NVM_GEN_CH_BITS;
  65                         u64 pu          : NVM_GEN_LUN_BITS;
  66                         u64 chk         : NVM_GEN_BLK_BITS;
  67                         u64 sec         : NVM_20_SEC_BITS;
  68                         u64 reserved    : NVM_20_RESERVED;
  69                 } m;
  70
  71                 struct {
  72                         u64 line        : 63;
  73                         u64 is_cached   : 1;
  74                 } c;
  75
  76                 u64 ppa;
  77         };
  78 };
  79
  80 struct nvm_rq;
  81 struct nvm_id;
  82 struct nvm_dev;
  83 struct nvm_tgt_dev;
  84 struct nvm_chk_meta;
  85
  86 typedef int (nvm_id_fn)(struct nvm_dev *);
  87 typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
  88 typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
  89 typedef int (nvm_get_chk_meta_fn)(struct nvm_dev *, sector_t, int,
  90                                                         struct nvm_chk_meta *);
  91 typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *, void *);
  92 typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *, int);
  93 typedef void (nvm_destroy_dma_pool_fn)(void *);
  94 typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
  95                                                                 dma_addr_t *);
  96 typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);
  97
  98 struct nvm_dev_ops {
  99         nvm_id_fn               *identity;
 100         nvm_op_bb_tbl_fn        *get_bb_tbl;
 101         nvm_op_set_bb_fn        *set_bb_tbl;
 102
 103         nvm_get_chk_meta_fn     *get_chk_meta;
 104
 105         nvm_submit_io_fn        *submit_io;
 106
 107         nvm_create_dma_pool_fn  *create_dma_pool;
 108         nvm_destroy_dma_pool_fn *destroy_dma_pool;
 109         nvm_dev_dma_alloc_fn    *dev_dma_alloc;
 110         nvm_dev_dma_free_fn     *dev_dma_free;
 111 };
 112
 113 #ifdef CONFIG_NVM
 114
 115 #include <linux/file.h>
 116 #include <linux/dmapool.h>
 117
 118 enum {
 119         /* HW Responsibilities */
 120         NVM_RSP_L2P     = 1 << 0,
 121         NVM_RSP_ECC     = 1 << 1,
 122
 123         /* Physical Adressing Mode */
 124         NVM_ADDRMODE_LINEAR     = 0,
 125         NVM_ADDRMODE_CHANNEL    = 1,
 126
 127         /* Plane programming mode for LUN */
 128         NVM_PLANE_SINGLE        = 1,
 129         NVM_PLANE_DOUBLE        = 2,
 130         NVM_PLANE_QUAD          = 4,
 131
 132         /* Status codes */
 133         NVM_RSP_SUCCESS         = 0x0,
 134         NVM_RSP_NOT_CHANGEABLE  = 0x1,
 135         NVM_RSP_ERR_FAILWRITE   = 0x40ff,
 136         NVM_RSP_ERR_EMPTYPAGE   = 0x42ff,
 137         NVM_RSP_ERR_FAILECC     = 0x4281,
 138         NVM_RSP_ERR_FAILCRC     = 0x4004,
 139         NVM_RSP_WARN_HIGHECC    = 0x4700,
 140
 141         /* Device opcodes */
 142         NVM_OP_PWRITE           = 0x91,
 143         NVM_OP_PREAD            = 0x92,
 144         NVM_OP_ERASE            = 0x90,
 145
 146         /* PPA Command Flags */
 147         NVM_IO_SNGL_ACCESS      = 0x0,
 148         NVM_IO_DUAL_ACCESS      = 0x1,
 149         NVM_IO_QUAD_ACCESS      = 0x2,
 150
 151         /* NAND Access Modes */
 152         NVM_IO_SUSPEND          = 0x80,
 153         NVM_IO_SLC_MODE         = 0x100,
 154         NVM_IO_SCRAMBLE_ENABLE  = 0x200,
 155
 156         /* Block Types */
 157         NVM_BLK_T_FREE          = 0x0,
 158         NVM_BLK_T_BAD           = 0x1,
 159         NVM_BLK_T_GRWN_BAD      = 0x2,
 160         NVM_BLK_T_DEV           = 0x4,
 161         NVM_BLK_T_HOST          = 0x8,
 162
 163         /* Memory capabilities */
 164         NVM_ID_CAP_SLC          = 0x1,
 165         NVM_ID_CAP_CMD_SUSPEND  = 0x2,
 166         NVM_ID_CAP_SCRAMBLE     = 0x4,
 167         NVM_ID_CAP_ENCRYPT      = 0x8,
 168
 169         /* Memory types */
 170         NVM_ID_FMTYPE_SLC       = 0,
 171         NVM_ID_FMTYPE_MLC       = 1,
 172
 173         /* Device capabilities */
 174         NVM_ID_DCAP_BBLKMGMT    = 0x1,
 175         NVM_UD_DCAP_ECC         = 0x2,
 176 };
 177
 178 struct nvm_id_lp_mlc {
 179         u16     num_pairs;
 180         u8      pairs[886];
 181 };
 182
 183 struct nvm_id_lp_tbl {
 184         __u8    id[8];
 185         struct nvm_id_lp_mlc mlc;
 186 };
 187
 188 struct nvm_addrf_12 {
 189         u8      ch_len;
 190         u8      lun_len;
 191         u8      blk_len;
 192         u8      pg_len;
 193         u8      pln_len;
 194         u8      sec_len;
 195
 196         u8      ch_offset;
 197         u8      lun_offset;
 198         u8      blk_offset;
 199         u8      pg_offset;
 200         u8      pln_offset;
 201         u8      sec_offset;
 202
 203         u64     ch_mask;
 204         u64     lun_mask;
 205         u64     blk_mask;
 206         u64     pg_mask;
 207         u64     pln_mask;
 208         u64     sec_mask;
 209 };
 210
 211 struct nvm_addrf {
 212         u8      ch_len;
 213         u8      lun_len;
 214         u8      chk_len;
 215         u8      sec_len;
 216         u8      rsv_len[2];
 217
 218         u8      ch_offset;
 219         u8      lun_offset;
 220         u8      chk_offset;
 221         u8      sec_offset;
 222         u8      rsv_off[2];
 223
 224         u64     ch_mask;
 225         u64     lun_mask;
 226         u64     chk_mask;
 227         u64     sec_mask;
 228         u64     rsv_mask[2];
 229 };
 230
 231 enum {
 232         /* Chunk states */
 233         NVM_CHK_ST_FREE =       1 << 0,
 234         NVM_CHK_ST_CLOSED =     1 << 1,
 235         NVM_CHK_ST_OPEN =       1 << 2,
 236         NVM_CHK_ST_OFFLINE =    1 << 3,
 237
 238         /* Chunk types */
 239         NVM_CHK_TP_W_SEQ =      1 << 0,
 240         NVM_CHK_TP_W_RAN =      1 << 1,
 241         NVM_CHK_TP_SZ_SPEC =    1 << 4,
 242 };
 243
 244 /*
 245  * Note: The structure size is linked to nvme_nvm_chk_meta such that the same
 246  * buffer can be used when converting from little endian to cpu addressing.
 247  */
 248 struct nvm_chk_meta {
 249         u8      state;
 250         u8      type;
 251         u8      wi;
 252         u8      rsvd[5];
 253         u64     slba;
 254         u64     cnlb;
 255         u64     wp;
 256 };
 257
 258 struct nvm_target {
 259         struct list_head list;
 260         struct nvm_tgt_dev *dev;
 261         struct nvm_tgt_type *type;
 262         struct gendisk *disk;
 263 };
 264
 265 #define ADDR_EMPTY (~0ULL)
 266
 267 #define NVM_TARGET_DEFAULT_OP (101)
 268 #define NVM_TARGET_MIN_OP (3)
 269 #define NVM_TARGET_MAX_OP (80)
 270
 271 #define NVM_VERSION_MAJOR 1
 272 #define NVM_VERSION_MINOR 0
 273 #define NVM_VERSION_PATCH 0
 274
 275 #define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */
 276
 277 struct nvm_rq;
 278 typedef void (nvm_end_io_fn)(struct nvm_rq *);
 279
 280 struct nvm_rq {
 281         struct nvm_tgt_dev *dev;
 282
 283         struct bio *bio;
 284
 285         union {
 286                 struct ppa_addr ppa_addr;
 287                 dma_addr_t dma_ppa_list;
 288         };
 289
 290         struct ppa_addr *ppa_list;
 291
 292         void *meta_list;
 293         dma_addr_t dma_meta_list;
 294
 295         nvm_end_io_fn *end_io;
 296
 297         uint8_t opcode;
 298         uint16_t nr_ppas;
 299         uint16_t flags;
 300
 301         u64 ppa_status; /* ppa media status */
 302         int error;
 303
 304         int is_seq; /* Sequential hint flag. 1.2 only */
 305
 306         void *private;
 307 };
 308
 309 static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
 310 {
 311         return pdu - sizeof(struct nvm_rq);
 312 }
 313
 314 static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
 315 {
 316         return rqdata + 1;
 317 }
 318
 319 static inline struct ppa_addr *nvm_rq_to_ppa_list(struct nvm_rq *rqd)
 320 {
 321         return (rqd->nr_ppas > 1) ? rqd->ppa_list : &rqd->ppa_addr;
 322 }
 323
 324 enum {
 325         NVM_BLK_ST_FREE =       0x1,    /* Free block */
 326         NVM_BLK_ST_TGT =        0x2,    /* Block in use by target */
 327         NVM_BLK_ST_BAD =        0x8,    /* Bad block */
 328 };
 329
 330 /* Instance geometry */
 331 struct nvm_geo {
 332         /* device reported version */
 333         u8      major_ver_id;
 334         u8      minor_ver_id;
 335
 336         /* kernel short version */
 337         u8      version;
 338
 339         /* instance specific geometry */
 340         int num_ch;
 341         int num_lun;            /* per channel */
 342
 343         /* calculated values */
 344         int all_luns;           /* across channels */
 345         int all_chunks;         /* across channels */
 346
 347         int op;                 /* over-provision in instance */
 348
 349         sector_t total_secs;    /* across channels */
 350
 351         /* chunk geometry */
 352         u32     num_chk;        /* chunks per lun */
 353         u32     clba;           /* sectors per chunk */
 354         u16     csecs;          /* sector size */
 355         u16     sos;            /* out-of-band area size */
 356         bool    ext;            /* metadata in extended data buffer */
 357         u32     mdts;           /* Max data transfer size*/
 358
 359         /* device write constrains */
 360         u32     ws_min;         /* minimum write size */
 361         u32     ws_opt;         /* optimal write size */
 362         u32     mw_cunits;      /* distance required for successful read */
 363         u32     maxoc;          /* maximum open chunks */
 364         u32     maxocpu;        /* maximum open chunks per parallel unit */
 365
 366         /* device capabilities */
 367         u32     mccap;
 368
 369         /* device timings */
 370         u32     trdt;           /* Avg. Tread (ns) */
 371         u32     trdm;           /* Max Tread (ns) */
 372         u32     tprt;           /* Avg. Tprog (ns) */
 373         u32     tprm;           /* Max Tprog (ns) */
 374         u32     tbet;           /* Avg. Terase (ns) */
 375         u32     tbem;           /* Max Terase (ns) */
 376
 377         /* generic address format */
 378         struct nvm_addrf addrf;
 379
 380         /* 1.2 compatibility */
 381         u8      vmnt;
 382         u32     cap;
 383         u32     dom;
 384
 385         u8      mtype;
 386         u8      fmtype;
 387
 388         u16     cpar;
 389         u32     mpos;
 390
 391         u8      num_pln;
 392         u8      pln_mode;
 393         u16     num_pg;
 394         u16     fpg_sz;
 395 };
 396
 397 /* sub-device structure */
 398 struct nvm_tgt_dev {
 399         /* Device information */
 400         struct nvm_geo geo;
 401
 402         /* Base ppas for target LUNs */
 403         struct ppa_addr *luns;
 404
 405         struct request_queue *q;
 406
 407         struct nvm_dev *parent;
 408         void *map;
 409 };
 410
 411 struct nvm_dev {
 412         struct nvm_dev_ops *ops;
 413
 414         struct list_head devices;
 415
 416         /* Device information */
 417         struct nvm_geo geo;
 418
 419         unsigned long *lun_map;
 420         void *dma_pool;
 421
 422         /* Backend device */
 423         struct request_queue *q;
 424         char name[DISK_NAME_LEN];
 425         void *private_data;
 426
 427         struct kref ref;
 428         void *rmap;
 429
 430         struct mutex mlock;
 431         spinlock_t lock;
 432
 433         /* target management */
 434         struct list_head area_list;
 435         struct list_head targets;
 436 };
 437
 438 static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev,
 439                                                   struct ppa_addr r)
 440 {
 441         struct nvm_geo *geo = &dev->geo;
 442         struct ppa_addr l;
 443
 444         if (geo->version == NVM_OCSSD_SPEC_12) {
 445                 struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
 446
 447                 l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
 448                 l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
 449                 l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
 450                 l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
 451                 l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
 452                 l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset;
 453         } else {
 454                 struct nvm_addrf *lbaf = &geo->addrf;
 455
 456                 l.ppa = ((u64)r.m.grp) << lbaf->ch_offset;
 457                 l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset;
 458                 l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset;
 459                 l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset;
 460         }
 461
 462         return l;
 463 }
 464
 465 static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev,
 466                                                   struct ppa_addr r)
 467 {
 468         struct nvm_geo *geo = &dev->geo;
 469         struct ppa_addr l;
 470
 471         l.ppa = 0;
 472
 473         if (geo->version == NVM_OCSSD_SPEC_12) {
 474                 struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
 475
 476                 l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
 477                 l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
 478                 l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
 479                 l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
 480                 l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
 481                 l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset;
 482         } else {
 483                 struct nvm_addrf *lbaf = &geo->addrf;
 484
 485                 l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset;
 486                 l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset;
 487                 l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset;
 488                 l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset;
 489         }
 490
 491         return l;
 492 }
 493
 494 static inline u64 dev_to_chunk_addr(struct nvm_dev *dev, void *addrf,
 495                                     struct ppa_addr p)
 496 {
 497         struct nvm_geo *geo = &dev->geo;
 498         u64 caddr;
 499
 500         if (geo->version == NVM_OCSSD_SPEC_12) {
 501                 struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)addrf;
 502
 503                 caddr = (u64)p.g.pg << ppaf->pg_offset;
 504                 caddr |= (u64)p.g.pl << ppaf->pln_offset;
 505                 caddr |= (u64)p.g.sec << ppaf->sec_offset;
 506         } else {
 507                 caddr = p.m.sec;
 508         }
 509
 510         return caddr;
 511 }
 512
 513 static inline struct ppa_addr nvm_ppa32_to_ppa64(struct nvm_dev *dev,
 514                                                  void *addrf, u32 ppa32)
 515 {
 516         struct ppa_addr ppa64;
 517
 518         ppa64.ppa = 0;
 519
 520         if (ppa32 == -1) {
 521                 ppa64.ppa = ADDR_EMPTY;
 522         } else if (ppa32 & (1U << 31)) {
 523                 ppa64.c.line = ppa32 & ((~0U) >> 1);
 524                 ppa64.c.is_cached = 1;
 525         } else {
 526                 struct nvm_geo *geo = &dev->geo;
 527
 528                 if (geo->version == NVM_OCSSD_SPEC_12) {
 529                         struct nvm_addrf_12 *ppaf = addrf;
 530
 531                         ppa64.g.ch = (ppa32 & ppaf->ch_mask) >>
 532                                                         ppaf->ch_offset;
 533                         ppa64.g.lun = (ppa32 & ppaf->lun_mask) >>
 534                                                         ppaf->lun_offset;
 535                         ppa64.g.blk = (ppa32 & ppaf->blk_mask) >>
 536                                                         ppaf->blk_offset;
 537                         ppa64.g.pg = (ppa32 & ppaf->pg_mask) >>
 538                                                         ppaf->pg_offset;
 539                         ppa64.g.pl = (ppa32 & ppaf->pln_mask) >>
 540                                                         ppaf->pln_offset;
 541                         ppa64.g.sec = (ppa32 & ppaf->sec_mask) >>
 542                                                         ppaf->sec_offset;
 543                 } else {
 544                         struct nvm_addrf *lbaf = addrf;
 545
 546                         ppa64.m.grp = (ppa32 & lbaf->ch_mask) >>
 547                                                         lbaf->ch_offset;
 548                         ppa64.m.pu = (ppa32 & lbaf->lun_mask) >>
 549                                                         lbaf->lun_offset;
 550                         ppa64.m.chk = (ppa32 & lbaf->chk_mask) >>
 551                                                         lbaf->chk_offset;
 552                         ppa64.m.sec = (ppa32 & lbaf->sec_mask) >>
 553                                                         lbaf->sec_offset;
 554                 }
 555         }
 556
 557         return ppa64;
 558 }
 559
 560 static inline u32 nvm_ppa64_to_ppa32(struct nvm_dev *dev,
 561                                      void *addrf, struct ppa_addr ppa64)
 562 {
 563         u32 ppa32 = 0;
 564
 565         if (ppa64.ppa == ADDR_EMPTY) {
 566                 ppa32 = ~0U;
 567         } else if (ppa64.c.is_cached) {
 568                 ppa32 |= ppa64.c.line;
 569                 ppa32 |= 1U << 31;
 570         } else {
 571                 struct nvm_geo *geo = &dev->geo;
 572
 573                 if (geo->version == NVM_OCSSD_SPEC_12) {
 574                         struct nvm_addrf_12 *ppaf = addrf;
 575
 576                         ppa32 |= ppa64.g.ch << ppaf->ch_offset;
 577                         ppa32 |= ppa64.g.lun << ppaf->lun_offset;
 578                         ppa32 |= ppa64.g.blk << ppaf->blk_offset;
 579                         ppa32 |= ppa64.g.pg << ppaf->pg_offset;
 580                         ppa32 |= ppa64.g.pl << ppaf->pln_offset;
 581                         ppa32 |= ppa64.g.sec << ppaf->sec_offset;
 582                 } else {
 583                         struct nvm_addrf *lbaf = addrf;
 584
 585                         ppa32 |= ppa64.m.grp << lbaf->ch_offset;
 586                         ppa32 |= ppa64.m.pu << lbaf->lun_offset;
 587                         ppa32 |= ppa64.m.chk << lbaf->chk_offset;
 588                         ppa32 |= ppa64.m.sec << lbaf->sec_offset;
 589                 }
 590         }
 591
 592         return ppa32;
 593 }
 594
 595 static inline int nvm_next_ppa_in_chk(struct nvm_tgt_dev *dev,
 596                                       struct ppa_addr *ppa)
 597 {
 598         struct nvm_geo *geo = &dev->geo;
 599         int last = 0;
 600
 601         if (geo->version == NVM_OCSSD_SPEC_12) {
 602                 int sec = ppa->g.sec;
 603
 604                 sec++;
 605                 if (sec == geo->ws_min) {
 606                         int pg = ppa->g.pg;
 607
 608                         sec = 0;
 609                         pg++;
 610                         if (pg == geo->num_pg) {
 611                                 int pl = ppa->g.pl;
 612
 613                                 pg = 0;
 614                                 pl++;
 615                                 if (pl == geo->num_pln)
 616                                         last = 1;
 617
 618                                 ppa->g.pl = pl;
 619                         }
 620                         ppa->g.pg = pg;
 621                 }
 622                 ppa->g.sec = sec;
 623         } else {
 624                 ppa->m.sec++;
 625                 if (ppa->m.sec == geo->clba)
 626                         last = 1;
 627         }
 628
 629         return last;
 630 }
 631
 632 typedef sector_t (nvm_tgt_capacity_fn)(void *);
 633 typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
 634                                 int flags);
 635 typedef void (nvm_tgt_exit_fn)(void *, bool);
 636 typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
 637 typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
 638
 639 enum {
 640         NVM_TGT_F_DEV_L2P = 0,
 641         NVM_TGT_F_HOST_L2P = 1 << 0,
 642 };
 643
 644 struct nvm_tgt_type {
 645         const char *name;
 646         unsigned int version[3];
 647         int flags;
 648
 649         /* target entry points */
 650         const struct block_device_operations *bops;
 651         nvm_tgt_capacity_fn *capacity;
 652
 653         /* module-specific init/teardown */
 654         nvm_tgt_init_fn *init;
 655         nvm_tgt_exit_fn *exit;
 656
 657         /* sysfs */
 658         nvm_tgt_sysfs_init_fn *sysfs_init;
 659         nvm_tgt_sysfs_exit_fn *sysfs_exit;
 660
 661         /* For internal use */
 662         struct list_head list;
 663         struct module *owner;
 664 };
 665
 666 extern int nvm_register_tgt_type(struct nvm_tgt_type *);
 667 extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
 668
 669 extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
 670 extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);
 671
 672 extern struct nvm_dev *nvm_alloc_dev(int);
 673 extern int nvm_register(struct nvm_dev *);
 674 extern void nvm_unregister(struct nvm_dev *);
 675
 676 extern int nvm_get_chunk_meta(struct nvm_tgt_dev *, struct ppa_addr,
 677                               int, struct nvm_chk_meta *);
 678 extern int nvm_set_chunk_meta(struct nvm_tgt_dev *, struct ppa_addr *,
 679                               int, int);
 680 extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *, void *);
 681 extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *, void *);
 682 extern void nvm_end_io(struct nvm_rq *);
 683
 684 #else /* CONFIG_NVM */
 685 struct nvm_dev_ops;
 686
 687 static inline struct nvm_dev *nvm_alloc_dev(int node)
 688 {
 689         return ERR_PTR(-EINVAL);
 690 }
 691 static inline int nvm_register(struct nvm_dev *dev)
 692 {
 693         return -EINVAL;
 694 }
 695 static inline void nvm_unregister(struct nvm_dev *dev) {}
 696 #endif /* CONFIG_NVM */
 697 #endif /* LIGHTNVM.H */