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1 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
2 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
3 * derived from Data Sheet, Copyright Motorola 1984 (!).
4 * It was written to be part of the Linux operating system.
6 /* permission is hereby granted to copy, modify and redistribute this code
7 * in terms of the GNU Library General Public License, Version 2 or later,
11 #ifndef _MC146818RTC_H
12 #define _MC146818RTC_H
15 #include <linux/rtc.h> /* get the user-level API */
16 #include <asm/mc146818rtc.h> /* register access macros */
19 #include <linux/spinlock.h> /* spinlock_t */
20 extern spinlock_t rtc_lock
; /* serialize CMOS RAM access */
22 /* Some RTCs extend the mc146818 register set to support alarms of more
23 * than 24 hours in the future; or dates that include a century code.
24 * This platform_data structure can pass this information to the driver.
26 struct cmos_rtc_board_info
{
27 u8 rtc_day_alarm
; /* zero, or register index */
28 u8 rtc_mon_alarm
; /* zero, or register index */
29 u8 rtc_century
; /* zero, or register index */
33 /**********************************************************************
35 **********************************************************************/
37 #define RTC_SECONDS_ALARM 1
39 #define RTC_MINUTES_ALARM 3
41 #define RTC_HOURS_ALARM 5
42 /* RTC_*_alarm is always true if 2 MSBs are set */
43 # define RTC_ALARM_DONT_CARE 0xC0
45 #define RTC_DAY_OF_WEEK 6
46 #define RTC_DAY_OF_MONTH 7
50 /* control registers - Moto names
57 /**********************************************************************
59 **********************************************************************/
60 #define RTC_FREQ_SELECT RTC_REG_A
62 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
63 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
64 * totalling to a max high interval of 2.228 ms.
67 # define RTC_DIV_CTL 0x70
68 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
69 # define RTC_REF_CLCK_4MHZ 0x00
70 # define RTC_REF_CLCK_1MHZ 0x10
71 # define RTC_REF_CLCK_32KHZ 0x20
72 /* 2 values for divider stage reset, others for "testing purposes only" */
73 # define RTC_DIV_RESET1 0x60
74 # define RTC_DIV_RESET2 0x70
75 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
76 # define RTC_RATE_SELECT 0x0F
78 /**********************************************************************/
79 #define RTC_CONTROL RTC_REG_B
80 # define RTC_SET 0x80 /* disable updates for clock setting */
81 # define RTC_PIE 0x40 /* periodic interrupt enable */
82 # define RTC_AIE 0x20 /* alarm interrupt enable */
83 # define RTC_UIE 0x10 /* update-finished interrupt enable */
84 # define RTC_SQWE 0x08 /* enable square-wave output */
85 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
86 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
87 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
89 /**********************************************************************/
90 #define RTC_INTR_FLAGS RTC_REG_C
91 /* caution - cleared by read */
92 # define RTC_IRQF 0x80 /* any of the following 3 is active */
97 /**********************************************************************/
98 #define RTC_VALID RTC_REG_D
99 # define RTC_VRT 0x80 /* valid RAM and time */
100 /**********************************************************************/
102 #ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */
104 #define RTC_IO_EXTENT 0x8
105 #define RTC_IOMAPPED 1 /* Default to I/O mapping. */
107 #endif /* ARCH_RTC_LOCATION */
109 #endif /* _MC146818RTC_H */