2 * Marvell 88PM80x Interface
4 * Copyright (C) 2012 Marvell International Ltd.
5 * Qiao Zhou <zhouqiao@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #ifndef __LINUX_MFD_88PM80X_H
13 #define __LINUX_MFD_88PM80X_H
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/regmap.h>
18 #include <linux/atomic.h>
20 #define PM80X_VERSION_MASK (0xFF) /* 80X chip ID mask */
57 #define PM800_MAX_REGULATOR PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */
58 #define PM800_NUM_BUCK (5) /*5 Bucks */
59 #define PM800_NUM_LDO (19) /*19 Bucks */
61 /* page 0 basic: slave adder 0x60 */
63 #define PM800_STATUS_1 (0x01)
64 #define PM800_ONKEY_STS1 (1 << 0)
65 #define PM800_EXTON_STS1 (1 << 1)
66 #define PM800_CHG_STS1 (1 << 2)
67 #define PM800_BAT_STS1 (1 << 3)
68 #define PM800_VBUS_STS1 (1 << 4)
69 #define PM800_LDO_PGOOD_STS1 (1 << 5)
70 #define PM800_BUCK_PGOOD_STS1 (1 << 6)
72 #define PM800_STATUS_2 (0x02)
73 #define PM800_RTC_ALARM_STS2 (1 << 0)
75 /* Wakeup Registers */
76 #define PM800_WAKEUP1 (0x0D)
78 #define PM800_WAKEUP2 (0x0E)
79 #define PM800_WAKEUP2_INV_INT (1 << 0)
80 #define PM800_WAKEUP2_INT_CLEAR (1 << 1)
81 #define PM800_WAKEUP2_INT_MASK (1 << 2)
83 #define PM800_POWER_UP_LOG (0x10)
85 /* Referance and low power registers */
86 #define PM800_LOW_POWER1 (0x20)
87 #define PM800_LOW_POWER2 (0x21)
88 #define PM800_LOW_POWER_CONFIG3 (0x22)
89 #define PM800_LOW_POWER_CONFIG4 (0x23)
92 #define PM800_GPIO_0_1_CNTRL (0x30)
93 #define PM800_GPIO0_VAL (1 << 0)
94 #define PM800_GPIO0_GPIO_MODE(x) (x << 1)
95 #define PM800_GPIO1_VAL (1 << 4)
96 #define PM800_GPIO1_GPIO_MODE(x) (x << 5)
98 #define PM800_GPIO_2_3_CNTRL (0x31)
99 #define PM800_GPIO2_VAL (1 << 0)
100 #define PM800_GPIO2_GPIO_MODE(x) (x << 1)
101 #define PM800_GPIO3_VAL (1 << 4)
102 #define PM800_GPIO3_GPIO_MODE(x) (x << 5)
103 #define PM800_GPIO3_MODE_MASK 0x1F
104 #define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
106 #define PM800_GPIO_4_CNTRL (0x32)
107 #define PM800_GPIO4_VAL (1 << 0)
108 #define PM800_GPIO4_GPIO_MODE(x) (x << 1)
110 #define PM800_HEADSET_CNTRL (0x38)
111 #define PM800_HEADSET_DET_EN (1 << 7)
112 #define PM800_HSDET_SLP (1 << 1)
114 #define PM800_PWM1 (0x40)
115 #define PM800_PWM2 (0x41)
116 #define PM800_PWM3 (0x42)
117 #define PM800_PWM4 (0x43)
120 #define PM800_RTC_CONTROL (0xD0)
121 #define PM800_RTC_MISC1 (0xE1)
122 #define PM800_RTC_MISC2 (0xE2)
123 #define PM800_RTC_MISC3 (0xE3)
124 #define PM800_RTC_MISC4 (0xE4)
125 #define PM800_RTC_MISC5 (0xE7)
126 /* bit definitions of RTC Register 1 (0xD0) */
127 #define PM800_ALARM1_EN (1 << 0)
128 #define PM800_ALARM_WAKEUP (1 << 4)
129 #define PM800_ALARM (1 << 5)
130 #define PM800_RTC1_USE_XO (1 << 7)
132 /* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
135 #define PM800_SLEEP_BUCK1 (0x30)
137 /* BUCK Sleep Mode Register 1: BUCK[1..4] */
138 #define PM800_BUCK_SLP1 (0x5A)
139 #define PM800_BUCK1_SLP1_SHIFT 0
140 #define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
142 /* page 2 GPADC: slave adder 0x02 */
143 #define PM800_GPADC_MEAS_EN1 (0x01)
144 #define PM800_MEAS_EN1_VBAT (1 << 2)
145 #define PM800_GPADC_MEAS_EN2 (0x02)
146 #define PM800_MEAS_EN2_RFTMP (1 << 0)
147 #define PM800_MEAS_GP0_EN (1 << 2)
148 #define PM800_MEAS_GP1_EN (1 << 3)
149 #define PM800_MEAS_GP2_EN (1 << 4)
150 #define PM800_MEAS_GP3_EN (1 << 5)
151 #define PM800_MEAS_GP4_EN (1 << 6)
153 #define PM800_GPADC_MISC_CONFIG1 (0x05)
154 #define PM800_GPADC_MISC_CONFIG2 (0x06)
155 #define PM800_GPADC_MISC_GPFSM_EN (1 << 0)
156 #define PM800_GPADC_SLOW_MODE(x) (x << 3)
158 #define PM800_GPADC_MISC_CONFIG3 (0x09)
159 #define PM800_GPADC_MISC_CONFIG4 (0x0A)
161 #define PM800_GPADC_PREBIAS1 (0x0F)
162 #define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
163 #define PM800_GPADC_PREBIAS2 (0x10)
165 #define PM800_GP_BIAS_ENA1 (0x14)
166 #define PM800_GPADC_GP_BIAS_EN0 (1 << 0)
167 #define PM800_GPADC_GP_BIAS_EN1 (1 << 1)
168 #define PM800_GPADC_GP_BIAS_EN2 (1 << 2)
169 #define PM800_GPADC_GP_BIAS_EN3 (1 << 3)
171 #define PM800_GP_BIAS_OUT1 (0x15)
172 #define PM800_BIAS_OUT_GP0 (1 << 0)
173 #define PM800_BIAS_OUT_GP1 (1 << 1)
174 #define PM800_BIAS_OUT_GP2 (1 << 2)
175 #define PM800_BIAS_OUT_GP3 (1 << 3)
177 #define PM800_GPADC0_LOW_TH 0x20
178 #define PM800_GPADC1_LOW_TH 0x21
179 #define PM800_GPADC2_LOW_TH 0x22
180 #define PM800_GPADC3_LOW_TH 0x23
181 #define PM800_GPADC4_LOW_TH 0x24
183 #define PM800_GPADC0_UPP_TH 0x30
184 #define PM800_GPADC1_UPP_TH 0x31
185 #define PM800_GPADC2_UPP_TH 0x32
186 #define PM800_GPADC3_UPP_TH 0x33
187 #define PM800_GPADC4_UPP_TH 0x34
189 #define PM800_VBBAT_MEAS1 0x40
190 #define PM800_VBBAT_MEAS2 0x41
191 #define PM800_VBAT_MEAS1 0x42
192 #define PM800_VBAT_MEAS2 0x43
193 #define PM800_VSYS_MEAS1 0x44
194 #define PM800_VSYS_MEAS2 0x45
195 #define PM800_VCHG_MEAS1 0x46
196 #define PM800_VCHG_MEAS2 0x47
197 #define PM800_TINT_MEAS1 0x50
198 #define PM800_TINT_MEAS2 0x51
199 #define PM800_PMOD_MEAS1 0x52
200 #define PM800_PMOD_MEAS2 0x53
202 #define PM800_GPADC0_MEAS1 0x54
203 #define PM800_GPADC0_MEAS2 0x55
204 #define PM800_GPADC1_MEAS1 0x56
205 #define PM800_GPADC1_MEAS2 0x57
206 #define PM800_GPADC2_MEAS1 0x58
207 #define PM800_GPADC2_MEAS2 0x59
208 #define PM800_GPADC3_MEAS1 0x5A
209 #define PM800_GPADC3_MEAS2 0x5B
210 #define PM800_GPADC4_MEAS1 0x5C
211 #define PM800_GPADC4_MEAS2 0x5D
213 #define PM800_GPADC4_AVG1 0xA8
214 #define PM800_GPADC4_AVG2 0xA9
216 /* 88PM805 Registers */
217 #define PM805_MAIN_POWERUP (0x01)
218 #define PM805_INT_STATUS0 (0x02) /* for ena/dis all interrupts */
220 #define PM805_STATUS0_INT_CLEAR (1 << 0)
221 #define PM805_STATUS0_INV_INT (1 << 1)
222 #define PM800_STATUS0_INT_MASK (1 << 2)
224 #define PM805_INT_STATUS1 (0x03)
226 #define PM805_INT1_HP1_SHRT (1 << 0)
227 #define PM805_INT1_HP2_SHRT (1 << 1)
228 #define PM805_INT1_MIC_CONFLICT (1 << 2)
229 #define PM805_INT1_CLIP_FAULT (1 << 3)
230 #define PM805_INT1_LDO_OFF (1 << 4)
231 #define PM805_INT1_SRC_DPLL_LOCK (1 << 5)
233 #define PM805_INT_STATUS2 (0x04)
235 #define PM805_INT2_MIC_DET (1 << 0)
236 #define PM805_INT2_SHRT_BTN_DET (1 << 1)
237 #define PM805_INT2_VOLM_BTN_DET (1 << 2)
238 #define PM805_INT2_VOLP_BTN_DET (1 << 3)
239 #define PM805_INT2_RAW_PLL_FAULT (1 << 4)
240 #define PM805_INT2_FINE_PLL_FAULT (1 << 5)
242 #define PM805_INT_MASK1 (0x05)
243 #define PM805_INT_MASK2 (0x06)
244 #define PM805_SHRT_BTN_DET (1 << 1)
246 /* number of status and int reg in a row */
247 #define PM805_INT_REG_NUM (2)
249 #define PM805_MIC_DET1 (0x07)
250 #define PM805_MIC_DET_EN_MIC_DET (1 << 0)
251 #define PM805_MIC_DET2 (0x08)
252 #define PM805_MIC_DET_STATUS1 (0x09)
254 #define PM805_MIC_DET_STATUS3 (0x0A)
255 #define PM805_AUTO_SEQ_STATUS1 (0x0B)
256 #define PM805_AUTO_SEQ_STATUS2 (0x0C)
258 #define PM805_ADC_SETTING1 (0x10)
259 #define PM805_ADC_SETTING2 (0x11)
260 #define PM805_ADC_SETTING3 (0x11)
261 #define PM805_ADC_GAIN1 (0x12)
262 #define PM805_ADC_GAIN2 (0x13)
263 #define PM805_DMIC_SETTING (0x15)
264 #define PM805_DWS_SETTING (0x16)
265 #define PM805_MIC_CONFLICT_STS (0x17)
267 #define PM805_PDM_SETTING1 (0x20)
268 #define PM805_PDM_SETTING2 (0x21)
269 #define PM805_PDM_SETTING3 (0x22)
270 #define PM805_PDM_CONTROL1 (0x23)
271 #define PM805_PDM_CONTROL2 (0x24)
272 #define PM805_PDM_CONTROL3 (0x25)
274 #define PM805_HEADPHONE_SETTING (0x26)
275 #define PM805_HEADPHONE_GAIN_A2A (0x27)
276 #define PM805_HEADPHONE_SHORT_STATE (0x28)
277 #define PM805_EARPHONE_SETTING (0x29)
278 #define PM805_AUTO_SEQ_SETTING (0x2A)
280 struct pm80x_rtc_pdata
{
285 struct pm80x_subchip
{
286 struct i2c_client
*power_page
; /* chip client for power page */
287 struct i2c_client
*gpadc_page
; /* chip client for gpadc page */
288 struct regmap
*regmap_power
;
289 struct regmap
*regmap_gpadc
;
290 unsigned short power_page_addr
; /* power page I2C address */
291 unsigned short gpadc_page_addr
; /* gpadc page I2C address */
295 struct pm80x_subchip
*subchip
;
297 struct i2c_client
*client
;
298 struct i2c_client
*companion
;
299 struct regmap
*regmap
;
300 struct regmap_irq_chip
*regmap_irq_chip
;
301 struct regmap_irq_chip_data
*irq_data
;
302 unsigned char version
;
306 unsigned long wu_flag
;
310 struct pm80x_platform_data
{
311 struct pm80x_rtc_pdata
*rtc
;
312 unsigned short power_page_addr
; /* power page I2C address */
313 unsigned short gpadc_page_addr
; /* gpadc page I2C address */
314 int irq_mode
; /* Clear interrupt by read/write(0/1) */
315 int batt_det
; /* enable/disable */
316 int (*plat_config
)(struct pm80x_chip
*chip
,
317 struct pm80x_platform_data
*pdata
);
320 extern const struct dev_pm_ops pm80x_pm_ops
;
321 extern const struct regmap_config pm80x_regmap_config
;
323 static inline int pm80x_request_irq(struct pm80x_chip
*pm80x
, int irq
,
324 irq_handler_t handler
, unsigned long flags
,
325 const char *name
, void *data
)
327 if (!pm80x
->irq_data
)
329 return request_threaded_irq(regmap_irq_get_virq(pm80x
->irq_data
, irq
),
330 NULL
, handler
, flags
, name
, data
);
333 static inline void pm80x_free_irq(struct pm80x_chip
*pm80x
, int irq
, void *data
)
335 if (!pm80x
->irq_data
)
337 free_irq(regmap_irq_get_virq(pm80x
->irq_data
, irq
), data
);
341 static inline int pm80x_dev_suspend(struct device
*dev
)
343 struct platform_device
*pdev
= to_platform_device(dev
);
344 struct pm80x_chip
*chip
= dev_get_drvdata(pdev
->dev
.parent
);
345 int irq
= platform_get_irq(pdev
, 0);
347 if (device_may_wakeup(dev
))
348 set_bit((1 << irq
), &chip
->wu_flag
);
353 static inline int pm80x_dev_resume(struct device
*dev
)
355 struct platform_device
*pdev
= to_platform_device(dev
);
356 struct pm80x_chip
*chip
= dev_get_drvdata(pdev
->dev
.parent
);
357 int irq
= platform_get_irq(pdev
, 0);
359 if (device_may_wakeup(dev
))
360 clear_bit((1 << irq
), &chip
->wu_flag
);
366 extern int pm80x_init(struct i2c_client
*client
,
367 const struct i2c_device_id
*id
);
368 extern int pm80x_deinit(void);
369 #endif /* __LINUX_MFD_88PM80X_H */