include/linux/mfd/altera-a10sr.h

   1 /*
   2  * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * Declarations for Altera Arria10 MAX5 System Resource Chip
  17  *
  18  * Adapted from DA9052
  19  */
  20
  21 #ifndef __MFD_ALTERA_A10SR_H
  22 #define __MFD_ALTERA_A10SR_H
  23
  24 #include <linux/completion.h>
  25 #include <linux/list.h>
  26 #include <linux/mfd/core.h>
  27 #include <linux/regmap.h>
  28 #include <linux/slab.h>
  29
  30 /* Write registers are always on even addresses */
  31 #define  WRITE_REG_MASK              0xFE
  32 /* Odd registers are always on odd addresses */
  33 #define  READ_REG_MASK               0x01
  34
  35 #define ALTR_A10SR_BITS_PER_REGISTER  8
  36 /*
  37  * To find the correct register, we divide the input GPIO by
  38  * the number of GPIO in each register. We then need to multiply
  39  * by 2 because the reads are at odd addresses.
  40  */
  41 #define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
  42 #define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
  43 #define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
  44 #define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
  45
  46 /* Arria10 System Controller Register Defines */
  47 #define ALTR_A10SR_NOP                0x00    /* No Change */
  48 #define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
  49
  50 #define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
  51 /* LED register Bit Definitions */
  52 #define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
  53 #define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
  54 #define ALTR_A10SR_OUT_VALID_RANGE_HI     7
  55
  56 #define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
  57 #define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
  58 /* Pushbutton & DIP Switch Bit Definitions */
  59 #define ALTR_A10SR_IN_VALID_RANGE_LO      8
  60 #define ALTR_A10SR_IN_VALID_RANGE_HI      15
  61
  62 #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
  63 #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
  64 #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
  65 #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
  66 #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
  67 #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
  68 #define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
  69 #define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
  70 #define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
  71 #define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
  72 #define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
  73 #define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
  74
  75 /**
  76  * struct altr_a10sr - Altera Max5 MFD device private data structure
  77  * @dev:  : this device
  78  * @regmap: the regmap assigned to the parent device.
  79  */
  80 struct altr_a10sr {
  81         struct device *dev;
  82         struct regmap *regmap;
  83 };
  84
  85 #endif /* __MFD_ALTERA_A10SR_H */