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1 /*
2 * Defining registers address and its bit definitions of MAX77620 and MAX20024
3 *
4 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11 #ifndef _MFD_MAX77620_H_
12 #define _MFD_MAX77620_H_
13
14 #include <linux/types.h>
15
16 /* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
17 #define MAX77620_REG_CNFGGLBL1 0x00
18 #define MAX77620_REG_CNFGGLBL2 0x01
19 #define MAX77620_REG_CNFGGLBL3 0x02
20 #define MAX77620_REG_CNFG1_32K 0x03
21 #define MAX77620_REG_CNFGBBC 0x04
22 #define MAX77620_REG_IRQTOP 0x05
23 #define MAX77620_REG_INTLBT 0x06
24 #define MAX77620_REG_IRQSD 0x07
25 #define MAX77620_REG_IRQ_LVL2_L0_7 0x08
26 #define MAX77620_REG_IRQ_LVL2_L8 0x09
27 #define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
28 #define MAX77620_REG_ONOFFIRQ 0x0B
29 #define MAX77620_REG_NVERC 0x0C
30 #define MAX77620_REG_IRQTOPM 0x0D
31 #define MAX77620_REG_INTENLBT 0x0E
32 #define MAX77620_REG_IRQMASKSD 0x0F
33 #define MAX77620_REG_IRQ_MSK_L0_7 0x10
34 #define MAX77620_REG_IRQ_MSK_L8 0x11
35 #define MAX77620_REG_ONOFFIRQM 0x12
36 #define MAX77620_REG_STATLBT 0x13
37 #define MAX77620_REG_STATSD 0x14
38 #define MAX77620_REG_ONOFFSTAT 0x15
39
40 /* SD and LDO Registers */
41 #define MAX77620_REG_SD0 0x16
42 #define MAX77620_REG_SD1 0x17
43 #define MAX77620_REG_SD2 0x18
44 #define MAX77620_REG_SD3 0x19
45 #define MAX77620_REG_SD4 0x1A
46 #define MAX77620_REG_DVSSD0 0x1B
47 #define MAX77620_REG_DVSSD1 0x1C
48 #define MAX77620_REG_SD0_CFG 0x1D
49 #define MAX77620_REG_SD1_CFG 0x1E
50 #define MAX77620_REG_SD2_CFG 0x1F
51 #define MAX77620_REG_SD3_CFG 0x20
52 #define MAX77620_REG_SD4_CFG 0x21
53 #define MAX77620_REG_SD_CFG2 0x22
54 #define MAX77620_REG_LDO0_CFG 0x23
55 #define MAX77620_REG_LDO0_CFG2 0x24
56 #define MAX77620_REG_LDO1_CFG 0x25
57 #define MAX77620_REG_LDO1_CFG2 0x26
58 #define MAX77620_REG_LDO2_CFG 0x27
59 #define MAX77620_REG_LDO2_CFG2 0x28
60 #define MAX77620_REG_LDO3_CFG 0x29
61 #define MAX77620_REG_LDO3_CFG2 0x2A
62 #define MAX77620_REG_LDO4_CFG 0x2B
63 #define MAX77620_REG_LDO4_CFG2 0x2C
64 #define MAX77620_REG_LDO5_CFG 0x2D
65 #define MAX77620_REG_LDO5_CFG2 0x2E
66 #define MAX77620_REG_LDO6_CFG 0x2F
67 #define MAX77620_REG_LDO6_CFG2 0x30
68 #define MAX77620_REG_LDO7_CFG 0x31
69 #define MAX77620_REG_LDO7_CFG2 0x32
70 #define MAX77620_REG_LDO8_CFG 0x33
71 #define MAX77620_REG_LDO8_CFG2 0x34
72 #define MAX77620_REG_LDO_CFG3 0x35
73
74 #define MAX77620_LDO_SLEW_RATE_MASK 0x1
75
76 /* LDO Configuration 3 */
77 #define MAX77620_TRACK4_MASK BIT(5)
78 #define MAX77620_TRACK4_SHIFT 5
79
80 /* Voltage */
81 #define MAX77620_SDX_VOLT_MASK 0xFF
82 #define MAX77620_SD0_VOLT_MASK 0x3F
83 #define MAX77620_SD1_VOLT_MASK 0x7F
84 #define MAX77620_LDO_VOLT_MASK 0x3F
85
86 #define MAX77620_REG_GPIO0 0x36
87 #define MAX77620_REG_GPIO1 0x37
88 #define MAX77620_REG_GPIO2 0x38
89 #define MAX77620_REG_GPIO3 0x39
90 #define MAX77620_REG_GPIO4 0x3A
91 #define MAX77620_REG_GPIO5 0x3B
92 #define MAX77620_REG_GPIO6 0x3C
93 #define MAX77620_REG_GPIO7 0x3D
94 #define MAX77620_REG_PUE_GPIO 0x3E
95 #define MAX77620_REG_PDE_GPIO 0x3F
96 #define MAX77620_REG_AME_GPIO 0x40
97 #define MAX77620_REG_ONOFFCNFG1 0x41
98 #define MAX77620_REG_ONOFFCNFG2 0x42
99
100 /* FPS Registers */
101 #define MAX77620_REG_FPS_CFG0 0x43
102 #define MAX77620_REG_FPS_CFG1 0x44
103 #define MAX77620_REG_FPS_CFG2 0x45
104 #define MAX77620_REG_FPS_LDO0 0x46
105 #define MAX77620_REG_FPS_LDO1 0x47
106 #define MAX77620_REG_FPS_LDO2 0x48
107 #define MAX77620_REG_FPS_LDO3 0x49
108 #define MAX77620_REG_FPS_LDO4 0x4A
109 #define MAX77620_REG_FPS_LDO5 0x4B
110 #define MAX77620_REG_FPS_LDO6 0x4C
111 #define MAX77620_REG_FPS_LDO7 0x4D
112 #define MAX77620_REG_FPS_LDO8 0x4E
113 #define MAX77620_REG_FPS_SD0 0x4F
114 #define MAX77620_REG_FPS_SD1 0x50
115 #define MAX77620_REG_FPS_SD2 0x51
116 #define MAX77620_REG_FPS_SD3 0x52
117 #define MAX77620_REG_FPS_SD4 0x53
118 #define MAX77620_REG_FPS_NONE 0
119
120 #define MAX77620_FPS_SRC_MASK 0xC0
121 #define MAX77620_FPS_SRC_SHIFT 6
122 #define MAX77620_FPS_PU_PERIOD_MASK 0x38
123 #define MAX77620_FPS_PU_PERIOD_SHIFT 3
124 #define MAX77620_FPS_PD_PERIOD_MASK 0x07
125 #define MAX77620_FPS_PD_PERIOD_SHIFT 0
126 #define MAX77620_FPS_TIME_PERIOD_MASK 0x38
127 #define MAX77620_FPS_TIME_PERIOD_SHIFT 3
128 #define MAX77620_FPS_EN_SRC_MASK 0x06
129 #define MAX77620_FPS_EN_SRC_SHIFT 1
130 #define MAX77620_FPS_ENFPS_SW_MASK 0x01
131 #define MAX77620_FPS_ENFPS_SW 0x01
132
133 /* Minimum and maximum FPS period time (in microseconds) are
134 * different for MAX77620 and Max20024.
135 */
136 #define MAX77620_FPS_PERIOD_MIN_US 40
137 #define MAX20024_FPS_PERIOD_MIN_US 20
138
139 #define MAX77620_FPS_PERIOD_MAX_US 2560
140 #define MAX20024_FPS_PERIOD_MAX_US 5120
141
142 #define MAX77620_REG_FPS_GPIO1 0x54
143 #define MAX77620_REG_FPS_GPIO2 0x55
144 #define MAX77620_REG_FPS_GPIO3 0x56
145 #define MAX77620_REG_FPS_RSO 0x57
146 #define MAX77620_REG_CID0 0x58
147 #define MAX77620_REG_CID1 0x59
148 #define MAX77620_REG_CID2 0x5A
149 #define MAX77620_REG_CID3 0x5B
150 #define MAX77620_REG_CID4 0x5C
151 #define MAX77620_REG_CID5 0x5D
152
153 #define MAX77620_REG_DVSSD4 0x5E
154 #define MAX20024_REG_MAX_ADD 0x70
155
156 #define MAX77620_CID_DIDM_MASK 0xF0
157 #define MAX77620_CID_DIDM_SHIFT 4
158
159 /* CNCG2SD */
160 #define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
161 #define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
162
163 /* Device Identification Metal */
164 #define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
165 /* Device Indentification OTP */
166 #define MAX77620_CID5_DIDO(n) ((n) & 0xF)
167
168 /* SD CNFG1 */
169 #define MAX77620_SD_SR_MASK 0xC0
170 #define MAX77620_SD_SR_SHIFT 6
171 #define MAX77620_SD_POWER_MODE_MASK 0x30
172 #define MAX77620_SD_POWER_MODE_SHIFT 4
173 #define MAX77620_SD_CFG1_ADE_MASK BIT(3)
174 #define MAX77620_SD_CFG1_ADE_DISABLE 0
175 #define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
176 #define MAX77620_SD_FPWM_MASK 0x04
177 #define MAX77620_SD_FPWM_SHIFT 2
178 #define MAX77620_SD_FSRADE_MASK 0x01
179 #define MAX77620_SD_FSRADE_SHIFT 0
180 #define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
181 #define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
182 #define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
183 #define MAX20024_SD_CFG1_MPOK_MASK BIT(1)
184 #define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
185 #define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
186 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
187
188 /* LDO_CNFG2 */
189 #define MAX77620_LDO_POWER_MODE_MASK 0xC0
190 #define MAX77620_LDO_POWER_MODE_SHIFT 6
191 #define MAX20024_LDO_CFG2_MPOK_MASK BIT(2)
192 #define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
193 #define MAX77620_LDO_CFG2_ADE_DISABLE 0
194 #define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
195 #define MAX77620_LDO_CFG2_SS_MASK BIT(0)
196 #define MAX77620_LDO_CFG2_SS_FAST BIT(0)
197 #define MAX77620_LDO_CFG2_SS_SLOW 0
198
199 #define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
200 #define MAX77620_IRQ_TOP_SD_MASK BIT(6)
201 #define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
202 #define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
203 #define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
204 #define MAX77620_IRQ_TOP_32K_MASK BIT(2)
205 #define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
206
207 #define MAX77620_IRQ_LBM_MASK BIT(3)
208 #define MAX77620_IRQ_TJALRM1_MASK BIT(2)
209 #define MAX77620_IRQ_TJALRM2_MASK BIT(1)
210
211 #define MAX77620_PWR_I2C_ADDR 0x3c
212 #define MAX77620_RTC_I2C_ADDR 0x68
213
214 #define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
215 #define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
216 #define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
217 #define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
218 #define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
219 #define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
220 #define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
221 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
222 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
223 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
224 #define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
225 #define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
226 #define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
227 #define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
228 #define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
229 #define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
230 #define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
231 #define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
232
233 #define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
234 #define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
235 #define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
236 #define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
237 #define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
238 #define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
239 #define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
240 #define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
241
242 #define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
243
244 #define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
245 #define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
246 #define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
247 #define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
248 #define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
249 #define MAX20024_ONOFFCNFG1_CLRSE 0x18
250
251 #define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
252 #define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
253 #define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
254 #define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
255 #define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
256
257 #define MAX77620_GLBLM_MASK BIT(0)
258
259 #define MAX77620_WDTC_MASK 0x3
260 #define MAX77620_WDTOFFC BIT(4)
261 #define MAX77620_WDTSLPC BIT(3)
262 #define MAX77620_WDTEN BIT(2)
263
264 #define MAX77620_TWD_MASK 0x3
265 #define MAX77620_TWD_2s 0x0
266 #define MAX77620_TWD_16s 0x1
267 #define MAX77620_TWD_64s 0x2
268 #define MAX77620_TWD_128s 0x3
269
270 #define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
271 #define MAX77620_CNFGGLBL1_MPPLD BIT(6)
272 #define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
273 #define MAX77620_CNFGGLBL1_LBDAC 0x0E
274 #define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
275
276 /* CNFG BBC registers */
277 #define MAX77620_CNFGBBC_ENABLE BIT(0)
278 #define MAX77620_CNFGBBC_CURRENT_MASK 0x06
279 #define MAX77620_CNFGBBC_CURRENT_SHIFT 1
280 #define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
281 #define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
282 #define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
283 #define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
284 #define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
285
286 #define MAX77620_FPS_COUNT 3
287
288 /* Interrupts */
289 enum {
290 MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
291 MAX77620_IRQ_TOP_SD, /* SD power fail */
292 MAX77620_IRQ_TOP_LDO, /* LDO power fail */
293 MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
294 MAX77620_IRQ_TOP_RTC, /* RTC */
295 MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
296 MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
297 MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
298 MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
299 MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
300 };
301
302 /* GPIOs */
303 enum {
304 MAX77620_GPIO0,
305 MAX77620_GPIO1,
306 MAX77620_GPIO2,
307 MAX77620_GPIO3,
308 MAX77620_GPIO4,
309 MAX77620_GPIO5,
310 MAX77620_GPIO6,
311 MAX77620_GPIO7,
312 MAX77620_GPIO_NR,
313 };
314
315 /* FPS Source */
316 enum max77620_fps_src {
317 MAX77620_FPS_SRC_0,
318 MAX77620_FPS_SRC_1,
319 MAX77620_FPS_SRC_2,
320 MAX77620_FPS_SRC_NONE,
321 MAX77620_FPS_SRC_DEF,
322 };
323
324 enum max77620_chip_id {
325 MAX77620,
326 MAX20024,
327 };
328
329 struct max77620_chip {
330 struct device *dev;
331 struct regmap *rmap;
332
333 int chip_irq;
334 int irq_base;
335
336 /* chip id */
337 enum max77620_chip_id chip_id;
338
339 bool sleep_enable;
340 bool enable_global_lpm;
341 int shutdown_fps_period[MAX77620_FPS_COUNT];
342 int suspend_fps_period[MAX77620_FPS_COUNT];
343
344 struct regmap_irq_chip_data *top_irq_data;
345 struct regmap_irq_chip_data *gpio_irq_data;
346 };
347
348 #endif /* _MFD_MAX77620_H_ */