2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
4 * Copyright (C) 2012 Samsung Electrnoics
5 * SangYoung Son <hello.son@samsung.com>
7 * This program is not provided / owned by Maxim Integrated Products.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __LINUX_MFD_MAX77693_PRIV_H
25 #define __LINUX_MFD_MAX77693_PRIV_H
27 #include <linux/i2c.h>
29 #define MAX77693_REG_INVALID (0xff)
31 /* Slave addr = 0xCC: PMIC, Charger, Flash LED */
32 enum max77693_pmic_reg
{
33 MAX77693_LED_REG_IFLASH1
= 0x00,
34 MAX77693_LED_REG_IFLASH2
= 0x01,
35 MAX77693_LED_REG_ITORCH
= 0x02,
36 MAX77693_LED_REG_ITORCHTIMER
= 0x03,
37 MAX77693_LED_REG_FLASH_TIMER
= 0x04,
38 MAX77693_LED_REG_FLASH_EN
= 0x05,
39 MAX77693_LED_REG_MAX_FLASH1
= 0x06,
40 MAX77693_LED_REG_MAX_FLASH2
= 0x07,
41 MAX77693_LED_REG_MAX_FLASH3
= 0x08,
42 MAX77693_LED_REG_MAX_FLASH4
= 0x09,
43 MAX77693_LED_REG_VOUT_CNTL
= 0x0A,
44 MAX77693_LED_REG_VOUT_FLASH1
= 0x0B,
45 MAX77693_LED_REG_VOUT_FLASH2
= 0x0C,
46 MAX77693_LED_REG_FLASH_INT
= 0x0E,
47 MAX77693_LED_REG_FLASH_INT_MASK
= 0x0F,
48 MAX77693_LED_REG_FLASH_STATUS
= 0x10,
50 MAX77693_PMIC_REG_PMIC_ID1
= 0x20,
51 MAX77693_PMIC_REG_PMIC_ID2
= 0x21,
52 MAX77693_PMIC_REG_INTSRC
= 0x22,
53 MAX77693_PMIC_REG_INTSRC_MASK
= 0x23,
54 MAX77693_PMIC_REG_TOPSYS_INT
= 0x24,
55 MAX77693_PMIC_REG_TOPSYS_INT_MASK
= 0x26,
56 MAX77693_PMIC_REG_TOPSYS_STAT
= 0x28,
57 MAX77693_PMIC_REG_MAINCTRL1
= 0x2A,
58 MAX77693_PMIC_REG_LSCNFG
= 0x2B,
60 MAX77693_CHG_REG_CHG_INT
= 0xB0,
61 MAX77693_CHG_REG_CHG_INT_MASK
= 0xB1,
62 MAX77693_CHG_REG_CHG_INT_OK
= 0xB2,
63 MAX77693_CHG_REG_CHG_DETAILS_00
= 0xB3,
64 MAX77693_CHG_REG_CHG_DETAILS_01
= 0xB4,
65 MAX77693_CHG_REG_CHG_DETAILS_02
= 0xB5,
66 MAX77693_CHG_REG_CHG_DETAILS_03
= 0xB6,
67 MAX77693_CHG_REG_CHG_CNFG_00
= 0xB7,
68 MAX77693_CHG_REG_CHG_CNFG_01
= 0xB8,
69 MAX77693_CHG_REG_CHG_CNFG_02
= 0xB9,
70 MAX77693_CHG_REG_CHG_CNFG_03
= 0xBA,
71 MAX77693_CHG_REG_CHG_CNFG_04
= 0xBB,
72 MAX77693_CHG_REG_CHG_CNFG_05
= 0xBC,
73 MAX77693_CHG_REG_CHG_CNFG_06
= 0xBD,
74 MAX77693_CHG_REG_CHG_CNFG_07
= 0xBE,
75 MAX77693_CHG_REG_CHG_CNFG_08
= 0xBF,
76 MAX77693_CHG_REG_CHG_CNFG_09
= 0xC0,
77 MAX77693_CHG_REG_CHG_CNFG_10
= 0xC1,
78 MAX77693_CHG_REG_CHG_CNFG_11
= 0xC2,
79 MAX77693_CHG_REG_CHG_CNFG_12
= 0xC3,
80 MAX77693_CHG_REG_CHG_CNFG_13
= 0xC4,
81 MAX77693_CHG_REG_CHG_CNFG_14
= 0xC5,
82 MAX77693_CHG_REG_SAFEOUT_CTRL
= 0xC6,
84 MAX77693_PMIC_REG_END
,
87 /* MAX77693 ITORCH register */
88 #define TORCH_IOUT1_SHIFT 0
89 #define TORCH_IOUT2_SHIFT 4
90 #define TORCH_IOUT_MIN 15625
91 #define TORCH_IOUT_MAX 250000
92 #define TORCH_IOUT_STEP 15625
94 /* MAX77693 IFLASH1 and IFLASH2 registers */
95 #define FLASH_IOUT_MIN 15625
96 #define FLASH_IOUT_MAX_1LED 1000000
97 #define FLASH_IOUT_MAX_2LEDS 625000
98 #define FLASH_IOUT_STEP 15625
100 /* MAX77693 TORCH_TIMER register */
101 #define TORCH_TMR_NO_TIMER 0x40
102 #define TORCH_TIMEOUT_MIN 262000
103 #define TORCH_TIMEOUT_MAX 15728000
105 /* MAX77693 FLASH_TIMER register */
106 #define FLASH_TMR_LEVEL 0x80
107 #define FLASH_TIMEOUT_MIN 62500
108 #define FLASH_TIMEOUT_MAX 1000000
109 #define FLASH_TIMEOUT_STEP 62500
111 /* MAX77693 FLASH_EN register */
112 #define FLASH_EN_OFF 0x0
113 #define FLASH_EN_FLASH 0x1
114 #define FLASH_EN_TORCH 0x2
115 #define FLASH_EN_ON 0x3
116 #define FLASH_EN_SHIFT(x) (6 - ((x) - 1) * 2)
117 #define TORCH_EN_SHIFT(x) (2 - ((x) - 1) * 2)
119 /* MAX77693 MAX_FLASH1 register */
120 #define MAX_FLASH1_MAX_FL_EN 0x80
121 #define MAX_FLASH1_VSYS_MIN 2400
122 #define MAX_FLASH1_VSYS_MAX 3400
123 #define MAX_FLASH1_VSYS_STEP 33
125 /* MAX77693 VOUT_CNTL register */
126 #define FLASH_BOOST_FIXED 0x04
127 #define FLASH_BOOST_LEDNUM_2 0x80
129 /* MAX77693 VOUT_FLASH1 register */
130 #define FLASH_VOUT_MIN 3300
131 #define FLASH_VOUT_MAX 5500
132 #define FLASH_VOUT_STEP 25
133 #define FLASH_VOUT_RMIN 0x0c
135 /* MAX77693 FLASH_STATUS register */
136 #define FLASH_STATUS_FLASH_ON BIT(3)
137 #define FLASH_STATUS_TORCH_ON BIT(2)
139 /* MAX77693 FLASH_INT register */
140 #define FLASH_INT_FLED2_OPEN BIT(0)
141 #define FLASH_INT_FLED2_SHORT BIT(1)
142 #define FLASH_INT_FLED1_OPEN BIT(2)
143 #define FLASH_INT_FLED1_SHORT BIT(3)
144 #define FLASH_INT_OVER_CURRENT BIT(4)
146 /* MAX77693 CHG_CNFG_00 register */
147 #define CHG_CNFG_00_CHG_MASK 0x1
148 #define CHG_CNFG_00_BUCK_MASK 0x4
150 /* MAX77693 CHG_CNFG_09 Register */
151 #define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F
153 /* MAX77693 CHG_CTRL Register */
154 #define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3
155 #define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC
156 #define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40
157 #define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80
159 /* Slave addr = 0x4A: MUIC */
160 enum max77693_muic_reg
{
161 MAX77693_MUIC_REG_ID
= 0x00,
162 MAX77693_MUIC_REG_INT1
= 0x01,
163 MAX77693_MUIC_REG_INT2
= 0x02,
164 MAX77693_MUIC_REG_INT3
= 0x03,
165 MAX77693_MUIC_REG_STATUS1
= 0x04,
166 MAX77693_MUIC_REG_STATUS2
= 0x05,
167 MAX77693_MUIC_REG_STATUS3
= 0x06,
168 MAX77693_MUIC_REG_INTMASK1
= 0x07,
169 MAX77693_MUIC_REG_INTMASK2
= 0x08,
170 MAX77693_MUIC_REG_INTMASK3
= 0x09,
171 MAX77693_MUIC_REG_CDETCTRL1
= 0x0A,
172 MAX77693_MUIC_REG_CDETCTRL2
= 0x0B,
173 MAX77693_MUIC_REG_CTRL1
= 0x0C,
174 MAX77693_MUIC_REG_CTRL2
= 0x0D,
175 MAX77693_MUIC_REG_CTRL3
= 0x0E,
177 MAX77693_MUIC_REG_END
,
180 /* MAX77693 INTMASK1~2 Register */
181 #define INTMASK1_ADC1K_SHIFT 3
182 #define INTMASK1_ADCERR_SHIFT 2
183 #define INTMASK1_ADCLOW_SHIFT 1
184 #define INTMASK1_ADC_SHIFT 0
185 #define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
186 #define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
187 #define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
188 #define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
190 #define INTMASK2_VIDRM_SHIFT 5
191 #define INTMASK2_VBVOLT_SHIFT 4
192 #define INTMASK2_DXOVP_SHIFT 3
193 #define INTMASK2_DCDTMR_SHIFT 2
194 #define INTMASK2_CHGDETRUN_SHIFT 1
195 #define INTMASK2_CHGTYP_SHIFT 0
196 #define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
197 #define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
198 #define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
199 #define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
200 #define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
201 #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
203 /* MAX77693 MUIC - STATUS1~3 Register */
204 #define STATUS1_ADC_SHIFT (0)
205 #define STATUS1_ADCLOW_SHIFT (5)
206 #define STATUS1_ADCERR_SHIFT (6)
207 #define STATUS1_ADC1K_SHIFT (7)
208 #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
209 #define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
210 #define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
211 #define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
213 #define STATUS2_CHGTYP_SHIFT (0)
214 #define STATUS2_CHGDETRUN_SHIFT (3)
215 #define STATUS2_DCDTMR_SHIFT (4)
216 #define STATUS2_DXOVP_SHIFT (5)
217 #define STATUS2_VBVOLT_SHIFT (6)
218 #define STATUS2_VIDRM_SHIFT (7)
219 #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
220 #define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
221 #define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
222 #define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
223 #define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
224 #define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
226 #define STATUS3_OVP_SHIFT (2)
227 #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
229 /* MAX77693 CDETCTRL1~2 register */
230 #define CDETCTRL1_CHGDETEN_SHIFT (0)
231 #define CDETCTRL1_CHGTYPMAN_SHIFT (1)
232 #define CDETCTRL1_DCDEN_SHIFT (2)
233 #define CDETCTRL1_DCD2SCT_SHIFT (3)
234 #define CDETCTRL1_CDDELAY_SHIFT (4)
235 #define CDETCTRL1_DCDCPL_SHIFT (5)
236 #define CDETCTRL1_CDPDET_SHIFT (7)
237 #define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
238 #define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
239 #define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
240 #define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
241 #define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
242 #define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
243 #define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
245 #define CDETCTRL2_VIDRMEN_SHIFT (1)
246 #define CDETCTRL2_DXOVPEN_SHIFT (3)
247 #define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
248 #define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
250 /* MAX77693 MUIC - CONTROL1~3 register */
251 #define COMN1SW_SHIFT (0)
252 #define COMP2SW_SHIFT (3)
253 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
254 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
255 #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
256 #define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
257 | (1 << COMN1SW_SHIFT))
258 #define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
259 | (2 << COMN1SW_SHIFT))
260 #define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
261 | (3 << COMN1SW_SHIFT))
262 #define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
263 | (0 << COMN1SW_SHIFT))
265 #define CONTROL2_LOWPWR_SHIFT (0)
266 #define CONTROL2_ADCEN_SHIFT (1)
267 #define CONTROL2_CPEN_SHIFT (2)
268 #define CONTROL2_SFOUTASRT_SHIFT (3)
269 #define CONTROL2_SFOUTORD_SHIFT (4)
270 #define CONTROL2_ACCDET_SHIFT (5)
271 #define CONTROL2_USBCPINT_SHIFT (6)
272 #define CONTROL2_RCPS_SHIFT (7)
273 #define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
274 #define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
275 #define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
276 #define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
277 #define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
278 #define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
279 #define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
280 #define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
282 #define CONTROL3_JIGSET_SHIFT (0)
283 #define CONTROL3_BTLDSET_SHIFT (2)
284 #define CONTROL3_ADCDBSET_SHIFT (4)
285 #define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
286 #define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
287 #define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
289 /* Slave addr = 0x90: Haptic */
290 enum max77693_haptic_reg
{
291 MAX77693_HAPTIC_REG_STATUS
= 0x00,
292 MAX77693_HAPTIC_REG_CONFIG1
= 0x01,
293 MAX77693_HAPTIC_REG_CONFIG2
= 0x02,
294 MAX77693_HAPTIC_REG_CONFIG_CHNL
= 0x03,
295 MAX77693_HAPTIC_REG_CONFG_CYC1
= 0x04,
296 MAX77693_HAPTIC_REG_CONFG_CYC2
= 0x05,
297 MAX77693_HAPTIC_REG_CONFIG_PER1
= 0x06,
298 MAX77693_HAPTIC_REG_CONFIG_PER2
= 0x07,
299 MAX77693_HAPTIC_REG_CONFIG_PER3
= 0x08,
300 MAX77693_HAPTIC_REG_CONFIG_PER4
= 0x09,
301 MAX77693_HAPTIC_REG_CONFIG_DUTY1
= 0x0A,
302 MAX77693_HAPTIC_REG_CONFIG_DUTY2
= 0x0B,
303 MAX77693_HAPTIC_REG_CONFIG_PWM1
= 0x0C,
304 MAX77693_HAPTIC_REG_CONFIG_PWM2
= 0x0D,
305 MAX77693_HAPTIC_REG_CONFIG_PWM3
= 0x0E,
306 MAX77693_HAPTIC_REG_CONFIG_PWM4
= 0x0F,
307 MAX77693_HAPTIC_REG_REV
= 0x10,
309 MAX77693_HAPTIC_REG_END
,
312 /* max77693-pmic LSCNFG configuraton register */
313 #define MAX77693_PMIC_LOW_SYS_MASK 0x80
314 #define MAX77693_PMIC_LOW_SYS_SHIFT 7
316 /* max77693-haptic configuration register */
317 #define MAX77693_CONFIG2_MODE 7
318 #define MAX77693_CONFIG2_MEN 6
319 #define MAX77693_CONFIG2_HTYP 5
321 enum max77693_irq_source
{
329 MAX77693_IRQ_GROUP_NR
,
332 #define SRC_IRQ_CHARGER BIT(0)
333 #define SRC_IRQ_TOP BIT(1)
334 #define SRC_IRQ_FLASH BIT(2)
335 #define SRC_IRQ_MUIC BIT(3)
336 #define SRC_IRQ_ALL (SRC_IRQ_CHARGER | SRC_IRQ_TOP \
337 | SRC_IRQ_FLASH | SRC_IRQ_MUIC)
339 #define LED_IRQ_FLED2_OPEN BIT(0)
340 #define LED_IRQ_FLED2_SHORT BIT(1)
341 #define LED_IRQ_FLED1_OPEN BIT(2)
342 #define LED_IRQ_FLED1_SHORT BIT(3)
343 #define LED_IRQ_MAX_FLASH BIT(4)
345 #define TOPSYS_IRQ_T120C_INT BIT(0)
346 #define TOPSYS_IRQ_T140C_INT BIT(1)
347 #define TOPSYS_IRQ_LOWSYS_INT BIT(3)
349 #define CHG_IRQ_BYP_I BIT(0)
350 #define CHG_IRQ_THM_I BIT(2)
351 #define CHG_IRQ_BAT_I BIT(3)
352 #define CHG_IRQ_CHG_I BIT(4)
353 #define CHG_IRQ_CHGIN_I BIT(6)
355 #define MUIC_IRQ_INT1_ADC BIT(0)
356 #define MUIC_IRQ_INT1_ADC_LOW BIT(1)
357 #define MUIC_IRQ_INT1_ADC_ERR BIT(2)
358 #define MUIC_IRQ_INT1_ADC1K BIT(3)
360 #define MUIC_IRQ_INT2_CHGTYP BIT(0)
361 #define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
362 #define MUIC_IRQ_INT2_DCDTMR BIT(2)
363 #define MUIC_IRQ_INT2_DXOVP BIT(3)
364 #define MUIC_IRQ_INT2_VBVOLT BIT(4)
365 #define MUIC_IRQ_INT2_VIDRM BIT(5)
367 #define MUIC_IRQ_INT3_EOC BIT(0)
368 #define MUIC_IRQ_INT3_CGMBC BIT(1)
369 #define MUIC_IRQ_INT3_OVP BIT(2)
370 #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
371 #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
372 #define MUIC_IRQ_INT3_BAT_DET BIT(5)
376 MAX77693_LED_IRQ_FLED2_OPEN
,
377 MAX77693_LED_IRQ_FLED2_SHORT
,
378 MAX77693_LED_IRQ_FLED1_OPEN
,
379 MAX77693_LED_IRQ_FLED1_SHORT
,
380 MAX77693_LED_IRQ_MAX_FLASH
,
383 MAX77693_TOPSYS_IRQ_T120C_INT
,
384 MAX77693_TOPSYS_IRQ_T140C_INT
,
385 MAX77693_TOPSYS_IRQ_LOWSYS_INT
,
388 MAX77693_CHG_IRQ_BYP_I
,
389 MAX77693_CHG_IRQ_THM_I
,
390 MAX77693_CHG_IRQ_BAT_I
,
391 MAX77693_CHG_IRQ_CHG_I
,
392 MAX77693_CHG_IRQ_CHGIN_I
,
397 enum max77693_irq_muic
{
399 MAX77693_MUIC_IRQ_INT1_ADC
,
400 MAX77693_MUIC_IRQ_INT1_ADC_LOW
,
401 MAX77693_MUIC_IRQ_INT1_ADC_ERR
,
402 MAX77693_MUIC_IRQ_INT1_ADC1K
,
405 MAX77693_MUIC_IRQ_INT2_CHGTYP
,
406 MAX77693_MUIC_IRQ_INT2_CHGDETREUN
,
407 MAX77693_MUIC_IRQ_INT2_DCDTMR
,
408 MAX77693_MUIC_IRQ_INT2_DXOVP
,
409 MAX77693_MUIC_IRQ_INT2_VBVOLT
,
410 MAX77693_MUIC_IRQ_INT2_VIDRM
,
413 MAX77693_MUIC_IRQ_INT3_EOC
,
414 MAX77693_MUIC_IRQ_INT3_CGMBC
,
415 MAX77693_MUIC_IRQ_INT3_OVP
,
416 MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR
,
417 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED
,
418 MAX77693_MUIC_IRQ_INT3_BAT_DET
,
420 MAX77693_MUIC_IRQ_NR
,
423 struct max77693_dev
{
425 struct i2c_client
*i2c
; /* 0xCC , PMIC, Charger, Flash LED */
426 struct i2c_client
*muic
; /* 0x4A , MUIC */
427 struct i2c_client
*haptic
; /* 0x90 , Haptic */
431 struct regmap
*regmap
;
432 struct regmap
*regmap_muic
;
433 struct regmap
*regmap_haptic
;
435 struct regmap_irq_chip_data
*irq_data_led
;
436 struct regmap_irq_chip_data
*irq_data_topsys
;
437 struct regmap_irq_chip_data
*irq_data_charger
;
438 struct regmap_irq_chip_data
*irq_data_muic
;
442 struct mutex irqlock
;
443 int irq_masks_cur
[MAX77693_IRQ_GROUP_NR
];
444 int irq_masks_cache
[MAX77693_IRQ_GROUP_NR
];
447 enum max77693_types
{
451 extern int max77693_irq_init(struct max77693_dev
*max77686
);
452 extern void max77693_irq_exit(struct max77693_dev
*max77686
);
453 extern int max77693_irq_resume(struct max77693_dev
*max77686
);
455 #endif /* __LINUX_MFD_MAX77693_PRIV_H */