4 * Copyright 2011-2013 Texas Instruments Inc.
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Ian Lartey <ian@slimlogic.co.uk>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
16 #ifndef __LINUX_MFD_PALMAS_H
17 #define __LINUX_MFD_PALMAS_H
19 #include <linux/usb/otg.h>
20 #include <linux/leds.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/driver.h>
23 #include <linux/extcon-provider.h>
24 #include <linux/of_gpio.h>
25 #include <linux/usb/phy_companion.h>
27 #define PALMAS_NUM_CLIENTS 3
29 /* The ID_REVISION NUMBERS */
30 #define PALMAS_CHIP_OLD_ID 0x0000
31 #define PALMAS_CHIP_ID 0xC035
32 #define PALMAS_CHIP_CHARGER_ID 0xC036
34 #define TPS65917_RESERVED -1
36 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
37 ((a) == PALMAS_CHIP_ID))
38 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
41 * Palmas PMIC feature types
43 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
46 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
47 * specific feature (above) or not. Return non-zero, if yes.
49 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
50 #define PALMAS_PMIC_HAS(b, f) \
51 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
55 struct palmas_resource
;
57 struct palmas_pmic_driver_data
;
58 struct palmas_pmic_platform_data
;
60 enum palmas_usb_state
{
61 PALMAS_USB_STATE_DISCONNECT
,
62 PALMAS_USB_STATE_VBUS
,
69 struct i2c_client
*i2c_clients
[PALMAS_NUM_CLIENTS
];
70 struct regmap
*regmap
[PALMAS_NUM_CLIENTS
];
75 unsigned int features
;
79 struct mutex irq_lock
;
80 struct regmap_irq_chip_data
*irq_data
;
82 struct palmas_pmic_driver_data
*pmic_ddata
;
85 struct palmas_pmic
*pmic
;
86 struct palmas_gpadc
*gpadc
;
87 struct palmas_resource
*resource
;
88 struct palmas_usb
*usb
;
96 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
97 PALMAS_EXT_CONTROL_ENABLE2 | \
98 PALMAS_EXT_CONTROL_NSLEEP)
100 struct palmas_sleep_requestor_info
{
106 struct palmas_regs_info
{
115 struct palmas_pmic_driver_data
{
122 struct palmas_regs_info
*palmas_regs_info
;
123 struct of_regulator_match
*palmas_matches
;
124 struct palmas_sleep_requestor_info
*sleep_req_info
;
125 int (*smps_register
)(struct palmas_pmic
*pmic
,
126 struct palmas_pmic_driver_data
*ddata
,
127 struct palmas_pmic_platform_data
*pdata
,
128 const char *pdev_name
,
129 struct regulator_config config
);
130 int (*ldo_register
)(struct palmas_pmic
*pmic
,
131 struct palmas_pmic_driver_data
*ddata
,
132 struct palmas_pmic_platform_data
*pdata
,
133 const char *pdev_name
,
134 struct regulator_config config
);
137 struct palmas_adc_wakeup_property
{
138 int adc_channel_number
;
139 int adc_high_threshold
;
140 int adc_low_threshold
;
143 struct palmas_gpadc_platform_data
{
144 /* Channel 3 current source is only enabled during conversion */
145 int ch3_current
; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
147 /* Channel 0 current source can be used for battery detection.
148 * If used for battery detection this will cause a permanent current
149 * consumption depending on current level set here.
151 int ch0_current
; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
152 bool extended_delay
; /* use extended delay for conversion */
154 /* default BAT_REMOVAL_DAT setting on device probe */
157 /* Sets the START_POLARITY bit in the RT_CTRL register */
160 int auto_conversion_period_ms
;
161 struct palmas_adc_wakeup_property
*adc_wakeup1_data
;
162 struct palmas_adc_wakeup_property
*adc_wakeup2_data
;
165 struct palmas_reg_init
{
166 /* warm_rest controls the voltage levels after a warm reset
168 * 0: reload default values from OTP on warm reset
169 * 1: maintain voltage from VSEL on warm reset
173 /* roof_floor controls whether the regulator uses the i2c style
174 * of DVS or uses the method where a GPIO or other control method is
175 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
179 * 0: i2c selection of voltage
180 * 1: pin selection of voltage.
186 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
203 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
204 * register. Set this is the default voltage set in OTP needs
211 enum palmas_regulators
{
212 /* SMPS regulators */
222 PALMAS_REG_SMPS10_OUT2
,
223 PALMAS_REG_SMPS10_OUT1
,
236 /* External regulators */
242 /* Total number of regulators */
246 enum tps65917_regulators
{
247 /* SMPS regulators */
264 /* Total number of regulators */
268 /* External controll signal name */
270 PALMAS_EXT_CONTROL_ENABLE1
= 0x1,
271 PALMAS_EXT_CONTROL_ENABLE2
= 0x2,
272 PALMAS_EXT_CONTROL_NSLEEP
= 0x4,
276 * Palmas device resources can be controlled externally for
277 * enabling/disabling it rather than register write through i2c.
278 * Add the external controlled requestor ID for different resources.
280 enum palmas_external_requestor_id
{
281 PALMAS_EXTERNAL_REQSTR_ID_REGEN1
,
282 PALMAS_EXTERNAL_REQSTR_ID_REGEN2
,
283 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1
,
284 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2
,
285 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG
,
286 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO
,
287 PALMAS_EXTERNAL_REQSTR_ID_REGEN3
,
288 PALMAS_EXTERNAL_REQSTR_ID_SMPS12
,
289 PALMAS_EXTERNAL_REQSTR_ID_SMPS3
,
290 PALMAS_EXTERNAL_REQSTR_ID_SMPS45
,
291 PALMAS_EXTERNAL_REQSTR_ID_SMPS6
,
292 PALMAS_EXTERNAL_REQSTR_ID_SMPS7
,
293 PALMAS_EXTERNAL_REQSTR_ID_SMPS8
,
294 PALMAS_EXTERNAL_REQSTR_ID_SMPS9
,
295 PALMAS_EXTERNAL_REQSTR_ID_SMPS10
,
296 PALMAS_EXTERNAL_REQSTR_ID_LDO1
,
297 PALMAS_EXTERNAL_REQSTR_ID_LDO2
,
298 PALMAS_EXTERNAL_REQSTR_ID_LDO3
,
299 PALMAS_EXTERNAL_REQSTR_ID_LDO4
,
300 PALMAS_EXTERNAL_REQSTR_ID_LDO5
,
301 PALMAS_EXTERNAL_REQSTR_ID_LDO6
,
302 PALMAS_EXTERNAL_REQSTR_ID_LDO7
,
303 PALMAS_EXTERNAL_REQSTR_ID_LDO8
,
304 PALMAS_EXTERNAL_REQSTR_ID_LDO9
,
305 PALMAS_EXTERNAL_REQSTR_ID_LDOLN
,
306 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB
,
309 PALMAS_EXTERNAL_REQSTR_ID_MAX
,
312 enum tps65917_external_requestor_id
{
313 TPS65917_EXTERNAL_REQSTR_ID_REGEN1
,
314 TPS65917_EXTERNAL_REQSTR_ID_REGEN2
,
315 TPS65917_EXTERNAL_REQSTR_ID_REGEN3
,
316 TPS65917_EXTERNAL_REQSTR_ID_SMPS1
,
317 TPS65917_EXTERNAL_REQSTR_ID_SMPS2
,
318 TPS65917_EXTERNAL_REQSTR_ID_SMPS3
,
319 TPS65917_EXTERNAL_REQSTR_ID_SMPS4
,
320 TPS65917_EXTERNAL_REQSTR_ID_SMPS5
,
321 TPS65917_EXTERNAL_REQSTR_ID_SMPS12
,
322 TPS65917_EXTERNAL_REQSTR_ID_LDO1
,
323 TPS65917_EXTERNAL_REQSTR_ID_LDO2
,
324 TPS65917_EXTERNAL_REQSTR_ID_LDO3
,
325 TPS65917_EXTERNAL_REQSTR_ID_LDO4
,
326 TPS65917_EXTERNAL_REQSTR_ID_LDO5
,
328 TPS65917_EXTERNAL_REQSTR_ID_MAX
,
331 struct palmas_pmic_platform_data
{
332 /* An array of pointers to regulator init data indexed by regulator
335 struct regulator_init_data
*reg_data
[PALMAS_NUM_REGS
];
337 /* An array of pointers to structures containing sleep mode and DVS
338 * configuration for regulators indexed by ID
340 struct palmas_reg_init
*reg_init
[PALMAS_NUM_REGS
];
342 /* use LDO6 for vibrator control */
345 /* Enable tracking mode of LDO8 */
346 bool enable_ldo8_tracking
;
349 struct palmas_usb_platform_data
{
350 /* Do we enable the wakeup comparator on probe */
354 struct palmas_resource_platform_data
{
355 int regen1_mode_sleep
;
356 int regen2_mode_sleep
;
357 int sysen1_mode_sleep
;
358 int sysen2_mode_sleep
;
360 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
362 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
364 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
366 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
369 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
371 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
373 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
375 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
378 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
380 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
382 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
384 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
388 struct palmas_clk_platform_data
{
389 int clk32kg_mode_sleep
;
390 int clk32kgaudio_mode_sleep
;
393 struct palmas_platform_data
{
397 /* bit value to be loaded to the POWER_CTRL register */
401 * boolean to select if we want to configure muxing here
402 * then the two value to load into the registers if true
408 struct palmas_pmic_platform_data
*pmic_pdata
;
409 struct palmas_gpadc_platform_data
*gpadc_pdata
;
410 struct palmas_usb_platform_data
*usb_pdata
;
411 struct palmas_resource_platform_data
*resource_pdata
;
412 struct palmas_clk_platform_data
*clk_pdata
;
415 struct palmas_gpadc_calibration
{
421 #define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name
423 struct palmas_gpadc_result
{
429 #define PALMAS_MAX_CHANNELS 16
431 /* Define the tps65917 IRQ numbers */
436 TPS65917_LONG_PRESS_KEY_IRQ
,
438 TPS65917_PWRDOWN_IRQ
,
440 TPS65917_VSYS_MON_IRQ
,
444 TPS65917_OTP_ERROR_IRQ
,
447 TPS65917_RESET_IN_IRQ
,
452 TPS65917_GPADC_AUTO_0_IRQ
,
453 TPS65917_GPADC_AUTO_1_IRQ
,
454 TPS65917_GPADC_EOC_SW_IRQ
,
469 /* Total Number IRQs */
473 /* Define the palmas IRQ numbers */
476 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ
,
478 PALMAS_LONG_PRESS_KEY_IRQ
,
485 PALMAS_RTC_ALARM_IRQ
,
486 PALMAS_RTC_TIMER_IRQ
,
488 PALMAS_BATREMOVAL_IRQ
,
494 PALMAS_GPADC_AUTO_0_IRQ
,
495 PALMAS_GPADC_AUTO_1_IRQ
,
496 PALMAS_GPADC_EOC_SW_IRQ
,
497 PALMAS_GPADC_EOC_RT_IRQ
,
511 /* Total Number IRQs */
515 /* Palmas GPADC Channels */
536 /* Palmas GPADC Channel0 Current Source */
538 PALMAS_ADC_CH0_CURRENT_SRC_0
,
539 PALMAS_ADC_CH0_CURRENT_SRC_5
,
540 PALMAS_ADC_CH0_CURRENT_SRC_15
,
541 PALMAS_ADC_CH0_CURRENT_SRC_20
,
544 /* Palmas GPADC Channel3 Current Source */
546 PALMAS_ADC_CH3_CURRENT_SRC_0
,
547 PALMAS_ADC_CH3_CURRENT_SRC_10
,
548 PALMAS_ADC_CH3_CURRENT_SRC_400
,
549 PALMAS_ADC_CH3_CURRENT_SRC_800
,
553 struct palmas
*palmas
;
555 struct regulator_desc desc
[PALMAS_NUM_REGS
];
562 int range
[PALMAS_REG_SMPS10_OUT1
];
563 unsigned int ramp_delay
[PALMAS_REG_SMPS10_OUT1
];
564 unsigned int current_reg_mode
[PALMAS_REG_SMPS10_OUT1
];
567 struct palmas_resource
{
568 struct palmas
*palmas
;
573 struct palmas
*palmas
;
576 struct extcon_dev
*edev
;
585 struct gpio_desc
*id_gpiod
;
586 struct gpio_desc
*vbus_gpiod
;
587 unsigned long sw_debounce_jiffies
;
588 struct delayed_work wq_detectid
;
590 enum palmas_usb_state linkstat
;
592 bool enable_vbus_detection
;
593 bool enable_id_detection
;
594 bool enable_gpio_id_detection
;
595 bool enable_gpio_vbus_detection
;
598 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
600 enum usb_irq_events
{
601 /* Wakeup events from INT3 */
602 PALMAS_USB_ID_WAKEPUP
,
603 PALMAS_USB_VBUS_WAKEUP
,
615 N_PALMAS_USB_ID_FLOAT
,
617 /* VBUS_OTG_EVENTS */
618 PALMAS_USB_VB_SESS_END
,
619 N_PALMAS_USB_VB_SESS_END
,
620 PALMAS_USB_VB_SESS_VLD
,
621 N_PALMAS_USB_VB_SESS_VLD
,
622 PALMAS_USB_VA_SESS_VLD
,
623 N_PALMAS_USB_VA_SESS_VLD
,
624 PALMAS_USB_VA_VBUS_VLD
,
625 N_PALMAS_USB_VA_VBUS_VLD
,
627 N_PALMAS_USB_VADP_SNS
,
629 N_PALMAS_USB_VADP_PRB
,
630 PALMAS_USB_VOTG_SESS_VLD
,
631 N_PALMAS_USB_VOTG_SESS_VLD
,
634 /* defines so we can store the mux settings */
635 #define PALMAS_GPIO_0_MUXED (1 << 0)
636 #define PALMAS_GPIO_1_MUXED (1 << 1)
637 #define PALMAS_GPIO_2_MUXED (1 << 2)
638 #define PALMAS_GPIO_3_MUXED (1 << 3)
639 #define PALMAS_GPIO_4_MUXED (1 << 4)
640 #define PALMAS_GPIO_5_MUXED (1 << 5)
641 #define PALMAS_GPIO_6_MUXED (1 << 6)
642 #define PALMAS_GPIO_7_MUXED (1 << 7)
644 #define PALMAS_LED1_MUXED (1 << 0)
645 #define PALMAS_LED2_MUXED (1 << 1)
647 #define PALMAS_PWM1_MUXED (1 << 0)
648 #define PALMAS_PWM2_MUXED (1 << 1)
650 /* helper macro to get correct slave number */
651 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
652 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
654 /* Base addresses of IP blocks in Palmas */
655 #define PALMAS_SMPS_DVS_BASE 0x020
656 #define PALMAS_RTC_BASE 0x100
657 #define PALMAS_VALIDITY_BASE 0x118
658 #define PALMAS_SMPS_BASE 0x120
659 #define PALMAS_LDO_BASE 0x150
660 #define PALMAS_DVFS_BASE 0x180
661 #define PALMAS_PMU_CONTROL_BASE 0x1A0
662 #define PALMAS_RESOURCE_BASE 0x1D4
663 #define PALMAS_PU_PD_OD_BASE 0x1F0
664 #define PALMAS_LED_BASE 0x200
665 #define PALMAS_INTERRUPT_BASE 0x210
666 #define PALMAS_USB_OTG_BASE 0x250
667 #define PALMAS_VIBRATOR_BASE 0x270
668 #define PALMAS_GPIO_BASE 0x280
669 #define PALMAS_USB_BASE 0x290
670 #define PALMAS_GPADC_BASE 0x2C0
671 #define PALMAS_TRIM_GPADC_BASE 0x3CD
673 /* Registers for function RTC */
674 #define PALMAS_SECONDS_REG 0x00
675 #define PALMAS_MINUTES_REG 0x01
676 #define PALMAS_HOURS_REG 0x02
677 #define PALMAS_DAYS_REG 0x03
678 #define PALMAS_MONTHS_REG 0x04
679 #define PALMAS_YEARS_REG 0x05
680 #define PALMAS_WEEKS_REG 0x06
681 #define PALMAS_ALARM_SECONDS_REG 0x08
682 #define PALMAS_ALARM_MINUTES_REG 0x09
683 #define PALMAS_ALARM_HOURS_REG 0x0A
684 #define PALMAS_ALARM_DAYS_REG 0x0B
685 #define PALMAS_ALARM_MONTHS_REG 0x0C
686 #define PALMAS_ALARM_YEARS_REG 0x0D
687 #define PALMAS_RTC_CTRL_REG 0x10
688 #define PALMAS_RTC_STATUS_REG 0x11
689 #define PALMAS_RTC_INTERRUPTS_REG 0x12
690 #define PALMAS_RTC_COMP_LSB_REG 0x13
691 #define PALMAS_RTC_COMP_MSB_REG 0x14
692 #define PALMAS_RTC_RES_PROG_REG 0x15
693 #define PALMAS_RTC_RESET_STATUS_REG 0x16
695 /* Bit definitions for SECONDS_REG */
696 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
697 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
698 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
699 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
701 /* Bit definitions for MINUTES_REG */
702 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
703 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
704 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
705 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
707 /* Bit definitions for HOURS_REG */
708 #define PALMAS_HOURS_REG_PM_NAM 0x80
709 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
710 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
711 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
712 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
713 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
715 /* Bit definitions for DAYS_REG */
716 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
717 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
718 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F
719 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
721 /* Bit definitions for MONTHS_REG */
722 #define PALMAS_MONTHS_REG_MONTH1 0x10
723 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
724 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
725 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
727 /* Bit definitions for YEARS_REG */
728 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
729 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
730 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
731 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
733 /* Bit definitions for WEEKS_REG */
734 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
735 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
737 /* Bit definitions for ALARM_SECONDS_REG */
738 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
739 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
740 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
741 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
743 /* Bit definitions for ALARM_MINUTES_REG */
744 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
745 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
746 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
747 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
749 /* Bit definitions for ALARM_HOURS_REG */
750 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
751 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
752 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
753 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
754 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
755 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
757 /* Bit definitions for ALARM_DAYS_REG */
758 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
759 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
760 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
761 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
763 /* Bit definitions for ALARM_MONTHS_REG */
764 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
765 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
766 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
767 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
769 /* Bit definitions for ALARM_YEARS_REG */
770 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
771 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
772 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
773 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
775 /* Bit definitions for RTC_CTRL_REG */
776 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
777 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
778 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
779 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
780 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
781 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
782 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
783 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
784 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
785 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
786 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
787 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
788 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
789 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
790 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
791 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
793 /* Bit definitions for RTC_STATUS_REG */
794 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
795 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
796 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
797 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
798 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
799 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
800 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
801 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
802 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
803 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
804 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
805 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
806 #define PALMAS_RTC_STATUS_REG_RUN 0x02
807 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
809 /* Bit definitions for RTC_INTERRUPTS_REG */
810 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
811 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
812 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
813 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
814 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
815 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
816 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
817 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
819 /* Bit definitions for RTC_COMP_LSB_REG */
820 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
821 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
823 /* Bit definitions for RTC_COMP_MSB_REG */
824 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
825 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
827 /* Bit definitions for RTC_RES_PROG_REG */
828 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
829 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
831 /* Bit definitions for RTC_RESET_STATUS_REG */
832 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
833 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
835 /* Registers for function BACKUP */
836 #define PALMAS_BACKUP0 0x00
837 #define PALMAS_BACKUP1 0x01
838 #define PALMAS_BACKUP2 0x02
839 #define PALMAS_BACKUP3 0x03
840 #define PALMAS_BACKUP4 0x04
841 #define PALMAS_BACKUP5 0x05
842 #define PALMAS_BACKUP6 0x06
843 #define PALMAS_BACKUP7 0x07
845 /* Bit definitions for BACKUP0 */
846 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF
847 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
849 /* Bit definitions for BACKUP1 */
850 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF
851 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
853 /* Bit definitions for BACKUP2 */
854 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF
855 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
857 /* Bit definitions for BACKUP3 */
858 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF
859 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
861 /* Bit definitions for BACKUP4 */
862 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF
863 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
865 /* Bit definitions for BACKUP5 */
866 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF
867 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
869 /* Bit definitions for BACKUP6 */
870 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF
871 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
873 /* Bit definitions for BACKUP7 */
874 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF
875 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
877 /* Registers for function SMPS */
878 #define PALMAS_SMPS12_CTRL 0x00
879 #define PALMAS_SMPS12_TSTEP 0x01
880 #define PALMAS_SMPS12_FORCE 0x02
881 #define PALMAS_SMPS12_VOLTAGE 0x03
882 #define PALMAS_SMPS3_CTRL 0x04
883 #define PALMAS_SMPS3_VOLTAGE 0x07
884 #define PALMAS_SMPS45_CTRL 0x08
885 #define PALMAS_SMPS45_TSTEP 0x09
886 #define PALMAS_SMPS45_FORCE 0x0A
887 #define PALMAS_SMPS45_VOLTAGE 0x0B
888 #define PALMAS_SMPS6_CTRL 0x0C
889 #define PALMAS_SMPS6_TSTEP 0x0D
890 #define PALMAS_SMPS6_FORCE 0x0E
891 #define PALMAS_SMPS6_VOLTAGE 0x0F
892 #define PALMAS_SMPS7_CTRL 0x10
893 #define PALMAS_SMPS7_VOLTAGE 0x13
894 #define PALMAS_SMPS8_CTRL 0x14
895 #define PALMAS_SMPS8_TSTEP 0x15
896 #define PALMAS_SMPS8_FORCE 0x16
897 #define PALMAS_SMPS8_VOLTAGE 0x17
898 #define PALMAS_SMPS9_CTRL 0x18
899 #define PALMAS_SMPS9_VOLTAGE 0x1B
900 #define PALMAS_SMPS10_CTRL 0x1C
901 #define PALMAS_SMPS10_STATUS 0x1F
902 #define PALMAS_SMPS_CTRL 0x24
903 #define PALMAS_SMPS_PD_CTRL 0x25
904 #define PALMAS_SMPS_DITHER_EN 0x26
905 #define PALMAS_SMPS_THERMAL_EN 0x27
906 #define PALMAS_SMPS_THERMAL_STATUS 0x28
907 #define PALMAS_SMPS_SHORT_STATUS 0x29
908 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
909 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
910 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
912 /* Bit definitions for SMPS12_CTRL */
913 #define PALMAS_SMPS12_CTRL_WR_S 0x80
914 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
915 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
916 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
917 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
918 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
919 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
920 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
921 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
922 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
924 /* Bit definitions for SMPS12_TSTEP */
925 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
926 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
928 /* Bit definitions for SMPS12_FORCE */
929 #define PALMAS_SMPS12_FORCE_CMD 0x80
930 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
931 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
932 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
934 /* Bit definitions for SMPS12_VOLTAGE */
935 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
936 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
937 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
938 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
940 /* Bit definitions for SMPS3_CTRL */
941 #define PALMAS_SMPS3_CTRL_WR_S 0x80
942 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
943 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
944 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
945 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
946 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
947 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
948 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
950 /* Bit definitions for SMPS3_VOLTAGE */
951 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
952 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
953 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
954 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
956 /* Bit definitions for SMPS45_CTRL */
957 #define PALMAS_SMPS45_CTRL_WR_S 0x80
958 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
959 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
960 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
961 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
962 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
963 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
964 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
965 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
966 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
968 /* Bit definitions for SMPS45_TSTEP */
969 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
970 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
972 /* Bit definitions for SMPS45_FORCE */
973 #define PALMAS_SMPS45_FORCE_CMD 0x80
974 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
975 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
976 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
978 /* Bit definitions for SMPS45_VOLTAGE */
979 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
980 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
981 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
982 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
984 /* Bit definitions for SMPS6_CTRL */
985 #define PALMAS_SMPS6_CTRL_WR_S 0x80
986 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
987 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
988 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
989 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
990 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
991 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
992 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
993 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
994 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
996 /* Bit definitions for SMPS6_TSTEP */
997 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
998 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
1000 /* Bit definitions for SMPS6_FORCE */
1001 #define PALMAS_SMPS6_FORCE_CMD 0x80
1002 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
1003 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
1004 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
1006 /* Bit definitions for SMPS6_VOLTAGE */
1007 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
1008 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
1009 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
1010 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
1012 /* Bit definitions for SMPS7_CTRL */
1013 #define PALMAS_SMPS7_CTRL_WR_S 0x80
1014 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
1015 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
1016 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
1017 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
1018 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
1019 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
1020 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
1022 /* Bit definitions for SMPS7_VOLTAGE */
1023 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
1024 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
1025 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
1026 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
1028 /* Bit definitions for SMPS8_CTRL */
1029 #define PALMAS_SMPS8_CTRL_WR_S 0x80
1030 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
1031 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
1032 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
1033 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
1034 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
1035 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
1036 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
1037 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
1038 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
1040 /* Bit definitions for SMPS8_TSTEP */
1041 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
1042 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
1044 /* Bit definitions for SMPS8_FORCE */
1045 #define PALMAS_SMPS8_FORCE_CMD 0x80
1046 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
1047 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
1048 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
1050 /* Bit definitions for SMPS8_VOLTAGE */
1051 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
1052 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
1053 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
1054 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
1056 /* Bit definitions for SMPS9_CTRL */
1057 #define PALMAS_SMPS9_CTRL_WR_S 0x80
1058 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
1059 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
1060 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
1061 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
1062 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
1063 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
1064 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
1066 /* Bit definitions for SMPS9_VOLTAGE */
1067 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
1068 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1069 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1070 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
1072 /* Bit definitions for SMPS10_CTRL */
1073 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
1074 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1075 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1076 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
1078 /* Bit definitions for SMPS10_STATUS */
1079 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1080 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
1082 /* Bit definitions for SMPS_CTRL */
1083 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
1084 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
1085 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
1086 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
1087 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
1088 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
1089 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
1090 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
1092 /* Bit definitions for SMPS_PD_CTRL */
1093 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
1094 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
1095 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
1096 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
1097 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
1098 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
1099 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
1100 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
1101 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
1102 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
1103 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
1104 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
1105 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
1106 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
1108 /* Bit definitions for SMPS_THERMAL_EN */
1109 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
1110 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
1111 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
1112 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
1113 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
1114 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
1115 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
1116 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
1117 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
1118 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
1120 /* Bit definitions for SMPS_THERMAL_STATUS */
1121 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
1122 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
1123 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
1124 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
1125 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
1126 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
1127 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
1128 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
1129 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
1130 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
1132 /* Bit definitions for SMPS_SHORT_STATUS */
1133 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
1134 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
1135 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
1136 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
1137 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
1138 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
1139 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
1140 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
1141 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
1142 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
1143 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
1144 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
1145 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
1146 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
1147 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
1148 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
1150 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1151 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
1152 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
1153 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
1154 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
1155 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
1156 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
1157 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
1158 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
1159 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
1160 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
1161 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
1162 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
1163 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
1164 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
1166 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1167 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1168 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1169 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1170 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1171 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1172 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1173 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1174 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1175 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1176 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1177 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1178 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1179 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1180 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1181 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1182 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1184 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1185 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1186 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1187 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1188 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1189 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1190 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1191 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1192 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1194 /* Registers for function LDO */
1195 #define PALMAS_LDO1_CTRL 0x00
1196 #define PALMAS_LDO1_VOLTAGE 0x01
1197 #define PALMAS_LDO2_CTRL 0x02
1198 #define PALMAS_LDO2_VOLTAGE 0x03
1199 #define PALMAS_LDO3_CTRL 0x04
1200 #define PALMAS_LDO3_VOLTAGE 0x05
1201 #define PALMAS_LDO4_CTRL 0x06
1202 #define PALMAS_LDO4_VOLTAGE 0x07
1203 #define PALMAS_LDO5_CTRL 0x08
1204 #define PALMAS_LDO5_VOLTAGE 0x09
1205 #define PALMAS_LDO6_CTRL 0x0A
1206 #define PALMAS_LDO6_VOLTAGE 0x0B
1207 #define PALMAS_LDO7_CTRL 0x0C
1208 #define PALMAS_LDO7_VOLTAGE 0x0D
1209 #define PALMAS_LDO8_CTRL 0x0E
1210 #define PALMAS_LDO8_VOLTAGE 0x0F
1211 #define PALMAS_LDO9_CTRL 0x10
1212 #define PALMAS_LDO9_VOLTAGE 0x11
1213 #define PALMAS_LDOLN_CTRL 0x12
1214 #define PALMAS_LDOLN_VOLTAGE 0x13
1215 #define PALMAS_LDOUSB_CTRL 0x14
1216 #define PALMAS_LDOUSB_VOLTAGE 0x15
1217 #define PALMAS_LDO_CTRL 0x1A
1218 #define PALMAS_LDO_PD_CTRL1 0x1B
1219 #define PALMAS_LDO_PD_CTRL2 0x1C
1220 #define PALMAS_LDO_SHORT_STATUS1 0x1D
1221 #define PALMAS_LDO_SHORT_STATUS2 0x1E
1223 /* Bit definitions for LDO1_CTRL */
1224 #define PALMAS_LDO1_CTRL_WR_S 0x80
1225 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1226 #define PALMAS_LDO1_CTRL_STATUS 0x10
1227 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1228 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1229 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1230 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1231 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1233 /* Bit definitions for LDO1_VOLTAGE */
1234 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1235 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1237 /* Bit definitions for LDO2_CTRL */
1238 #define PALMAS_LDO2_CTRL_WR_S 0x80
1239 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1240 #define PALMAS_LDO2_CTRL_STATUS 0x10
1241 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1242 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1243 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1244 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1245 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1247 /* Bit definitions for LDO2_VOLTAGE */
1248 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1249 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1251 /* Bit definitions for LDO3_CTRL */
1252 #define PALMAS_LDO3_CTRL_WR_S 0x80
1253 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1254 #define PALMAS_LDO3_CTRL_STATUS 0x10
1255 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1256 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1257 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1258 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1259 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1261 /* Bit definitions for LDO3_VOLTAGE */
1262 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1263 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1265 /* Bit definitions for LDO4_CTRL */
1266 #define PALMAS_LDO4_CTRL_WR_S 0x80
1267 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1268 #define PALMAS_LDO4_CTRL_STATUS 0x10
1269 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1270 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1271 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1272 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1273 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1275 /* Bit definitions for LDO4_VOLTAGE */
1276 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1277 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1279 /* Bit definitions for LDO5_CTRL */
1280 #define PALMAS_LDO5_CTRL_WR_S 0x80
1281 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1282 #define PALMAS_LDO5_CTRL_STATUS 0x10
1283 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1284 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1285 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1286 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1287 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1289 /* Bit definitions for LDO5_VOLTAGE */
1290 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1291 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1293 /* Bit definitions for LDO6_CTRL */
1294 #define PALMAS_LDO6_CTRL_WR_S 0x80
1295 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1296 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1297 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1298 #define PALMAS_LDO6_CTRL_STATUS 0x10
1299 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1300 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1301 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1302 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1303 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1305 /* Bit definitions for LDO6_VOLTAGE */
1306 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1307 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1309 /* Bit definitions for LDO7_CTRL */
1310 #define PALMAS_LDO7_CTRL_WR_S 0x80
1311 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1312 #define PALMAS_LDO7_CTRL_STATUS 0x10
1313 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1314 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1315 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1316 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1317 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1319 /* Bit definitions for LDO7_VOLTAGE */
1320 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1321 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1323 /* Bit definitions for LDO8_CTRL */
1324 #define PALMAS_LDO8_CTRL_WR_S 0x80
1325 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1326 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1327 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1328 #define PALMAS_LDO8_CTRL_STATUS 0x10
1329 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1330 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1331 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1332 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1333 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1335 /* Bit definitions for LDO8_VOLTAGE */
1336 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1337 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1339 /* Bit definitions for LDO9_CTRL */
1340 #define PALMAS_LDO9_CTRL_WR_S 0x80
1341 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1342 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1343 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1344 #define PALMAS_LDO9_CTRL_STATUS 0x10
1345 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1346 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1347 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1348 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1349 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1351 /* Bit definitions for LDO9_VOLTAGE */
1352 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1353 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1355 /* Bit definitions for LDOLN_CTRL */
1356 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1357 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1358 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1359 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1360 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1361 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1362 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1363 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1365 /* Bit definitions for LDOLN_VOLTAGE */
1366 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1367 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1369 /* Bit definitions for LDOUSB_CTRL */
1370 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1371 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1372 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1373 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1374 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1375 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1376 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1377 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1379 /* Bit definitions for LDOUSB_VOLTAGE */
1380 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1381 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1383 /* Bit definitions for LDO_CTRL */
1384 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1385 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1387 /* Bit definitions for LDO_PD_CTRL1 */
1388 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1389 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1390 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1391 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1392 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1393 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1394 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1395 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1396 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1397 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1398 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1399 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1400 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1401 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1402 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1403 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1405 /* Bit definitions for LDO_PD_CTRL2 */
1406 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1407 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1408 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1409 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1410 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1411 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1413 /* Bit definitions for LDO_SHORT_STATUS1 */
1414 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1415 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1416 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1417 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1418 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1419 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1420 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1421 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1422 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1423 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1424 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1425 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1426 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1427 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1428 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1429 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1431 /* Bit definitions for LDO_SHORT_STATUS2 */
1432 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1433 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1434 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1435 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1436 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1437 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1438 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1439 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1441 /* Registers for function PMU_CONTROL */
1442 #define PALMAS_DEV_CTRL 0x00
1443 #define PALMAS_POWER_CTRL 0x01
1444 #define PALMAS_VSYS_LO 0x02
1445 #define PALMAS_VSYS_MON 0x03
1446 #define PALMAS_VBAT_MON 0x04
1447 #define PALMAS_WATCHDOG 0x05
1448 #define PALMAS_BOOT_STATUS 0x06
1449 #define PALMAS_BATTERY_BOUNCE 0x07
1450 #define PALMAS_BACKUP_BATTERY_CTRL 0x08
1451 #define PALMAS_LONG_PRESS_KEY 0x09
1452 #define PALMAS_OSC_THERM_CTRL 0x0A
1453 #define PALMAS_BATDEBOUNCING 0x0B
1454 #define PALMAS_SWOFF_HWRST 0x0F
1455 #define PALMAS_SWOFF_COLDRST 0x10
1456 #define PALMAS_SWOFF_STATUS 0x11
1457 #define PALMAS_PMU_CONFIG 0x12
1458 #define PALMAS_SPARE 0x14
1459 #define PALMAS_PMU_SECONDARY_INT 0x15
1460 #define PALMAS_SW_REVISION 0x17
1461 #define PALMAS_EXT_CHRG_CTRL 0x18
1462 #define PALMAS_PMU_SECONDARY_INT2 0x19
1464 /* Bit definitions for DEV_CTRL */
1465 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1466 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1467 #define PALMAS_DEV_CTRL_SW_RST 0x02
1468 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1469 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1470 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1472 /* Bit definitions for POWER_CTRL */
1473 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1474 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1475 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1476 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1477 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1478 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1480 /* Bit definitions for VSYS_LO */
1481 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1482 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1484 /* Bit definitions for VSYS_MON */
1485 #define PALMAS_VSYS_MON_ENABLE 0x80
1486 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1487 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1488 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1490 /* Bit definitions for VBAT_MON */
1491 #define PALMAS_VBAT_MON_ENABLE 0x80
1492 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1493 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1494 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1496 /* Bit definitions for WATCHDOG */
1497 #define PALMAS_WATCHDOG_LOCK 0x20
1498 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1499 #define PALMAS_WATCHDOG_ENABLE 0x10
1500 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1501 #define PALMAS_WATCHDOG_MODE 0x08
1502 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1503 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1504 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1506 /* Bit definitions for BOOT_STATUS */
1507 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1508 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1509 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1510 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1512 /* Bit definitions for BATTERY_BOUNCE */
1513 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1514 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1516 /* Bit definitions for BACKUP_BATTERY_CTRL */
1517 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1518 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1519 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1520 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1521 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1522 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1523 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1524 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1525 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1526 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1527 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1528 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1529 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1530 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1532 /* Bit definitions for LONG_PRESS_KEY */
1533 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1534 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1535 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1536 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1537 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1538 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1539 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1540 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1542 /* Bit definitions for OSC_THERM_CTRL */
1543 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1544 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1545 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1546 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1547 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1548 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1549 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1550 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1551 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1552 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1553 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1554 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1555 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1556 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1558 /* Bit definitions for BATDEBOUNCING */
1559 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1560 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1561 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1562 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1563 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1564 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1566 /* Bit definitions for SWOFF_HWRST */
1567 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1568 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1569 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1570 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1571 #define PALMAS_SWOFF_HWRST_WTD 0x20
1572 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1573 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1574 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1575 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1576 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1577 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1578 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1579 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1580 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1581 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1582 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1584 /* Bit definitions for SWOFF_COLDRST */
1585 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1586 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1587 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1588 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1589 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1590 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1591 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1592 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1593 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1594 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1595 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1596 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1597 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1598 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1599 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1600 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1602 /* Bit definitions for SWOFF_STATUS */
1603 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1604 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1605 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1606 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1607 #define PALMAS_SWOFF_STATUS_WTD 0x20
1608 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1609 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1610 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1611 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1612 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1613 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1614 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1615 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1616 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1617 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1618 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1620 /* Bit definitions for PMU_CONFIG */
1621 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1622 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1623 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1624 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1625 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1626 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1627 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1628 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1629 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1630 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1632 /* Bit definitions for SPARE */
1633 #define PALMAS_SPARE_SPARE_MASK 0xf8
1634 #define PALMAS_SPARE_SPARE_SHIFT 0x03
1635 #define PALMAS_SPARE_REGEN3_OD 0x04
1636 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1637 #define PALMAS_SPARE_REGEN2_OD 0x02
1638 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1639 #define PALMAS_SPARE_REGEN1_OD 0x01
1640 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1642 /* Bit definitions for PMU_SECONDARY_INT */
1643 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1644 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1645 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1646 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1647 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1648 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1649 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1650 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1651 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1652 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1653 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1654 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1655 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1656 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1657 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1658 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1660 /* Bit definitions for SW_REVISION */
1661 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1662 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1664 /* Bit definitions for EXT_CHRG_CTRL */
1665 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1666 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1667 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1668 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1669 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1670 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1671 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1672 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1673 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1674 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1675 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1676 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1678 /* Bit definitions for PMU_SECONDARY_INT2 */
1679 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1680 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1681 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1682 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1683 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1684 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1685 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1686 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1688 /* Registers for function RESOURCE */
1689 #define PALMAS_CLK32KG_CTRL 0x00
1690 #define PALMAS_CLK32KGAUDIO_CTRL 0x01
1691 #define PALMAS_REGEN1_CTRL 0x02
1692 #define PALMAS_REGEN2_CTRL 0x03
1693 #define PALMAS_SYSEN1_CTRL 0x04
1694 #define PALMAS_SYSEN2_CTRL 0x05
1695 #define PALMAS_NSLEEP_RES_ASSIGN 0x06
1696 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1697 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1698 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1699 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1700 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1701 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1702 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1703 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1704 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1705 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1706 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1707 #define PALMAS_REGEN3_CTRL 0x12
1709 /* Bit definitions for CLK32KG_CTRL */
1710 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1711 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1712 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1713 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1714 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1715 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1717 /* Bit definitions for CLK32KGAUDIO_CTRL */
1718 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1719 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1720 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1721 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1722 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1723 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1724 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1725 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1727 /* Bit definitions for REGEN1_CTRL */
1728 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1729 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1730 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1731 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1732 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1733 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1735 /* Bit definitions for REGEN2_CTRL */
1736 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1737 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1738 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1739 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1740 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1741 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1743 /* Bit definitions for SYSEN1_CTRL */
1744 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1745 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1746 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1747 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1748 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1749 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1751 /* Bit definitions for SYSEN2_CTRL */
1752 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1753 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1754 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1755 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1756 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1757 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1759 /* Bit definitions for NSLEEP_RES_ASSIGN */
1760 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1761 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1762 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1763 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1764 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1765 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1766 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1767 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1768 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1769 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1770 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1771 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1772 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1773 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1775 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1776 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1777 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1778 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1779 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1780 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1781 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1782 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1783 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1784 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1785 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1786 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1787 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1788 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1789 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1790 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1791 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1793 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1794 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1795 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1796 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1797 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1798 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1799 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1800 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1801 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1802 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1803 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1804 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1805 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1806 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1807 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1808 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1809 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1811 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1812 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1813 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1814 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1815 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1816 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1817 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1819 /* Bit definitions for ENABLE1_RES_ASSIGN */
1820 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1821 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1822 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1823 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1824 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1825 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1826 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1827 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1828 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1829 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1830 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1831 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1832 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1833 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1835 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1836 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1837 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1838 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1839 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1840 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1841 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1842 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1843 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1844 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1845 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1846 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1847 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1848 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1849 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1850 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1851 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1853 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1854 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1855 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1856 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1857 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1858 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1859 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1860 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1861 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1862 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1863 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1864 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1865 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1866 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1867 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1868 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1869 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1871 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1872 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1873 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1874 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1875 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1876 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1877 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1879 /* Bit definitions for ENABLE2_RES_ASSIGN */
1880 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1881 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1882 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1883 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1884 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1885 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1886 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1887 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1888 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1889 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1890 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1891 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1892 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1893 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1895 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1896 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1897 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1898 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1899 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1900 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1901 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1902 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1903 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1904 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1905 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1906 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1907 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1908 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1909 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1910 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1911 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1913 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1914 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1915 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1916 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1917 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1918 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1919 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1920 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1921 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1922 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1923 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1924 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1925 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1926 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1927 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1928 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1929 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1931 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1932 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1933 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1934 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1935 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1936 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1937 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1939 /* Bit definitions for REGEN3_CTRL */
1940 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1941 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1942 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1943 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1944 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1945 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1947 /* Registers for function PAD_CONTROL */
1948 #define PALMAS_OD_OUTPUT_CTRL2 0x02
1949 #define PALMAS_POLARITY_CTRL2 0x03
1950 #define PALMAS_PU_PD_INPUT_CTRL1 0x04
1951 #define PALMAS_PU_PD_INPUT_CTRL2 0x05
1952 #define PALMAS_PU_PD_INPUT_CTRL3 0x06
1953 #define PALMAS_PU_PD_INPUT_CTRL5 0x07
1954 #define PALMAS_OD_OUTPUT_CTRL 0x08
1955 #define PALMAS_POLARITY_CTRL 0x09
1956 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1957 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1958 #define PALMAS_I2C_SPI 0x0C
1959 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1960 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1961 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1963 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1964 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1965 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1966 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1967 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1968 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1969 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1970 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1971 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1972 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1973 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1975 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1976 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1977 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1978 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1979 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1980 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1981 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1982 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1983 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1984 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1985 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1986 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1987 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1989 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1990 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1991 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1992 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1993 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1994 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1995 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1996 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1997 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1999 /* Bit definitions for OD_OUTPUT_CTRL */
2000 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
2001 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
2002 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
2003 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
2004 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
2005 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
2006 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
2007 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
2009 /* Bit definitions for POLARITY_CTRL */
2010 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
2011 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
2012 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
2013 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
2014 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
2015 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
2016 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
2017 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
2018 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
2019 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
2020 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
2021 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
2022 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
2023 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
2024 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
2025 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
2027 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2028 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
2029 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
2030 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
2031 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2032 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
2033 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2034 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
2035 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2036 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
2037 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2038 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
2039 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2041 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2042 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
2043 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2044 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
2045 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2046 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
2047 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2048 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
2049 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2051 /* Bit definitions for I2C_SPI */
2052 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
2053 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2054 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
2055 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2056 #define PALMAS_I2C_SPI_ID_I2C2 0x20
2057 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2058 #define PALMAS_I2C_SPI_I2C_SPI 0x10
2059 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
2060 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
2061 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2063 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2064 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
2065 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2066 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
2067 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2068 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
2069 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2070 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
2071 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2073 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2074 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
2075 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2076 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
2077 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2079 /* Registers for function LED_PWM */
2080 #define PALMAS_LED_PERIOD_CTRL 0x00
2081 #define PALMAS_LED_CTRL 0x01
2082 #define PALMAS_PWM_CTRL1 0x02
2083 #define PALMAS_PWM_CTRL2 0x03
2085 /* Bit definitions for LED_PERIOD_CTRL */
2086 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
2087 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2088 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
2089 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2091 /* Bit definitions for LED_CTRL */
2092 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
2093 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2094 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
2095 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2096 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
2097 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2098 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
2099 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2101 /* Bit definitions for PWM_CTRL1 */
2102 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
2103 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2104 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
2105 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2107 /* Bit definitions for PWM_CTRL2 */
2108 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2109 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2111 /* Registers for function INTERRUPT */
2112 #define PALMAS_INT1_STATUS 0x00
2113 #define PALMAS_INT1_MASK 0x01
2114 #define PALMAS_INT1_LINE_STATE 0x02
2115 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2116 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2117 #define PALMAS_INT2_STATUS 0x05
2118 #define PALMAS_INT2_MASK 0x06
2119 #define PALMAS_INT2_LINE_STATE 0x07
2120 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2121 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2122 #define PALMAS_INT3_STATUS 0x0A
2123 #define PALMAS_INT3_MASK 0x0B
2124 #define PALMAS_INT3_LINE_STATE 0x0C
2125 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2126 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2127 #define PALMAS_INT4_STATUS 0x0F
2128 #define PALMAS_INT4_MASK 0x10
2129 #define PALMAS_INT4_LINE_STATE 0x11
2130 #define PALMAS_INT4_EDGE_DETECT1 0x12
2131 #define PALMAS_INT4_EDGE_DETECT2 0x13
2132 #define PALMAS_INT_CTRL 0x14
2134 /* Bit definitions for INT1_STATUS */
2135 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
2136 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2137 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
2138 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2139 #define PALMAS_INT1_STATUS_HOTDIE 0x20
2140 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2141 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
2142 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2143 #define PALMAS_INT1_STATUS_RPWRON 0x08
2144 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2145 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
2146 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2147 #define PALMAS_INT1_STATUS_PWRON 0x02
2148 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2149 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
2150 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2152 /* Bit definitions for INT1_MASK */
2153 #define PALMAS_INT1_MASK_VBAT_MON 0x80
2154 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2155 #define PALMAS_INT1_MASK_VSYS_MON 0x40
2156 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2157 #define PALMAS_INT1_MASK_HOTDIE 0x20
2158 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2159 #define PALMAS_INT1_MASK_PWRDOWN 0x10
2160 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2161 #define PALMAS_INT1_MASK_RPWRON 0x08
2162 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2163 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
2164 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2165 #define PALMAS_INT1_MASK_PWRON 0x02
2166 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2167 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2168 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2170 /* Bit definitions for INT1_LINE_STATE */
2171 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2172 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2173 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2174 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2175 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2176 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2177 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2178 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2179 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2180 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2181 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2182 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2183 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
2184 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2185 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2186 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2188 /* Bit definitions for INT2_STATUS */
2189 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2190 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2191 #define PALMAS_INT2_STATUS_SHORT 0x40
2192 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2193 #define PALMAS_INT2_STATUS_FBI_BB 0x20
2194 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2195 #define PALMAS_INT2_STATUS_RESET_IN 0x10
2196 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2197 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2198 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2199 #define PALMAS_INT2_STATUS_WDT 0x04
2200 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2201 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2202 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2203 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2204 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2206 /* Bit definitions for INT2_MASK */
2207 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
2208 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2209 #define PALMAS_INT2_MASK_SHORT 0x40
2210 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2211 #define PALMAS_INT2_MASK_FBI_BB 0x20
2212 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2213 #define PALMAS_INT2_MASK_RESET_IN 0x10
2214 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2215 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
2216 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2217 #define PALMAS_INT2_MASK_WDT 0x04
2218 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2219 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
2220 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2221 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
2222 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2224 /* Bit definitions for INT2_LINE_STATE */
2225 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2226 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2227 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
2228 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2229 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2230 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2231 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2232 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2233 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2234 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2235 #define PALMAS_INT2_LINE_STATE_WDT 0x04
2236 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2237 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2238 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2239 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2240 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2242 /* Bit definitions for INT3_STATUS */
2243 #define PALMAS_INT3_STATUS_VBUS 0x80
2244 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2245 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2246 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2247 #define PALMAS_INT3_STATUS_ID 0x20
2248 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2249 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2250 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2251 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2252 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2253 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2254 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2255 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2256 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2257 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2258 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2260 /* Bit definitions for INT3_MASK */
2261 #define PALMAS_INT3_MASK_VBUS 0x80
2262 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2263 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2264 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2265 #define PALMAS_INT3_MASK_ID 0x20
2266 #define PALMAS_INT3_MASK_ID_SHIFT 0x05
2267 #define PALMAS_INT3_MASK_ID_OTG 0x10
2268 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2269 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2270 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2271 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2272 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2273 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2274 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2275 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2276 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2278 /* Bit definitions for INT3_LINE_STATE */
2279 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2280 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2281 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2282 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2283 #define PALMAS_INT3_LINE_STATE_ID 0x20
2284 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2285 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2286 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2287 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2288 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2289 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2290 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2291 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2292 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2293 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2294 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2296 /* Bit definitions for INT4_STATUS */
2297 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2298 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2299 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2300 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2301 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2302 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2303 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2304 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2305 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2306 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2307 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2308 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2309 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2310 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2311 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2312 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2314 /* Bit definitions for INT4_MASK */
2315 #define PALMAS_INT4_MASK_GPIO_7 0x80
2316 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2317 #define PALMAS_INT4_MASK_GPIO_6 0x40
2318 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2319 #define PALMAS_INT4_MASK_GPIO_5 0x20
2320 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2321 #define PALMAS_INT4_MASK_GPIO_4 0x10
2322 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2323 #define PALMAS_INT4_MASK_GPIO_3 0x08
2324 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2325 #define PALMAS_INT4_MASK_GPIO_2 0x04
2326 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2327 #define PALMAS_INT4_MASK_GPIO_1 0x02
2328 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2329 #define PALMAS_INT4_MASK_GPIO_0 0x01
2330 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2332 /* Bit definitions for INT4_LINE_STATE */
2333 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2334 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2335 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2336 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2337 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2338 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2339 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2340 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2341 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2342 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2343 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2344 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2345 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2346 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2347 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2348 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2350 /* Bit definitions for INT4_EDGE_DETECT1 */
2351 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2352 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2353 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2354 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2355 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2356 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2357 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2358 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2359 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2360 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2361 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2362 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2363 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2364 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2365 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2366 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2368 /* Bit definitions for INT4_EDGE_DETECT2 */
2369 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2370 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2371 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2372 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2373 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2374 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2375 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2376 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2377 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2378 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2379 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2380 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2381 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2382 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2383 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2384 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2386 /* Bit definitions for INT_CTRL */
2387 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2388 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2389 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2390 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2392 /* Registers for function USB_OTG */
2393 #define PALMAS_USB_WAKEUP 0x03
2394 #define PALMAS_USB_VBUS_CTRL_SET 0x04
2395 #define PALMAS_USB_VBUS_CTRL_CLR 0x05
2396 #define PALMAS_USB_ID_CTRL_SET 0x06
2397 #define PALMAS_USB_ID_CTRL_CLEAR 0x07
2398 #define PALMAS_USB_VBUS_INT_SRC 0x08
2399 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2400 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2401 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2402 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2403 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2404 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2405 #define PALMAS_USB_ID_INT_SRC 0x0F
2406 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2407 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2408 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2409 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2410 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2411 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2412 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2413 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2414 #define PALMAS_USB_OTG_ADP_LOW 0x18
2415 #define PALMAS_USB_OTG_ADP_RISE 0x19
2416 #define PALMAS_USB_OTG_REVISION 0x1A
2418 /* Bit definitions for USB_WAKEUP */
2419 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2420 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2422 /* Bit definitions for USB_VBUS_CTRL_SET */
2423 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2424 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2425 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2426 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2427 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2428 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2429 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2430 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2431 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2432 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2434 /* Bit definitions for USB_VBUS_CTRL_CLR */
2435 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2436 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2437 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2438 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2439 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2440 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2441 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2442 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2443 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2444 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2446 /* Bit definitions for USB_ID_CTRL_SET */
2447 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2448 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2449 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2450 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2451 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2452 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2453 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2454 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2455 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2456 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2457 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2458 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2460 /* Bit definitions for USB_ID_CTRL_CLEAR */
2461 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2462 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2463 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2464 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2465 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2466 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2467 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2468 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2469 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2470 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2471 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2472 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2474 /* Bit definitions for USB_VBUS_INT_SRC */
2475 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2476 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2477 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2478 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2479 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2480 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2481 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2482 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2483 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2484 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2485 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2486 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2487 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2488 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2490 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2491 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2492 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2493 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2494 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2495 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2496 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2497 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2498 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2499 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2500 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2501 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2502 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2503 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2504 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2505 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2506 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2508 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2509 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2510 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2511 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2512 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2513 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2514 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2515 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2516 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2517 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2518 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2519 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2520 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2521 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2522 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2523 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2524 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2526 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2527 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2528 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2529 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2530 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2531 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2532 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2533 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2534 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2535 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2536 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2537 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2538 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2539 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2540 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2542 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2543 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2544 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2545 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2546 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2547 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2548 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2549 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2550 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2551 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2552 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2553 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2554 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2555 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2556 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2558 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2559 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2560 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2561 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2562 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2563 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2564 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2565 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2566 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2567 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2568 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2569 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2570 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2571 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2572 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2573 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2574 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2576 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2577 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2578 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2579 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2580 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2581 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2582 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2583 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2584 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2585 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2586 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2587 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2588 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2589 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2590 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2591 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2592 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2594 /* Bit definitions for USB_ID_INT_SRC */
2595 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2596 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2597 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2598 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2599 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2600 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2601 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2602 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2603 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2604 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2606 /* Bit definitions for USB_ID_INT_LATCH_SET */
2607 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2608 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2609 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2610 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2611 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2612 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2613 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2614 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2615 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2616 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2618 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2619 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2620 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2621 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2622 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2623 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2624 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2625 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2626 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2627 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2628 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2630 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2631 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2632 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2633 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2634 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2635 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2636 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2637 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2638 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2639 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2640 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2642 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2643 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2644 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2645 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2646 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2647 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2648 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2649 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2650 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2651 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2652 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2654 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2655 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2656 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2657 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2658 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2659 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2660 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2661 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2662 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2663 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2664 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2666 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2667 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2668 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2669 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2670 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2671 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2672 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2673 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2674 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2675 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2676 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2678 /* Bit definitions for USB_OTG_ADP_CTRL */
2679 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2680 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2681 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2682 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2684 /* Bit definitions for USB_OTG_ADP_HIGH */
2685 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2686 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2688 /* Bit definitions for USB_OTG_ADP_LOW */
2689 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2690 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2692 /* Bit definitions for USB_OTG_ADP_RISE */
2693 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2694 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2696 /* Bit definitions for USB_OTG_REVISION */
2697 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2698 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2700 /* Registers for function VIBRATOR */
2701 #define PALMAS_VIBRA_CTRL 0x00
2703 /* Bit definitions for VIBRA_CTRL */
2704 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2705 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2706 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2707 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2709 /* Registers for function GPIO */
2710 #define PALMAS_GPIO_DATA_IN 0x00
2711 #define PALMAS_GPIO_DATA_DIR 0x01
2712 #define PALMAS_GPIO_DATA_OUT 0x02
2713 #define PALMAS_GPIO_DEBOUNCE_EN 0x03
2714 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2715 #define PALMAS_GPIO_SET_DATA_OUT 0x05
2716 #define PALMAS_PU_PD_GPIO_CTRL1 0x06
2717 #define PALMAS_PU_PD_GPIO_CTRL2 0x07
2718 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2719 #define PALMAS_GPIO_DATA_IN2 0x09
2720 #define PALMAS_GPIO_DATA_DIR2 0x0A
2721 #define PALMAS_GPIO_DATA_OUT2 0x0B
2722 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2723 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2724 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2725 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2726 #define PALMAS_PU_PD_GPIO_CTRL4 0x10
2727 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2729 /* Bit definitions for GPIO_DATA_IN */
2730 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2731 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2732 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2733 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2734 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2735 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2736 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2737 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2738 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2739 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2740 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2741 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2742 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2743 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2744 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2745 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2747 /* Bit definitions for GPIO_DATA_DIR */
2748 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2749 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2750 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2751 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2752 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2753 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2754 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2755 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2756 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2757 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2758 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2759 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2760 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2761 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2762 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2763 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2765 /* Bit definitions for GPIO_DATA_OUT */
2766 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2767 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2768 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2769 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2770 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2771 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2772 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2773 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2774 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2775 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2776 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2777 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2778 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2779 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2780 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2781 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2783 /* Bit definitions for GPIO_DEBOUNCE_EN */
2784 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2785 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2786 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2787 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2788 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2789 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2790 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2791 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2792 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2793 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2794 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2795 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2796 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2797 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2798 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2799 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2801 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2802 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2803 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2804 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2805 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2806 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2807 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2808 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2809 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2810 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2811 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2812 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2813 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2814 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2815 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2816 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2817 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2819 /* Bit definitions for GPIO_SET_DATA_OUT */
2820 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2821 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2822 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2823 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2824 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2825 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2826 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2827 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2828 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2829 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2830 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2831 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2832 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2833 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2834 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2835 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2837 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2838 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2839 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2840 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2841 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2842 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2843 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2844 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2845 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2846 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2847 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2848 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2849 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2851 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2852 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2853 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2854 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2855 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2856 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2857 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2858 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2859 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2860 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2861 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2862 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2863 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2864 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2865 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2867 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2868 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2869 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2870 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2871 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2872 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2873 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2875 /* Registers for function GPADC */
2876 #define PALMAS_GPADC_CTRL1 0x00
2877 #define PALMAS_GPADC_CTRL2 0x01
2878 #define PALMAS_GPADC_RT_CTRL 0x02
2879 #define PALMAS_GPADC_AUTO_CTRL 0x03
2880 #define PALMAS_GPADC_STATUS 0x04
2881 #define PALMAS_GPADC_RT_SELECT 0x05
2882 #define PALMAS_GPADC_RT_CONV0_LSB 0x06
2883 #define PALMAS_GPADC_RT_CONV0_MSB 0x07
2884 #define PALMAS_GPADC_AUTO_SELECT 0x08
2885 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2886 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2887 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2888 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2889 #define PALMAS_GPADC_SW_SELECT 0x0D
2890 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2891 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2892 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2893 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2894 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2895 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2896 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2897 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2899 /* Bit definitions for GPADC_CTRL1 */
2900 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2901 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2902 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2903 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2904 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2905 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2906 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2907 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2908 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2909 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2911 /* Bit definitions for GPADC_CTRL2 */
2912 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2913 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2915 /* Bit definitions for GPADC_RT_CTRL */
2916 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2917 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2918 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2919 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2921 /* Bit definitions for GPADC_AUTO_CTRL */
2922 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2923 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2924 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2925 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2926 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2927 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2928 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2929 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2930 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2931 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2933 /* Bit definitions for GPADC_STATUS */
2934 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2935 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2937 /* Bit definitions for GPADC_RT_SELECT */
2938 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2939 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2940 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2941 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2943 /* Bit definitions for GPADC_RT_CONV0_LSB */
2944 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2945 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2947 /* Bit definitions for GPADC_RT_CONV0_MSB */
2948 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2949 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2951 /* Bit definitions for GPADC_AUTO_SELECT */
2952 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2953 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2954 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2955 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2957 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2958 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2959 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2961 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2962 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2963 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2965 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2966 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2967 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2969 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2970 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2971 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2973 /* Bit definitions for GPADC_SW_SELECT */
2974 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2975 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2976 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2977 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2978 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2979 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2981 /* Bit definitions for GPADC_SW_CONV0_LSB */
2982 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2983 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2985 /* Bit definitions for GPADC_SW_CONV0_MSB */
2986 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2987 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2989 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2990 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2991 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2993 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2994 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2995 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2996 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2997 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2999 /* Bit definitions for GPADC_THRES_CONV1_LSB */
3000 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
3001 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
3003 /* Bit definitions for GPADC_THRES_CONV1_MSB */
3004 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
3005 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
3006 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
3007 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
3009 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
3010 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
3011 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
3012 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
3013 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
3014 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
3015 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
3017 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3018 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
3019 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
3020 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
3021 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
3023 /* Registers for function GPADC */
3024 #define PALMAS_GPADC_TRIM1 0x00
3025 #define PALMAS_GPADC_TRIM2 0x01
3026 #define PALMAS_GPADC_TRIM3 0x02
3027 #define PALMAS_GPADC_TRIM4 0x03
3028 #define PALMAS_GPADC_TRIM5 0x04
3029 #define PALMAS_GPADC_TRIM6 0x05
3030 #define PALMAS_GPADC_TRIM7 0x06
3031 #define PALMAS_GPADC_TRIM8 0x07
3032 #define PALMAS_GPADC_TRIM9 0x08
3033 #define PALMAS_GPADC_TRIM10 0x09
3034 #define PALMAS_GPADC_TRIM11 0x0A
3035 #define PALMAS_GPADC_TRIM12 0x0B
3036 #define PALMAS_GPADC_TRIM13 0x0C
3037 #define PALMAS_GPADC_TRIM14 0x0D
3038 #define PALMAS_GPADC_TRIM15 0x0E
3039 #define PALMAS_GPADC_TRIM16 0x0F
3041 /* TPS659038 regen2_ctrl offset iss different from palmas */
3042 #define TPS659038_REGEN2_CTRL 0x12
3044 /* TPS65917 Interrupt registers */
3046 /* Registers for function INTERRUPT */
3047 #define TPS65917_INT1_STATUS 0x00
3048 #define TPS65917_INT1_MASK 0x01
3049 #define TPS65917_INT1_LINE_STATE 0x02
3050 #define TPS65917_INT2_STATUS 0x05
3051 #define TPS65917_INT2_MASK 0x06
3052 #define TPS65917_INT2_LINE_STATE 0x07
3053 #define TPS65917_INT3_STATUS 0x0A
3054 #define TPS65917_INT3_MASK 0x0B
3055 #define TPS65917_INT3_LINE_STATE 0x0C
3056 #define TPS65917_INT4_STATUS 0x0F
3057 #define TPS65917_INT4_MASK 0x10
3058 #define TPS65917_INT4_LINE_STATE 0x11
3059 #define TPS65917_INT4_EDGE_DETECT1 0x12
3060 #define TPS65917_INT4_EDGE_DETECT2 0x13
3061 #define TPS65917_INT_CTRL 0x14
3063 /* Bit definitions for INT1_STATUS */
3064 #define TPS65917_INT1_STATUS_VSYS_MON 0x40
3065 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3066 #define TPS65917_INT1_STATUS_HOTDIE 0x20
3067 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3068 #define TPS65917_INT1_STATUS_PWRDOWN 0x10
3069 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3070 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3071 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3072 #define TPS65917_INT1_STATUS_PWRON 0x02
3073 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3075 /* Bit definitions for INT1_MASK */
3076 #define TPS65917_INT1_MASK_VSYS_MON 0x40
3077 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3078 #define TPS65917_INT1_MASK_HOTDIE 0x20
3079 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3080 #define TPS65917_INT1_MASK_PWRDOWN 0x10
3081 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3082 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3083 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3084 #define TPS65917_INT1_MASK_PWRON 0x02
3085 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3087 /* Bit definitions for INT1_LINE_STATE */
3088 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3089 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3090 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3091 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3092 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3093 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3094 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3095 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3096 #define TPS65917_INT1_LINE_STATE_PWRON 0x02
3097 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3099 /* Bit definitions for INT2_STATUS */
3100 #define TPS65917_INT2_STATUS_SHORT 0x40
3101 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3102 #define TPS65917_INT2_STATUS_FSD 0x20
3103 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3104 #define TPS65917_INT2_STATUS_RESET_IN 0x10
3105 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3106 #define TPS65917_INT2_STATUS_WDT 0x04
3107 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3108 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3109 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3111 /* Bit definitions for INT2_MASK */
3112 #define TPS65917_INT2_MASK_SHORT 0x40
3113 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3114 #define TPS65917_INT2_MASK_FSD 0x20
3115 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3116 #define TPS65917_INT2_MASK_RESET_IN 0x10
3117 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3118 #define TPS65917_INT2_MASK_WDT 0x04
3119 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3120 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3121 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3123 /* Bit definitions for INT2_LINE_STATE */
3124 #define TPS65917_INT2_LINE_STATE_SHORT 0x40
3125 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3126 #define TPS65917_INT2_LINE_STATE_FSD 0x20
3127 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3128 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3129 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3130 #define TPS65917_INT2_LINE_STATE_WDT 0x04
3131 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3132 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3133 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3135 /* Bit definitions for INT3_STATUS */
3136 #define TPS65917_INT3_STATUS_VBUS 0x80
3137 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3138 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3139 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3140 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3141 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3142 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3143 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3145 /* Bit definitions for INT3_MASK */
3146 #define TPS65917_INT3_MASK_VBUS 0x80
3147 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3148 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3149 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3150 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3151 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3152 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3153 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3155 /* Bit definitions for INT3_LINE_STATE */
3156 #define TPS65917_INT3_LINE_STATE_VBUS 0x80
3157 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3158 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3159 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3160 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3161 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3162 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3163 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3165 /* Bit definitions for INT4_STATUS */
3166 #define TPS65917_INT4_STATUS_GPIO_6 0x40
3167 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3168 #define TPS65917_INT4_STATUS_GPIO_5 0x20
3169 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3170 #define TPS65917_INT4_STATUS_GPIO_4 0x10
3171 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3172 #define TPS65917_INT4_STATUS_GPIO_3 0x08
3173 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3174 #define TPS65917_INT4_STATUS_GPIO_2 0x04
3175 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3176 #define TPS65917_INT4_STATUS_GPIO_1 0x02
3177 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3178 #define TPS65917_INT4_STATUS_GPIO_0 0x01
3179 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3181 /* Bit definitions for INT4_MASK */
3182 #define TPS65917_INT4_MASK_GPIO_6 0x40
3183 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3184 #define TPS65917_INT4_MASK_GPIO_5 0x20
3185 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3186 #define TPS65917_INT4_MASK_GPIO_4 0x10
3187 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3188 #define TPS65917_INT4_MASK_GPIO_3 0x08
3189 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3190 #define TPS65917_INT4_MASK_GPIO_2 0x04
3191 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3192 #define TPS65917_INT4_MASK_GPIO_1 0x02
3193 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3194 #define TPS65917_INT4_MASK_GPIO_0 0x01
3195 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3197 /* Bit definitions for INT4_LINE_STATE */
3198 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3199 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3200 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3201 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3202 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3203 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3204 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3205 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3206 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3207 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3208 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3209 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3210 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3211 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3213 /* Bit definitions for INT4_EDGE_DETECT1 */
3214 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3215 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3216 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3217 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3218 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3219 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3220 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3221 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3222 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3223 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3224 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3225 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3226 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3227 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3228 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3229 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3231 /* Bit definitions for INT4_EDGE_DETECT2 */
3232 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3233 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3234 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3235 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3236 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3237 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3238 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3239 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3240 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3241 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3242 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3243 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3245 /* Bit definitions for INT_CTRL */
3246 #define TPS65917_INT_CTRL_INT_PENDING 0x04
3247 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3248 #define TPS65917_INT_CTRL_INT_CLEAR 0x01
3249 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3251 /* TPS65917 SMPS Registers */
3253 /* Registers for function SMPS */
3254 #define TPS65917_SMPS1_CTRL 0x00
3255 #define TPS65917_SMPS1_FORCE 0x02
3256 #define TPS65917_SMPS1_VOLTAGE 0x03
3257 #define TPS65917_SMPS2_CTRL 0x04
3258 #define TPS65917_SMPS2_FORCE 0x06
3259 #define TPS65917_SMPS2_VOLTAGE 0x07
3260 #define TPS65917_SMPS3_CTRL 0x0C
3261 #define TPS65917_SMPS3_FORCE 0x0E
3262 #define TPS65917_SMPS3_VOLTAGE 0x0F
3263 #define TPS65917_SMPS4_CTRL 0x10
3264 #define TPS65917_SMPS4_VOLTAGE 0x13
3265 #define TPS65917_SMPS5_CTRL 0x18
3266 #define TPS65917_SMPS5_VOLTAGE 0x1B
3267 #define TPS65917_SMPS_CTRL 0x24
3268 #define TPS65917_SMPS_PD_CTRL 0x25
3269 #define TPS65917_SMPS_THERMAL_EN 0x27
3270 #define TPS65917_SMPS_THERMAL_STATUS 0x28
3271 #define TPS65917_SMPS_SHORT_STATUS 0x29
3272 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3273 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3274 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3276 /* Bit definitions for SMPS1_CTRL */
3277 #define TPS65917_SMPS1_CTRL_WR_S 0x80
3278 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3279 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3280 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3281 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3282 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3283 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3284 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3285 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3286 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3288 /* Bit definitions for SMPS1_FORCE */
3289 #define TPS65917_SMPS1_FORCE_CMD 0x80
3290 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3291 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3292 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3294 /* Bit definitions for SMPS1_VOLTAGE */
3295 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3296 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3297 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3298 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3300 /* Bit definitions for SMPS2_CTRL */
3301 #define TPS65917_SMPS2_CTRL_WR_S 0x80
3302 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3303 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3304 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3305 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3306 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3307 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3308 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3309 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3310 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3312 /* Bit definitions for SMPS2_FORCE */
3313 #define TPS65917_SMPS2_FORCE_CMD 0x80
3314 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3315 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3316 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3318 /* Bit definitions for SMPS2_VOLTAGE */
3319 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3320 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3321 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3322 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3324 /* Bit definitions for SMPS3_CTRL */
3325 #define TPS65917_SMPS3_CTRL_WR_S 0x80
3326 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3327 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3328 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3329 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3330 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3331 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3332 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3333 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3334 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3336 /* Bit definitions for SMPS3_FORCE */
3337 #define TPS65917_SMPS3_FORCE_CMD 0x80
3338 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3339 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3340 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3342 /* Bit definitions for SMPS3_VOLTAGE */
3343 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3344 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3345 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3346 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3348 /* Bit definitions for SMPS4_CTRL */
3349 #define TPS65917_SMPS4_CTRL_WR_S 0x80
3350 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3351 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3352 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3353 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3354 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3355 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3356 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3357 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3358 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3360 /* Bit definitions for SMPS4_VOLTAGE */
3361 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3362 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3363 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3364 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3366 /* Bit definitions for SMPS5_CTRL */
3367 #define TPS65917_SMPS5_CTRL_WR_S 0x80
3368 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3369 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3370 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3371 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3372 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3373 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3374 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3375 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3376 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3378 /* Bit definitions for SMPS5_VOLTAGE */
3379 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3380 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3381 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3382 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3384 /* Bit definitions for SMPS_CTRL */
3385 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3386 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3387 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3388 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3390 /* Bit definitions for SMPS_PD_CTRL */
3391 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3392 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3393 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3394 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3395 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3396 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3397 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3398 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3399 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3400 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3402 /* Bit definitions for SMPS_THERMAL_EN */
3403 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3404 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3405 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3406 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3407 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3408 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3410 /* Bit definitions for SMPS_THERMAL_STATUS */
3411 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3412 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3413 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3414 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3415 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3416 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3418 /* Bit definitions for SMPS_SHORT_STATUS */
3419 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3420 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3421 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3422 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3423 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3424 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3425 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3426 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3427 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3428 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3430 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3431 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3432 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3433 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3434 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3435 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3436 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3437 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3438 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3439 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3440 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3442 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
3443 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3444 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3445 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3446 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3447 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3448 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3449 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3450 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3451 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3452 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3454 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
3455 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3456 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3457 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3458 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3460 /* Bit definitions for SMPS_PLL_CTRL */
3462 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3463 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3464 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3465 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3467 /* Registers for function LDO */
3468 #define TPS65917_LDO1_CTRL 0x00
3469 #define TPS65917_LDO1_VOLTAGE 0x01
3470 #define TPS65917_LDO2_CTRL 0x02
3471 #define TPS65917_LDO2_VOLTAGE 0x03
3472 #define TPS65917_LDO3_CTRL 0x04
3473 #define TPS65917_LDO3_VOLTAGE 0x05
3474 #define TPS65917_LDO4_CTRL 0x0E
3475 #define TPS65917_LDO4_VOLTAGE 0x0F
3476 #define TPS65917_LDO5_CTRL 0x12
3477 #define TPS65917_LDO5_VOLTAGE 0x13
3478 #define TPS65917_LDO_PD_CTRL1 0x1B
3479 #define TPS65917_LDO_PD_CTRL2 0x1C
3480 #define TPS65917_LDO_SHORT_STATUS1 0x1D
3481 #define TPS65917_LDO_SHORT_STATUS2 0x1E
3482 #define TPS65917_LDO_PD_CTRL3 0x2D
3483 #define TPS65917_LDO_SHORT_STATUS3 0x2E
3485 /* Bit definitions for LDO1_CTRL */
3486 #define TPS65917_LDO1_CTRL_WR_S 0x80
3487 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3488 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3489 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3490 #define TPS65917_LDO1_CTRL_STATUS 0x10
3491 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3492 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3493 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3494 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3495 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3497 /* Bit definitions for LDO1_VOLTAGE */
3498 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3499 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3501 /* Bit definitions for LDO2_CTRL */
3502 #define TPS65917_LDO2_CTRL_WR_S 0x80
3503 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3504 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3505 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3506 #define TPS65917_LDO2_CTRL_STATUS 0x10
3507 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3508 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3509 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3510 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3511 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3513 /* Bit definitions for LDO2_VOLTAGE */
3514 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3515 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3517 /* Bit definitions for LDO3_CTRL */
3518 #define TPS65917_LDO3_CTRL_WR_S 0x80
3519 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3520 #define TPS65917_LDO3_CTRL_STATUS 0x10
3521 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3522 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3523 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3524 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3525 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3527 /* Bit definitions for LDO3_VOLTAGE */
3528 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3529 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3531 /* Bit definitions for LDO4_CTRL */
3532 #define TPS65917_LDO4_CTRL_WR_S 0x80
3533 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3534 #define TPS65917_LDO4_CTRL_STATUS 0x10
3535 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3536 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3537 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3538 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3539 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3541 /* Bit definitions for LDO4_VOLTAGE */
3542 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3543 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3545 /* Bit definitions for LDO5_CTRL */
3546 #define TPS65917_LDO5_CTRL_WR_S 0x80
3547 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3548 #define TPS65917_LDO5_CTRL_STATUS 0x10
3549 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3550 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3551 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3552 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3553 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3555 /* Bit definitions for LDO5_VOLTAGE */
3556 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3557 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3559 /* Bit definitions for LDO_PD_CTRL1 */
3560 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3561 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3562 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3563 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3564 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3565 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3567 /* Bit definitions for LDO_PD_CTRL2 */
3568 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3569 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3570 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3571 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3573 /* Bit definitions for LDO_PD_CTRL3 */
3574 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3575 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3577 /* Bit definitions for LDO_SHORT_STATUS1 */
3578 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3579 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3580 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3581 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3582 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3583 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3585 /* Bit definitions for LDO_SHORT_STATUS2 */
3586 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3587 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3588 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3589 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3591 /* Bit definitions for LDO_SHORT_STATUS2 */
3592 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3593 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3595 /* Bit definitions for REGEN1_CTRL */
3596 #define TPS65917_REGEN1_CTRL_STATUS 0x10
3597 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3598 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3599 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3600 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3601 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3603 /* Bit definitions for PLLEN_CTRL */
3604 #define TPS65917_PLLEN_CTRL_STATUS 0x10
3605 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3606 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3607 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3608 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3609 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3611 /* Bit definitions for REGEN2_CTRL */
3612 #define TPS65917_REGEN2_CTRL_STATUS 0x10
3613 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3614 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3615 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3616 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3617 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3619 /* Bit definitions for NSLEEP_RES_ASSIGN */
3620 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3621 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3622 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3623 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3624 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3625 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3626 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3627 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3629 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
3630 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3631 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3632 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3633 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3634 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3635 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3636 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3637 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3638 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3639 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3641 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3642 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3643 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3644 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3645 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3646 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3647 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3649 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3650 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3651 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3652 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3653 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3655 /* Bit definitions for ENABLE1_RES_ASSIGN */
3656 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3657 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3658 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3659 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3660 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3661 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3662 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3663 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3665 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
3666 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3667 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3668 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3669 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3670 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3671 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3672 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3673 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3674 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3675 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3677 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3678 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3679 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3680 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3681 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3682 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3683 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3685 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3686 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3687 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3688 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3689 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3691 /* Bit definitions for ENABLE2_RES_ASSIGN */
3692 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3693 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3694 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3695 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3696 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3697 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3698 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3699 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3701 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
3702 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3703 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3704 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3705 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3706 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3707 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3708 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3709 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3710 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3711 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3713 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3714 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3715 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3716 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3717 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3718 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3719 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3721 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3722 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3723 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3724 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3725 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3727 /* Bit definitions for REGEN3_CTRL */
3728 #define TPS65917_REGEN3_CTRL_STATUS 0x10
3729 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3730 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3731 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3732 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3733 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3735 /* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */
3736 #define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0xC
3738 /* Registers for function RESOURCE */
3739 #define TPS65917_REGEN1_CTRL 0x2
3740 #define TPS65917_PLLEN_CTRL 0x3
3741 #define TPS65917_NSLEEP_RES_ASSIGN 0x6
3742 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3743 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3744 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3745 #define TPS65917_ENABLE1_RES_ASSIGN 0xA
3746 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3747 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3748 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3749 #define TPS65917_ENABLE2_RES_ASSIGN 0xE
3750 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3751 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3752 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3753 #define TPS65917_REGEN2_CTRL 0x12
3754 #define TPS65917_REGEN3_CTRL 0x13
3756 static inline int palmas_read(struct palmas
*palmas
, unsigned int base
,
3757 unsigned int reg
, unsigned int *val
)
3759 unsigned int addr
= PALMAS_BASE_TO_REG(base
, reg
);
3760 int slave_id
= PALMAS_BASE_TO_SLAVE(base
);
3762 return regmap_read(palmas
->regmap
[slave_id
], addr
, val
);
3765 static inline int palmas_write(struct palmas
*palmas
, unsigned int base
,
3766 unsigned int reg
, unsigned int value
)
3768 unsigned int addr
= PALMAS_BASE_TO_REG(base
, reg
);
3769 int slave_id
= PALMAS_BASE_TO_SLAVE(base
);
3771 return regmap_write(palmas
->regmap
[slave_id
], addr
, value
);
3774 static inline int palmas_bulk_write(struct palmas
*palmas
, unsigned int base
,
3775 unsigned int reg
, const void *val
, size_t val_count
)
3777 unsigned int addr
= PALMAS_BASE_TO_REG(base
, reg
);
3778 int slave_id
= PALMAS_BASE_TO_SLAVE(base
);
3780 return regmap_bulk_write(palmas
->regmap
[slave_id
], addr
,
3784 static inline int palmas_bulk_read(struct palmas
*palmas
, unsigned int base
,
3785 unsigned int reg
, void *val
, size_t val_count
)
3787 unsigned int addr
= PALMAS_BASE_TO_REG(base
, reg
);
3788 int slave_id
= PALMAS_BASE_TO_SLAVE(base
);
3790 return regmap_bulk_read(palmas
->regmap
[slave_id
], addr
,
3794 static inline int palmas_update_bits(struct palmas
*palmas
, unsigned int base
,
3795 unsigned int reg
, unsigned int mask
, unsigned int val
)
3797 unsigned int addr
= PALMAS_BASE_TO_REG(base
, reg
);
3798 int slave_id
= PALMAS_BASE_TO_SLAVE(base
);
3800 return regmap_update_bits(palmas
->regmap
[slave_id
], addr
, mask
, val
);
3803 static inline int palmas_irq_get_virq(struct palmas
*palmas
, int irq
)
3805 return regmap_irq_get_virq(palmas
->irq_data
, irq
);
3809 int palmas_ext_control_req_config(struct palmas
*palmas
,
3810 enum palmas_external_requestor_id ext_control_req_id
,
3811 int ext_ctrl
, bool enable
);
3813 #endif /* __LINUX_MFD_PALMAS_H */