1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core driver interface to access RICOH_RC5T583 power management chip.
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
6 * Author: Laxman dewangan <ldewangan@nvidia.com>
9 * Copyright (C) 2011 RICOH COMPANY,LTD
12 #ifndef __LINUX_MFD_RC5T583_H
13 #define __LINUX_MFD_RC5T583_H
15 #include <linux/mutex.h>
16 #include <linux/types.h>
17 #include <linux/regmap.h>
19 /* Maximum number of main interrupts */
20 #define MAX_MAIN_INTERRUPT 5
21 #define RC5T583_MAX_GPEDGE_REG 2
22 #define RC5T583_MAX_INTERRUPT_EN_REGS 8
23 #define RC5T583_MAX_INTERRUPT_MASK_REGS 9
25 /* Interrupt enable register */
26 #define RC5T583_INT_EN_SYS1 0x19
27 #define RC5T583_INT_EN_SYS2 0x1D
28 #define RC5T583_INT_EN_DCDC 0x41
29 #define RC5T583_INT_EN_RTC 0xED
30 #define RC5T583_INT_EN_ADC1 0x90
31 #define RC5T583_INT_EN_ADC2 0x91
32 #define RC5T583_INT_EN_ADC3 0x92
34 /* Interrupt status registers (monitor regs in Ricoh)*/
35 #define RC5T583_INTC_INTPOL 0xAD
36 #define RC5T583_INTC_INTEN 0xAE
37 #define RC5T583_INTC_INTMON 0xAF
39 #define RC5T583_INT_MON_GRP 0xAF
40 #define RC5T583_INT_MON_SYS1 0x1B
41 #define RC5T583_INT_MON_SYS2 0x1F
42 #define RC5T583_INT_MON_DCDC 0x43
43 #define RC5T583_INT_MON_RTC 0xEE
45 /* Interrupt clearing registers */
46 #define RC5T583_INT_IR_SYS1 0x1A
47 #define RC5T583_INT_IR_SYS2 0x1E
48 #define RC5T583_INT_IR_DCDC 0x42
49 #define RC5T583_INT_IR_RTC 0xEE
50 #define RC5T583_INT_IR_ADCL 0x94
51 #define RC5T583_INT_IR_ADCH 0x95
52 #define RC5T583_INT_IR_ADCEND 0x96
53 #define RC5T583_INT_IR_GPIOR 0xA9
54 #define RC5T583_INT_IR_GPIOF 0xAA
56 /* Sleep sequence registers */
57 #define RC5T583_SLPSEQ1 0x21
58 #define RC5T583_SLPSEQ2 0x22
59 #define RC5T583_SLPSEQ3 0x23
60 #define RC5T583_SLPSEQ4 0x24
61 #define RC5T583_SLPSEQ5 0x25
62 #define RC5T583_SLPSEQ6 0x26
63 #define RC5T583_SLPSEQ7 0x27
64 #define RC5T583_SLPSEQ8 0x28
65 #define RC5T583_SLPSEQ9 0x29
66 #define RC5T583_SLPSEQ10 0x2A
67 #define RC5T583_SLPSEQ11 0x2B
69 /* Regulator registers */
70 #define RC5T583_REG_DC0CTL 0x30
71 #define RC5T583_REG_DC0DAC 0x31
72 #define RC5T583_REG_DC0LATCTL 0x32
73 #define RC5T583_REG_SR0CTL 0x33
75 #define RC5T583_REG_DC1CTL 0x34
76 #define RC5T583_REG_DC1DAC 0x35
77 #define RC5T583_REG_DC1LATCTL 0x36
78 #define RC5T583_REG_SR1CTL 0x37
80 #define RC5T583_REG_DC2CTL 0x38
81 #define RC5T583_REG_DC2DAC 0x39
82 #define RC5T583_REG_DC2LATCTL 0x3A
83 #define RC5T583_REG_SR2CTL 0x3B
85 #define RC5T583_REG_DC3CTL 0x3C
86 #define RC5T583_REG_DC3DAC 0x3D
87 #define RC5T583_REG_DC3LATCTL 0x3E
88 #define RC5T583_REG_SR3CTL 0x3F
91 #define RC5T583_REG_LDOEN1 0x50
92 #define RC5T583_REG_LDOEN2 0x51
93 #define RC5T583_REG_LDODIS1 0x52
94 #define RC5T583_REG_LDODIS2 0x53
96 #define RC5T583_REG_LDO0DAC 0x54
97 #define RC5T583_REG_LDO1DAC 0x55
98 #define RC5T583_REG_LDO2DAC 0x56
99 #define RC5T583_REG_LDO3DAC 0x57
100 #define RC5T583_REG_LDO4DAC 0x58
101 #define RC5T583_REG_LDO5DAC 0x59
102 #define RC5T583_REG_LDO6DAC 0x5A
103 #define RC5T583_REG_LDO7DAC 0x5B
104 #define RC5T583_REG_LDO8DAC 0x5C
105 #define RC5T583_REG_LDO9DAC 0x5D
107 #define RC5T583_REG_DC0DAC_DS 0x60
108 #define RC5T583_REG_DC1DAC_DS 0x61
109 #define RC5T583_REG_DC2DAC_DS 0x62
110 #define RC5T583_REG_DC3DAC_DS 0x63
112 #define RC5T583_REG_LDO0DAC_DS 0x64
113 #define RC5T583_REG_LDO1DAC_DS 0x65
114 #define RC5T583_REG_LDO2DAC_DS 0x66
115 #define RC5T583_REG_LDO3DAC_DS 0x67
116 #define RC5T583_REG_LDO4DAC_DS 0x68
117 #define RC5T583_REG_LDO5DAC_DS 0x69
118 #define RC5T583_REG_LDO6DAC_DS 0x6A
119 #define RC5T583_REG_LDO7DAC_DS 0x6B
120 #define RC5T583_REG_LDO8DAC_DS 0x6C
121 #define RC5T583_REG_LDO9DAC_DS 0x6D
123 /* GPIO register base address */
124 #define RC5T583_GPIO_IOSEL 0xA0
125 #define RC5T583_GPIO_PDEN 0xA1
126 #define RC5T583_GPIO_IOOUT 0xA2
127 #define RC5T583_GPIO_PGSEL 0xA3
128 #define RC5T583_GPIO_GPINV 0xA4
129 #define RC5T583_GPIO_GPDEB 0xA5
130 #define RC5T583_GPIO_GPEDGE1 0xA6
131 #define RC5T583_GPIO_GPEDGE2 0xA7
132 #define RC5T583_GPIO_EN_INT 0xA8
133 #define RC5T583_GPIO_MON_IOIN 0xAB
134 #define RC5T583_GPIO_GPOFUNC 0xAC
137 #define RC5T583_RTC_SEC 0xE0
138 #define RC5T583_RTC_MIN 0xE1
139 #define RC5T583_RTC_HOUR 0xE2
140 #define RC5T583_RTC_WDAY 0xE3
141 #define RC5T583_RTC_DAY 0xE4
142 #define RC5T583_RTC_MONTH 0xE5
143 #define RC5T583_RTC_YEAR 0xE6
144 #define RC5T583_RTC_ADJ 0xE7
145 #define RC5T583_RTC_AW_MIN 0xE8
146 #define RC5T583_RTC_AW_HOUR 0xE9
147 #define RC5T583_RTC_AW_WEEK 0xEA
148 #define RC5T583_RTC_AD_MIN 0xEB
149 #define RC5T583_RTC_AD_HOUR 0xEC
150 #define RC5T583_RTC_CTL1 0xED
151 #define RC5T583_RTC_CTL2 0xEE
152 #define RC5T583_RTC_AY_MIN 0xF0
153 #define RC5T583_RTC_AY_HOUR 0xF1
154 #define RC5T583_RTC_AY_DAY 0xF2
155 #define RC5T583_RTC_AY_MONTH 0xF3
156 #define RC5T583_RTC_AY_YEAR 0xF4
158 #define RC5T583_MAX_REG 0xF7
159 #define RC5T583_NUM_REGS (RC5T583_MAX_REG + 1)
161 /* RICOH_RC5T583 IRQ definitions */
168 RC5T583_IRQ_ONKEY_OFF
,
170 RC5T583_IRQ_EN_PWRREQ1
,
171 RC5T583_IRQ_EN_PWRREQ2
,
172 RC5T583_IRQ_PRE_VINDET
,
207 /* Should be last entry */
211 /* Ricoh583 gpio definitions */
222 /* Should be last entry */
251 /* Should be last entry */
256 * Ricoh pmic RC5T583 supports sleep through two external controls.
257 * The output of gpios and regulator can be enable/disable through
258 * this external signals.
261 RC5T583_EXT_PWRREQ1_CONTROL
= 0x1,
262 RC5T583_EXT_PWRREQ2_CONTROL
= 0x2,
266 RC5T583_REGULATOR_DC0
,
267 RC5T583_REGULATOR_DC1
,
268 RC5T583_REGULATOR_DC2
,
269 RC5T583_REGULATOR_DC3
,
270 RC5T583_REGULATOR_LDO0
,
271 RC5T583_REGULATOR_LDO1
,
272 RC5T583_REGULATOR_LDO2
,
273 RC5T583_REGULATOR_LDO3
,
274 RC5T583_REGULATOR_LDO4
,
275 RC5T583_REGULATOR_LDO5
,
276 RC5T583_REGULATOR_LDO6
,
277 RC5T583_REGULATOR_LDO7
,
278 RC5T583_REGULATOR_LDO8
,
279 RC5T583_REGULATOR_LDO9
,
281 /* Should be last entry */
282 RC5T583_REGULATOR_MAX
,
287 struct regmap
*regmap
;
290 struct mutex irq_lock
;
291 unsigned long group_irq_en
[MAX_MAIN_INTERRUPT
];
293 /* For main interrupt bits in INTC */
294 uint8_t intc_inten_reg
;
296 /* For group interrupt bits and address */
297 uint8_t irq_en_reg
[RC5T583_MAX_INTERRUPT_EN_REGS
];
300 uint8_t gpedge_reg
[RC5T583_MAX_GPEDGE_REG
];
304 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
305 * The board specific data is provided through this structure.
306 * @irq_base: Irq base number on which this device registers their interrupts.
307 * @gpio_base: GPIO base from which gpio of this device will start.
308 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
309 * @regulator_deepsleep_slot: The slot number on which device goes to sleep
310 * in device sleep mode.
311 * @regulator_ext_pwr_control: External power request regulator control. The
312 * regulator output enable/disable is controlled by the external
313 * power request input state.
314 * @reg_init_data: Regulator init data.
317 struct rc5t583_platform_data
{
320 bool enable_shutdown
;
321 int regulator_deepsleep_slot
[RC5T583_REGULATOR_MAX
];
322 unsigned long regulator_ext_pwr_control
[RC5T583_REGULATOR_MAX
];
323 struct regulator_init_data
*reg_init_data
[RC5T583_REGULATOR_MAX
];
326 static inline int rc5t583_write(struct device
*dev
, uint8_t reg
, uint8_t val
)
328 struct rc5t583
*rc5t583
= dev_get_drvdata(dev
);
329 return regmap_write(rc5t583
->regmap
, reg
, val
);
332 static inline int rc5t583_read(struct device
*dev
, uint8_t reg
, uint8_t *val
)
334 struct rc5t583
*rc5t583
= dev_get_drvdata(dev
);
337 ret
= regmap_read(rc5t583
->regmap
, reg
, &ival
);
339 *val
= (uint8_t)ival
;
343 static inline int rc5t583_set_bits(struct device
*dev
, unsigned int reg
,
344 unsigned int bit_mask
)
346 struct rc5t583
*rc5t583
= dev_get_drvdata(dev
);
347 return regmap_update_bits(rc5t583
->regmap
, reg
, bit_mask
, bit_mask
);
350 static inline int rc5t583_clear_bits(struct device
*dev
, unsigned int reg
,
351 unsigned int bit_mask
)
353 struct rc5t583
*rc5t583
= dev_get_drvdata(dev
);
354 return regmap_update_bits(rc5t583
->regmap
, reg
, bit_mask
, 0);
357 static inline int rc5t583_update(struct device
*dev
, unsigned int reg
,
358 unsigned int val
, unsigned int mask
)
360 struct rc5t583
*rc5t583
= dev_get_drvdata(dev
);
361 return regmap_update_bits(rc5t583
->regmap
, reg
, mask
, val
);
364 int rc5t583_ext_power_req_config(struct device
*dev
, int deepsleep_id
,
365 int ext_pwr_req
, int deepsleep_slot_nr
);
366 int rc5t583_irq_init(struct rc5t583
*rc5t583
, int irq
, int irq_base
);
367 int rc5t583_irq_exit(struct rc5t583
*rc5t583
);