include/linux/mfd/tmio.h

   1 #ifndef MFD_TMIO_H
   2 #define MFD_TMIO_H
   3
   4 #include <linux/device.h>
   5 #include <linux/fb.h>
   6 #include <linux/io.h>
   7 #include <linux/jiffies.h>
   8 #include <linux/mmc/card.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/pm_runtime.h>
  11
  12 #define tmio_ioread8(addr) readb(addr)
  13 #define tmio_ioread16(addr) readw(addr)
  14 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
  15 #define tmio_ioread32(addr) \
  16         (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
  17
  18 #define tmio_iowrite8(val, addr) writeb((val), (addr))
  19 #define tmio_iowrite16(val, addr) writew((val), (addr))
  20 #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
  21 #define tmio_iowrite32(val, addr) \
  22         do { \
  23         writew((val),       (addr)); \
  24         writew((val) >> 16, (addr) + 2); \
  25         } while (0)
  26
  27 #define CNF_CMD     0x04
  28 #define CNF_CTL_BASE   0x10
  29 #define CNF_INT_PIN  0x3d
  30 #define CNF_STOP_CLK_CTL 0x40
  31 #define CNF_GCLK_CTL 0x41
  32 #define CNF_SD_CLK_MODE 0x42
  33 #define CNF_PIN_STATUS 0x44
  34 #define CNF_PWR_CTL_1 0x48
  35 #define CNF_PWR_CTL_2 0x49
  36 #define CNF_PWR_CTL_3 0x4a
  37 #define CNF_CARD_DETECT_MODE 0x4c
  38 #define CNF_SD_SLOT 0x50
  39 #define CNF_EXT_GCLK_CTL_1 0xf0
  40 #define CNF_EXT_GCLK_CTL_2 0xf1
  41 #define CNF_EXT_GCLK_CTL_3 0xf9
  42 #define CNF_SD_LED_EN_1 0xfa
  43 #define CNF_SD_LED_EN_2 0xfe
  44
  45 #define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
  46
  47 #define sd_config_write8(base, shift, reg, val) \
  48         tmio_iowrite8((val), (base) + ((reg) << (shift)))
  49 #define sd_config_write16(base, shift, reg, val) \
  50         tmio_iowrite16((val), (base) + ((reg) << (shift)))
  51 #define sd_config_write32(base, shift, reg, val) \
  52         do { \
  53                 tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
  54                 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
  55         } while (0)
  56
  57 /* tmio MMC platform flags */
  58 #define TMIO_MMC_WRPROTECT_DISABLE      (1 << 0)
  59 /*
  60  * Some controllers can support a 2-byte block size when the bus width
  61  * is configured in 4-bit mode.
  62  */
  63 #define TMIO_MMC_BLKSZ_2BYTES           (1 << 1)
  64 /*
  65  * Some controllers can support SDIO IRQ signalling.
  66  */
  67 #define TMIO_MMC_SDIO_IRQ               (1 << 2)
  68
  69 /* Some features are only available or tested on RCar Gen2 or later */
  70 #define TMIO_MMC_MIN_RCAR2              (1 << 3)
  71
  72 /*
  73  * Some controllers require waiting for the SD bus to become
  74  * idle before writing to some registers.
  75  */
  76 #define TMIO_MMC_HAS_IDLE_WAIT          (1 << 4)
  77 /*
  78  * A GPIO is used for card hotplug detection. We need an extra flag for this,
  79  * because 0 is a valid GPIO number too, and requiring users to specify
  80  * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
  81  */
  82 #define TMIO_MMC_USE_GPIO_CD            (1 << 5)
  83
  84 /*
  85  * Some controllers doesn't have over 0x100 register.
  86  * it is used to checking accessibility of
  87  * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
  88  */
  89 #define TMIO_MMC_HAVE_HIGH_REG          (1 << 6)
  90
  91 /*
  92  * Some controllers have CMD12 automatically
  93  * issue/non-issue register
  94  */
  95 #define TMIO_MMC_HAVE_CMD12_CTRL        (1 << 7)
  96
  97 /*
  98  * Some controllers needs to set 1 on SDIO status reserved bits
  99  */
 100 #define TMIO_MMC_SDIO_STATUS_QUIRK      (1 << 8)
 101
 102 /*
 103  * Some controllers have a 32-bit wide data port register
 104  */
 105 #define TMIO_MMC_32BIT_DATA_PORT        (1 << 9)
 106
 107 /*
 108  * Some controllers allows to set SDx actual clock
 109  */
 110 #define TMIO_MMC_CLK_ACTUAL             (1 << 10)
 111
 112 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
 113 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
 114 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
 115 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
 116
 117 struct dma_chan;
 118
 119 /*
 120  * data for the MMC controller
 121  */
 122 struct tmio_mmc_data {
 123         void                            *chan_priv_tx;
 124         void                            *chan_priv_rx;
 125         unsigned int                    hclk;
 126         unsigned long                   capabilities;
 127         unsigned long                   capabilities2;
 128         unsigned long                   flags;
 129         u32                             ocr_mask;       /* available voltages */
 130         unsigned int                    cd_gpio;
 131         int                             alignment_shift;
 132         dma_addr_t                      dma_rx_offset;
 133         void (*set_pwr)(struct platform_device *host, int state);
 134         void (*set_clk_div)(struct platform_device *host, int state);
 135 };
 136
 137 /*
 138  * data for the NAND controller
 139  */
 140 struct tmio_nand_data {
 141         struct nand_bbt_descr   *badblock_pattern;
 142         struct mtd_partition    *partition;
 143         unsigned int            num_partitions;
 144 };
 145
 146 #define FBIO_TMIO_ACC_WRITE     0x7C639300
 147 #define FBIO_TMIO_ACC_SYNC      0x7C639301
 148
 149 struct tmio_fb_data {
 150         int                     (*lcd_set_power)(struct platform_device *fb_dev,
 151                                                                 bool on);
 152         int                     (*lcd_mode)(struct platform_device *fb_dev,
 153                                         const struct fb_videomode *mode);
 154         int                     num_modes;
 155         struct fb_videomode     *modes;
 156
 157         /* in mm: size of screen */
 158         int                     height;
 159         int                     width;
 160 };
 161
 162
 163 #endif