2 * Copyright (c) 2006 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/dma-mapping.h>
37 #include <linux/if_link.h>
40 /* initialization and general commands */
41 MLX4_CMD_SYS_EN
= 0x1,
42 MLX4_CMD_SYS_DIS
= 0x2,
43 MLX4_CMD_MAP_FA
= 0xfff,
44 MLX4_CMD_UNMAP_FA
= 0xffe,
45 MLX4_CMD_RUN_FW
= 0xff6,
46 MLX4_CMD_MOD_STAT_CFG
= 0x34,
47 MLX4_CMD_QUERY_DEV_CAP
= 0x3,
48 MLX4_CMD_QUERY_FW
= 0x4,
49 MLX4_CMD_ENABLE_LAM
= 0xff8,
50 MLX4_CMD_DISABLE_LAM
= 0xff7,
51 MLX4_CMD_QUERY_DDR
= 0x5,
52 MLX4_CMD_QUERY_ADAPTER
= 0x6,
53 MLX4_CMD_INIT_HCA
= 0x7,
54 MLX4_CMD_CLOSE_HCA
= 0x8,
55 MLX4_CMD_INIT_PORT
= 0x9,
56 MLX4_CMD_CLOSE_PORT
= 0xa,
57 MLX4_CMD_QUERY_HCA
= 0xb,
58 MLX4_CMD_QUERY_PORT
= 0x43,
59 MLX4_CMD_SENSE_PORT
= 0x4d,
60 MLX4_CMD_HW_HEALTH_CHECK
= 0x50,
61 MLX4_CMD_SET_PORT
= 0xc,
62 MLX4_CMD_SET_NODE
= 0x5a,
63 MLX4_CMD_QUERY_FUNC
= 0x56,
64 MLX4_CMD_ACCESS_DDR
= 0x2e,
65 MLX4_CMD_MAP_ICM
= 0xffa,
66 MLX4_CMD_UNMAP_ICM
= 0xff9,
67 MLX4_CMD_MAP_ICM_AUX
= 0xffc,
68 MLX4_CMD_UNMAP_ICM_AUX
= 0xffb,
69 MLX4_CMD_SET_ICM_SIZE
= 0xffd,
70 MLX4_CMD_ACCESS_REG
= 0x3b,
71 MLX4_CMD_ALLOCATE_VPP
= 0x80,
72 MLX4_CMD_SET_VPORT_QOS
= 0x81,
74 /*master notify fw on finish for slave's flr*/
75 MLX4_CMD_INFORM_FLR_DONE
= 0x5b,
76 MLX4_CMD_VIRT_PORT_MAP
= 0x5c,
77 MLX4_CMD_GET_OP_REQ
= 0x59,
80 MLX4_CMD_SW2HW_MPT
= 0xd,
81 MLX4_CMD_QUERY_MPT
= 0xe,
82 MLX4_CMD_HW2SW_MPT
= 0xf,
83 MLX4_CMD_READ_MTT
= 0x10,
84 MLX4_CMD_WRITE_MTT
= 0x11,
85 MLX4_CMD_SYNC_TPT
= 0x2f,
88 MLX4_CMD_MAP_EQ
= 0x12,
89 MLX4_CMD_SW2HW_EQ
= 0x13,
90 MLX4_CMD_HW2SW_EQ
= 0x14,
91 MLX4_CMD_QUERY_EQ
= 0x15,
94 MLX4_CMD_SW2HW_CQ
= 0x16,
95 MLX4_CMD_HW2SW_CQ
= 0x17,
96 MLX4_CMD_QUERY_CQ
= 0x18,
97 MLX4_CMD_MODIFY_CQ
= 0x2c,
100 MLX4_CMD_SW2HW_SRQ
= 0x35,
101 MLX4_CMD_HW2SW_SRQ
= 0x36,
102 MLX4_CMD_QUERY_SRQ
= 0x37,
103 MLX4_CMD_ARM_SRQ
= 0x40,
106 MLX4_CMD_RST2INIT_QP
= 0x19,
107 MLX4_CMD_INIT2RTR_QP
= 0x1a,
108 MLX4_CMD_RTR2RTS_QP
= 0x1b,
109 MLX4_CMD_RTS2RTS_QP
= 0x1c,
110 MLX4_CMD_SQERR2RTS_QP
= 0x1d,
111 MLX4_CMD_2ERR_QP
= 0x1e,
112 MLX4_CMD_RTS2SQD_QP
= 0x1f,
113 MLX4_CMD_SQD2SQD_QP
= 0x38,
114 MLX4_CMD_SQD2RTS_QP
= 0x20,
115 MLX4_CMD_2RST_QP
= 0x21,
116 MLX4_CMD_QUERY_QP
= 0x22,
117 MLX4_CMD_INIT2INIT_QP
= 0x2d,
118 MLX4_CMD_SUSPEND_QP
= 0x32,
119 MLX4_CMD_UNSUSPEND_QP
= 0x33,
120 MLX4_CMD_UPDATE_QP
= 0x61,
121 /* special QP and management commands */
122 MLX4_CMD_CONF_SPECIAL_QP
= 0x23,
123 MLX4_CMD_MAD_IFC
= 0x24,
124 MLX4_CMD_MAD_DEMUX
= 0x203,
126 /* multicast commands */
127 MLX4_CMD_READ_MCG
= 0x25,
128 MLX4_CMD_WRITE_MCG
= 0x26,
129 MLX4_CMD_MGID_HASH
= 0x27,
131 /* miscellaneous commands */
132 MLX4_CMD_DIAG_RPRT
= 0x30,
134 MLX4_CMD_CONFIG_DEV
= 0x3a,
135 MLX4_CMD_ACCESS_MEM
= 0x2e,
136 MLX4_CMD_SET_VEP
= 0x52,
138 /* Ethernet specific commands */
139 MLX4_CMD_SET_VLAN_FLTR
= 0x47,
140 MLX4_CMD_SET_MCAST_FLTR
= 0x48,
141 MLX4_CMD_DUMP_ETH_STATS
= 0x49,
143 /* Communication channel commands */
144 MLX4_CMD_ARM_COMM_CHANNEL
= 0x57,
145 MLX4_CMD_GEN_EQE
= 0x58,
147 /* virtual commands */
148 MLX4_CMD_ALLOC_RES
= 0xf00,
149 MLX4_CMD_FREE_RES
= 0xf01,
150 MLX4_CMD_MCAST_ATTACH
= 0xf05,
151 MLX4_CMD_UCAST_ATTACH
= 0xf06,
152 MLX4_CMD_PROMISC
= 0xf08,
153 MLX4_CMD_QUERY_FUNC_CAP
= 0xf0a,
154 MLX4_CMD_QP_ATTACH
= 0xf0b,
157 MLX4_CMD_QUERY_DEBUG_MSG
= 0x2a,
158 MLX4_CMD_SET_DEBUG_MSG
= 0x2b,
160 /* statistics commands */
161 MLX4_CMD_QUERY_IF_STAT
= 0X54,
162 MLX4_CMD_SET_IF_STAT
= 0X55,
164 /* register/delete flow steering network rules */
165 MLX4_QP_FLOW_STEERING_ATTACH
= 0x65,
166 MLX4_QP_FLOW_STEERING_DETACH
= 0x66,
167 MLX4_FLOW_STEERING_IB_UC_QP_RANGE
= 0x64,
169 /* Update and read QCN parameters */
170 MLX4_CMD_CONGESTION_CTRL_OPCODE
= 0x68,
174 MLX4_CMD_TIME_CLASS_A
= 60000,
175 MLX4_CMD_TIME_CLASS_B
= 60000,
176 MLX4_CMD_TIME_CLASS_C
= 60000,
180 /* virtual to physical port mapping opcode modifiers */
181 MLX4_GET_PORT_VIRT2PHY
= 0x0,
182 MLX4_SET_PORT_VIRT2PHY
= 0x1,
186 MLX4_MAILBOX_SIZE
= 4096,
187 MLX4_ACCESS_MEM_ALIGN
= 256,
191 /* Set port opcode modifiers */
192 MLX4_SET_PORT_IB_OPCODE
= 0x0,
193 MLX4_SET_PORT_ETH_OPCODE
= 0x1,
194 MLX4_SET_PORT_BEACON_OPCODE
= 0x4,
198 /* Set port Ethernet input modifiers */
199 MLX4_SET_PORT_GENERAL
= 0x0,
200 MLX4_SET_PORT_RQP_CALC
= 0x1,
201 MLX4_SET_PORT_MAC_TABLE
= 0x2,
202 MLX4_SET_PORT_VLAN_TABLE
= 0x3,
203 MLX4_SET_PORT_PRIO_MAP
= 0x4,
204 MLX4_SET_PORT_GID_TABLE
= 0x5,
205 MLX4_SET_PORT_PRIO2TC
= 0x8,
206 MLX4_SET_PORT_SCHEDULER
= 0x9,
207 MLX4_SET_PORT_VXLAN
= 0xB
211 MLX4_CMD_MAD_DEMUX_CONFIG
= 0,
212 MLX4_CMD_MAD_DEMUX_QUERY_STATE
= 1,
213 MLX4_CMD_MAD_DEMUX_QUERY_RESTR
= 2, /* Query mad demux restrictions */
222 * MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP -
223 * Receive checksum value is reported in CQE also for non TCP/UDP packets.
225 * MLX4_RX_CSUM_MODE_L4 -
226 * L4_CSUM bit in CQE, which indicates whether or not L4 checksum
227 * was validated correctly, is supported.
229 * MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP -
230 * IP_OK CQE's field is supported also for non TCP/UDP IP packets.
232 * MLX4_RX_CSUM_MODE_MULTI_VLAN -
233 * Receive Checksum offload is supported for packets with more than 2 vlan headers.
235 enum mlx4_rx_csum_mode
{
236 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP
= 1UL << 0,
237 MLX4_RX_CSUM_MODE_L4
= 1UL << 1,
238 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP
= 1UL << 2,
239 MLX4_RX_CSUM_MODE_MULTI_VLAN
= 1UL << 3
242 struct mlx4_config_dev_params
{
244 u8 rx_csum_flags_port_1
;
245 u8 rx_csum_flags_port_2
;
248 enum mlx4_en_congestion_control_algorithm
{
249 MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT
= 0,
252 enum mlx4_en_congestion_control_opmod
{
253 MLX4_CONGESTION_CONTROL_GET_PARAMS
,
254 MLX4_CONGESTION_CONTROL_GET_STATISTICS
,
255 MLX4_CONGESTION_CONTROL_SET_PARAMS
= 4,
260 struct mlx4_cmd_mailbox
{
265 int __mlx4_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
266 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
267 u16 op
, unsigned long timeout
, int native
);
269 /* Invoke a command with no output parameter */
270 static inline int mlx4_cmd(struct mlx4_dev
*dev
, u64 in_param
, u32 in_modifier
,
271 u8 op_modifier
, u16 op
, unsigned long timeout
,
274 return __mlx4_cmd(dev
, in_param
, NULL
, 0, in_modifier
,
275 op_modifier
, op
, timeout
, native
);
278 /* Invoke a command with an output mailbox */
279 static inline int mlx4_cmd_box(struct mlx4_dev
*dev
, u64 in_param
, u64 out_param
,
280 u32 in_modifier
, u8 op_modifier
, u16 op
,
281 unsigned long timeout
, int native
)
283 return __mlx4_cmd(dev
, in_param
, &out_param
, 0, in_modifier
,
284 op_modifier
, op
, timeout
, native
);
288 * Invoke a command with an immediate output parameter (and copy the
289 * output into the caller's out_param pointer after the command
292 static inline int mlx4_cmd_imm(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
293 u32 in_modifier
, u8 op_modifier
, u16 op
,
294 unsigned long timeout
, int native
)
296 return __mlx4_cmd(dev
, in_param
, out_param
, 1, in_modifier
,
297 op_modifier
, op
, timeout
, native
);
300 struct mlx4_cmd_mailbox
*mlx4_alloc_cmd_mailbox(struct mlx4_dev
*dev
);
301 void mlx4_free_cmd_mailbox(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
);
303 u32
mlx4_comm_get_version(void);
304 int mlx4_set_vf_mac(struct mlx4_dev
*dev
, int port
, int vf
, u64 mac
);
305 int mlx4_set_vf_vlan(struct mlx4_dev
*dev
, int port
, int vf
, u16 vlan
, u8 qos
);
306 int mlx4_set_vf_rate(struct mlx4_dev
*dev
, int port
, int vf
, int min_tx_rate
,
308 int mlx4_set_vf_spoofchk(struct mlx4_dev
*dev
, int port
, int vf
, bool setting
);
309 int mlx4_get_vf_config(struct mlx4_dev
*dev
, int port
, int vf
, struct ifla_vf_info
*ivf
);
310 int mlx4_set_vf_link_state(struct mlx4_dev
*dev
, int port
, int vf
, int link_state
);
311 int mlx4_config_dev_retrieval(struct mlx4_dev
*dev
,
312 struct mlx4_config_dev_params
*params
);
313 void mlx4_cmd_wake_completions(struct mlx4_dev
*dev
);
314 void mlx4_report_internal_err_comm_event(struct mlx4_dev
*dev
);
316 * mlx4_get_slave_default_vlan -
317 * return true if VST ( default vlan)
318 * if VST, will return vlan & qos (if not NULL)
320 bool mlx4_get_slave_default_vlan(struct mlx4_dev
*dev
, int port
, int slave
,
323 #define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8)
324 #define COMM_CHAN_EVENT_INTERNAL_ERR (1 << 17)
326 #endif /* MLX4_CMD_H */