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1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/clocksource.h>
46
47 #define MAX_MSIX_P_PORT 17
48 #define MAX_MSIX 64
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
51
52 #define MLX4_NUM_UP 8
53 #define MLX4_NUM_TC 8
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
58 */
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
65
66 enum {
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 };
74
75 enum {
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
78 };
79
80 enum {
81 MLX4_MAX_PORTS = 2,
82 MLX4_MAX_PORT_PKEYS = 128
83 };
84
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
88 */
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
91
92 enum {
93 MLX4_BOARD_ID_LEN = 64
94 };
95
96 enum {
97 MLX4_MAX_NUM_PF = 16,
98 MLX4_MAX_NUM_VF = 64,
99 MLX4_MAX_NUM_VF_P_PORT = 64,
100 MLX4_MFUNC_MAX = 80,
101 MLX4_MAX_EQ_NUM = 1024,
102 MLX4_MFUNC_EQ_NUM = 4,
103 MLX4_MFUNC_MAX_EQES = 8,
104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
105 };
106
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
112 * B0 mode is in use.
113 */
114 enum {
115 MLX4_STEERING_MODE_A0,
116 MLX4_STEERING_MODE_B0,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
118 };
119
120 static inline const char *mlx4_steering_mode_str(int steering_mode)
121 {
122 switch (steering_mode) {
123 case MLX4_STEERING_MODE_A0:
124 return "A0 steering";
125
126 case MLX4_STEERING_MODE_B0:
127 return "B0 steering";
128
129 case MLX4_STEERING_MODE_DEVICE_MANAGED:
130 return "Device managed flow steering";
131
132 default:
133 return "Unrecognize steering mode";
134 }
135 }
136
137 enum {
138 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
139 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
140 };
141
142 enum {
143 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
144 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
145 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
146 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
147 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
148 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
149 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
150 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
151 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
152 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
153 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
154 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
155 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
156 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
157 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
158 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
159 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
160 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
161 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
162 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
163 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
164 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
165 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
166 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
167 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
168 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
169 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
173 };
174
175 enum {
176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
180 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
181 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
182 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
183 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
184 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
185 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
186 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
187 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
188 };
189
190 enum {
191 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
192 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
193 };
194
195 enum {
196 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
197 };
198
199 enum {
200 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
201 };
202
203
204 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
205
206 enum {
207 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
208 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
209 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
210 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
211 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
212 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
213 };
214
215 enum mlx4_event {
216 MLX4_EVENT_TYPE_COMP = 0x00,
217 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
218 MLX4_EVENT_TYPE_COMM_EST = 0x02,
219 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
220 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
221 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
222 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
223 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
224 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
225 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
226 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
227 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
228 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
229 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
230 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
231 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
232 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
233 MLX4_EVENT_TYPE_CMD = 0x0a,
234 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
235 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
236 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
237 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
238 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
239 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
240 MLX4_EVENT_TYPE_NONE = 0xff,
241 };
242
243 enum {
244 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
245 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
246 };
247
248 enum {
249 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
250 };
251
252 enum slave_port_state {
253 SLAVE_PORT_DOWN = 0,
254 SLAVE_PENDING_UP,
255 SLAVE_PORT_UP,
256 };
257
258 enum slave_port_gen_event {
259 SLAVE_PORT_GEN_EVENT_DOWN = 0,
260 SLAVE_PORT_GEN_EVENT_UP,
261 SLAVE_PORT_GEN_EVENT_NONE,
262 };
263
264 enum slave_port_state_event {
265 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
266 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
267 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
268 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
269 };
270
271 enum {
272 MLX4_PERM_LOCAL_READ = 1 << 10,
273 MLX4_PERM_LOCAL_WRITE = 1 << 11,
274 MLX4_PERM_REMOTE_READ = 1 << 12,
275 MLX4_PERM_REMOTE_WRITE = 1 << 13,
276 MLX4_PERM_ATOMIC = 1 << 14,
277 MLX4_PERM_BIND_MW = 1 << 15,
278 MLX4_PERM_MASK = 0xFC00
279 };
280
281 enum {
282 MLX4_OPCODE_NOP = 0x00,
283 MLX4_OPCODE_SEND_INVAL = 0x01,
284 MLX4_OPCODE_RDMA_WRITE = 0x08,
285 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
286 MLX4_OPCODE_SEND = 0x0a,
287 MLX4_OPCODE_SEND_IMM = 0x0b,
288 MLX4_OPCODE_LSO = 0x0e,
289 MLX4_OPCODE_RDMA_READ = 0x10,
290 MLX4_OPCODE_ATOMIC_CS = 0x11,
291 MLX4_OPCODE_ATOMIC_FA = 0x12,
292 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
293 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
294 MLX4_OPCODE_BIND_MW = 0x18,
295 MLX4_OPCODE_FMR = 0x19,
296 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
297 MLX4_OPCODE_CONFIG_CMD = 0x1f,
298
299 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
300 MLX4_RECV_OPCODE_SEND = 0x01,
301 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
302 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
303
304 MLX4_CQE_OPCODE_ERROR = 0x1e,
305 MLX4_CQE_OPCODE_RESIZE = 0x16,
306 };
307
308 enum {
309 MLX4_STAT_RATE_OFFSET = 5
310 };
311
312 enum mlx4_protocol {
313 MLX4_PROT_IB_IPV6 = 0,
314 MLX4_PROT_ETH,
315 MLX4_PROT_IB_IPV4,
316 MLX4_PROT_FCOE
317 };
318
319 enum {
320 MLX4_MTT_FLAG_PRESENT = 1
321 };
322
323 enum mlx4_qp_region {
324 MLX4_QP_REGION_FW = 0,
325 MLX4_QP_REGION_ETH_ADDR,
326 MLX4_QP_REGION_FC_ADDR,
327 MLX4_QP_REGION_FC_EXCH,
328 MLX4_NUM_QP_REGION
329 };
330
331 enum mlx4_port_type {
332 MLX4_PORT_TYPE_NONE = 0,
333 MLX4_PORT_TYPE_IB = 1,
334 MLX4_PORT_TYPE_ETH = 2,
335 MLX4_PORT_TYPE_AUTO = 3
336 };
337
338 enum mlx4_special_vlan_idx {
339 MLX4_NO_VLAN_IDX = 0,
340 MLX4_VLAN_MISS_IDX,
341 MLX4_VLAN_REGULAR
342 };
343
344 enum mlx4_steer_type {
345 MLX4_MC_STEER = 0,
346 MLX4_UC_STEER,
347 MLX4_NUM_STEERS
348 };
349
350 enum {
351 MLX4_NUM_FEXCH = 64 * 1024,
352 };
353
354 enum {
355 MLX4_MAX_FAST_REG_PAGES = 511,
356 };
357
358 enum {
359 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
360 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
361 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
362 };
363
364 /* Port mgmt change event handling */
365 enum {
366 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
367 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
368 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
369 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
370 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
371 };
372
373 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
374 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
375
376 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
377 {
378 return (major << 32) | (minor << 16) | subminor;
379 }
380
381 struct mlx4_phys_caps {
382 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
383 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
384 u32 num_phys_eqs;
385 u32 base_sqpn;
386 u32 base_proxy_sqpn;
387 u32 base_tunnel_sqpn;
388 };
389
390 struct mlx4_caps {
391 u64 fw_ver;
392 u32 function;
393 int num_ports;
394 int vl_cap[MLX4_MAX_PORTS + 1];
395 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
396 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
397 u64 def_mac[MLX4_MAX_PORTS + 1];
398 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
399 int gid_table_len[MLX4_MAX_PORTS + 1];
400 int pkey_table_len[MLX4_MAX_PORTS + 1];
401 int trans_type[MLX4_MAX_PORTS + 1];
402 int vendor_oui[MLX4_MAX_PORTS + 1];
403 int wavelength[MLX4_MAX_PORTS + 1];
404 u64 trans_code[MLX4_MAX_PORTS + 1];
405 int local_ca_ack_delay;
406 int num_uars;
407 u32 uar_page_size;
408 int bf_reg_size;
409 int bf_regs_per_page;
410 int max_sq_sg;
411 int max_rq_sg;
412 int num_qps;
413 int max_wqes;
414 int max_sq_desc_sz;
415 int max_rq_desc_sz;
416 int max_qp_init_rdma;
417 int max_qp_dest_rdma;
418 u32 *qp0_qkey;
419 u32 *qp0_proxy;
420 u32 *qp1_proxy;
421 u32 *qp0_tunnel;
422 u32 *qp1_tunnel;
423 int num_srqs;
424 int max_srq_wqes;
425 int max_srq_sge;
426 int reserved_srqs;
427 int num_cqs;
428 int max_cqes;
429 int reserved_cqs;
430 int num_eqs;
431 int reserved_eqs;
432 int num_comp_vectors;
433 int comp_pool;
434 int num_mpts;
435 int max_fmr_maps;
436 int num_mtts;
437 int fmr_reserved_mtts;
438 int reserved_mtts;
439 int reserved_mrws;
440 int reserved_uars;
441 int num_mgms;
442 int num_amgms;
443 int reserved_mcgs;
444 int num_qp_per_mgm;
445 int steering_mode;
446 int fs_log_max_ucast_qp_range_size;
447 int num_pds;
448 int reserved_pds;
449 int max_xrcds;
450 int reserved_xrcds;
451 int mtt_entry_sz;
452 u32 max_msg_sz;
453 u32 page_size_cap;
454 u64 flags;
455 u64 flags2;
456 u32 bmme_flags;
457 u32 reserved_lkey;
458 u16 stat_rate_support;
459 u8 port_width_cap[MLX4_MAX_PORTS + 1];
460 int max_gso_sz;
461 int max_rss_tbl_sz;
462 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
463 int reserved_qps;
464 int reserved_qps_base[MLX4_NUM_QP_REGION];
465 int log_num_macs;
466 int log_num_vlans;
467 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
468 u8 supported_type[MLX4_MAX_PORTS + 1];
469 u8 suggested_type[MLX4_MAX_PORTS + 1];
470 u8 default_sense[MLX4_MAX_PORTS + 1];
471 u32 port_mask[MLX4_MAX_PORTS + 1];
472 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
473 u32 max_counters;
474 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
475 u16 sqp_demux;
476 u32 eqe_size;
477 u32 cqe_size;
478 u8 eqe_factor;
479 u32 userspace_caps; /* userspace must be aware of these */
480 u32 function_caps; /* VFs must be aware of these */
481 u16 hca_core_clock;
482 u64 phys_port_id[MLX4_MAX_PORTS + 1];
483 int tunnel_offload_mode;
484 };
485
486 struct mlx4_buf_list {
487 void *buf;
488 dma_addr_t map;
489 };
490
491 struct mlx4_buf {
492 struct mlx4_buf_list direct;
493 struct mlx4_buf_list *page_list;
494 int nbufs;
495 int npages;
496 int page_shift;
497 };
498
499 struct mlx4_mtt {
500 u32 offset;
501 int order;
502 int page_shift;
503 };
504
505 enum {
506 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
507 };
508
509 struct mlx4_db_pgdir {
510 struct list_head list;
511 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
512 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
513 unsigned long *bits[2];
514 __be32 *db_page;
515 dma_addr_t db_dma;
516 };
517
518 struct mlx4_ib_user_db_page;
519
520 struct mlx4_db {
521 __be32 *db;
522 union {
523 struct mlx4_db_pgdir *pgdir;
524 struct mlx4_ib_user_db_page *user_page;
525 } u;
526 dma_addr_t dma;
527 int index;
528 int order;
529 };
530
531 struct mlx4_hwq_resources {
532 struct mlx4_db db;
533 struct mlx4_mtt mtt;
534 struct mlx4_buf buf;
535 };
536
537 struct mlx4_mr {
538 struct mlx4_mtt mtt;
539 u64 iova;
540 u64 size;
541 u32 key;
542 u32 pd;
543 u32 access;
544 int enabled;
545 };
546
547 enum mlx4_mw_type {
548 MLX4_MW_TYPE_1 = 1,
549 MLX4_MW_TYPE_2 = 2,
550 };
551
552 struct mlx4_mw {
553 u32 key;
554 u32 pd;
555 enum mlx4_mw_type type;
556 int enabled;
557 };
558
559 struct mlx4_fmr {
560 struct mlx4_mr mr;
561 struct mlx4_mpt_entry *mpt;
562 __be64 *mtts;
563 dma_addr_t dma_handle;
564 int max_pages;
565 int max_maps;
566 int maps;
567 u8 page_shift;
568 };
569
570 struct mlx4_uar {
571 unsigned long pfn;
572 int index;
573 struct list_head bf_list;
574 unsigned free_bf_bmap;
575 void __iomem *map;
576 void __iomem *bf_map;
577 };
578
579 struct mlx4_bf {
580 unsigned long offset;
581 int buf_size;
582 struct mlx4_uar *uar;
583 void __iomem *reg;
584 };
585
586 struct mlx4_cq {
587 void (*comp) (struct mlx4_cq *);
588 void (*event) (struct mlx4_cq *, enum mlx4_event);
589
590 struct mlx4_uar *uar;
591
592 u32 cons_index;
593
594 u16 irq;
595 __be32 *set_ci_db;
596 __be32 *arm_db;
597 int arm_sn;
598
599 int cqn;
600 unsigned vector;
601
602 atomic_t refcount;
603 struct completion free;
604 };
605
606 struct mlx4_qp {
607 void (*event) (struct mlx4_qp *, enum mlx4_event);
608
609 int qpn;
610
611 atomic_t refcount;
612 struct completion free;
613 };
614
615 struct mlx4_srq {
616 void (*event) (struct mlx4_srq *, enum mlx4_event);
617
618 int srqn;
619 int max;
620 int max_gs;
621 int wqe_shift;
622
623 atomic_t refcount;
624 struct completion free;
625 };
626
627 struct mlx4_av {
628 __be32 port_pd;
629 u8 reserved1;
630 u8 g_slid;
631 __be16 dlid;
632 u8 reserved2;
633 u8 gid_index;
634 u8 stat_rate;
635 u8 hop_limit;
636 __be32 sl_tclass_flowlabel;
637 u8 dgid[16];
638 };
639
640 struct mlx4_eth_av {
641 __be32 port_pd;
642 u8 reserved1;
643 u8 smac_idx;
644 u16 reserved2;
645 u8 reserved3;
646 u8 gid_index;
647 u8 stat_rate;
648 u8 hop_limit;
649 __be32 sl_tclass_flowlabel;
650 u8 dgid[16];
651 u8 s_mac[6];
652 u8 reserved4[2];
653 __be16 vlan;
654 u8 mac[ETH_ALEN];
655 };
656
657 union mlx4_ext_av {
658 struct mlx4_av ib;
659 struct mlx4_eth_av eth;
660 };
661
662 struct mlx4_counter {
663 u8 reserved1[3];
664 u8 counter_mode;
665 __be32 num_ifc;
666 u32 reserved2[2];
667 __be64 rx_frames;
668 __be64 rx_bytes;
669 __be64 tx_frames;
670 __be64 tx_bytes;
671 };
672
673 struct mlx4_quotas {
674 int qp;
675 int cq;
676 int srq;
677 int mpt;
678 int mtt;
679 int counter;
680 int xrcd;
681 };
682
683 struct mlx4_vf_dev {
684 u8 min_port;
685 u8 n_ports;
686 };
687
688 struct mlx4_dev {
689 struct pci_dev *pdev;
690 unsigned long flags;
691 unsigned long num_slaves;
692 struct mlx4_caps caps;
693 struct mlx4_phys_caps phys_caps;
694 struct mlx4_quotas quotas;
695 struct radix_tree_root qp_table_tree;
696 u8 rev_id;
697 char board_id[MLX4_BOARD_ID_LEN];
698 int num_vfs;
699 int numa_node;
700 int oper_log_mgm_entry_size;
701 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
702 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
703 struct mlx4_vf_dev *dev_vfs;
704 };
705
706 struct mlx4_eqe {
707 u8 reserved1;
708 u8 type;
709 u8 reserved2;
710 u8 subtype;
711 union {
712 u32 raw[6];
713 struct {
714 __be32 cqn;
715 } __packed comp;
716 struct {
717 u16 reserved1;
718 __be16 token;
719 u32 reserved2;
720 u8 reserved3[3];
721 u8 status;
722 __be64 out_param;
723 } __packed cmd;
724 struct {
725 __be32 qpn;
726 } __packed qp;
727 struct {
728 __be32 srqn;
729 } __packed srq;
730 struct {
731 __be32 cqn;
732 u32 reserved1;
733 u8 reserved2[3];
734 u8 syndrome;
735 } __packed cq_err;
736 struct {
737 u32 reserved1[2];
738 __be32 port;
739 } __packed port_change;
740 struct {
741 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
742 u32 reserved;
743 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
744 } __packed comm_channel_arm;
745 struct {
746 u8 port;
747 u8 reserved[3];
748 __be64 mac;
749 } __packed mac_update;
750 struct {
751 __be32 slave_id;
752 } __packed flr_event;
753 struct {
754 __be16 current_temperature;
755 __be16 warning_threshold;
756 } __packed warming;
757 struct {
758 u8 reserved[3];
759 u8 port;
760 union {
761 struct {
762 __be16 mstr_sm_lid;
763 __be16 port_lid;
764 __be32 changed_attr;
765 u8 reserved[3];
766 u8 mstr_sm_sl;
767 __be64 gid_prefix;
768 } __packed port_info;
769 struct {
770 __be32 block_ptr;
771 __be32 tbl_entries_mask;
772 } __packed tbl_change_info;
773 } params;
774 } __packed port_mgmt_change;
775 } event;
776 u8 slave_id;
777 u8 reserved3[2];
778 u8 owner;
779 } __packed;
780
781 struct mlx4_init_port_param {
782 int set_guid0;
783 int set_node_guid;
784 int set_si_guid;
785 u16 mtu;
786 int port_width_cap;
787 u16 vl_cap;
788 u16 max_gid;
789 u16 max_pkey;
790 u64 guid0;
791 u64 node_guid;
792 u64 si_guid;
793 };
794
795 #define mlx4_foreach_port(port, dev, type) \
796 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
797 if ((type) == (dev)->caps.port_mask[(port)])
798
799 #define mlx4_foreach_non_ib_transport_port(port, dev) \
800 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
801 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
802
803 #define mlx4_foreach_ib_transport_port(port, dev) \
804 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
805 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
806 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
807
808 #define MLX4_INVALID_SLAVE_ID 0xFF
809
810 void handle_port_mgmt_change_event(struct work_struct *work);
811
812 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
813 {
814 return dev->caps.function;
815 }
816
817 static inline int mlx4_is_master(struct mlx4_dev *dev)
818 {
819 return dev->flags & MLX4_FLAG_MASTER;
820 }
821
822 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
823 {
824 return dev->phys_caps.base_sqpn + 8 +
825 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
826 }
827
828 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
829 {
830 return (qpn < dev->phys_caps.base_sqpn + 8 +
831 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
832 }
833
834 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
835 {
836 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
837
838 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
839 return 1;
840
841 return 0;
842 }
843
844 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
845 {
846 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
847 }
848
849 static inline int mlx4_is_slave(struct mlx4_dev *dev)
850 {
851 return dev->flags & MLX4_FLAG_SLAVE;
852 }
853
854 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
855 struct mlx4_buf *buf, gfp_t gfp);
856 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
857 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
858 {
859 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
860 return buf->direct.buf + offset;
861 else
862 return buf->page_list[offset >> PAGE_SHIFT].buf +
863 (offset & (PAGE_SIZE - 1));
864 }
865
866 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
867 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
868 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
869 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
870
871 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
872 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
873 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
874 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
875
876 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
877 struct mlx4_mtt *mtt);
878 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
879 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
880
881 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
882 int npages, int page_shift, struct mlx4_mr *mr);
883 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
884 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
885 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
886 struct mlx4_mw *mw);
887 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
888 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
889 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
890 int start_index, int npages, u64 *page_list);
891 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
892 struct mlx4_buf *buf, gfp_t gfp);
893
894 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
895 gfp_t gfp);
896 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
897
898 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
899 int size, int max_direct);
900 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
901 int size);
902
903 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
904 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
905 unsigned vector, int collapsed, int timestamp_en);
906 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
907
908 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
909 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
910
911 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
912 gfp_t gfp);
913 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
914
915 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
916 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
917 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
918 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
919 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
920
921 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
922 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
923
924 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
925 int block_mcast_loopback, enum mlx4_protocol prot);
926 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
927 enum mlx4_protocol prot);
928 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
929 u8 port, int block_mcast_loopback,
930 enum mlx4_protocol protocol, u64 *reg_id);
931 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
932 enum mlx4_protocol protocol, u64 reg_id);
933
934 enum {
935 MLX4_DOMAIN_UVERBS = 0x1000,
936 MLX4_DOMAIN_ETHTOOL = 0x2000,
937 MLX4_DOMAIN_RFS = 0x3000,
938 MLX4_DOMAIN_NIC = 0x5000,
939 };
940
941 enum mlx4_net_trans_rule_id {
942 MLX4_NET_TRANS_RULE_ID_ETH = 0,
943 MLX4_NET_TRANS_RULE_ID_IB,
944 MLX4_NET_TRANS_RULE_ID_IPV6,
945 MLX4_NET_TRANS_RULE_ID_IPV4,
946 MLX4_NET_TRANS_RULE_ID_TCP,
947 MLX4_NET_TRANS_RULE_ID_UDP,
948 MLX4_NET_TRANS_RULE_ID_VXLAN,
949 MLX4_NET_TRANS_RULE_NUM, /* should be last */
950 };
951
952 extern const u16 __sw_id_hw[];
953
954 static inline int map_hw_to_sw_id(u16 header_id)
955 {
956
957 int i;
958 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
959 if (header_id == __sw_id_hw[i])
960 return i;
961 }
962 return -EINVAL;
963 }
964
965 enum mlx4_net_trans_promisc_mode {
966 MLX4_FS_REGULAR = 1,
967 MLX4_FS_ALL_DEFAULT,
968 MLX4_FS_MC_DEFAULT,
969 MLX4_FS_UC_SNIFFER,
970 MLX4_FS_MC_SNIFFER,
971 MLX4_FS_MODE_NUM, /* should be last */
972 };
973
974 struct mlx4_spec_eth {
975 u8 dst_mac[ETH_ALEN];
976 u8 dst_mac_msk[ETH_ALEN];
977 u8 src_mac[ETH_ALEN];
978 u8 src_mac_msk[ETH_ALEN];
979 u8 ether_type_enable;
980 __be16 ether_type;
981 __be16 vlan_id_msk;
982 __be16 vlan_id;
983 };
984
985 struct mlx4_spec_tcp_udp {
986 __be16 dst_port;
987 __be16 dst_port_msk;
988 __be16 src_port;
989 __be16 src_port_msk;
990 };
991
992 struct mlx4_spec_ipv4 {
993 __be32 dst_ip;
994 __be32 dst_ip_msk;
995 __be32 src_ip;
996 __be32 src_ip_msk;
997 };
998
999 struct mlx4_spec_ib {
1000 __be32 l3_qpn;
1001 __be32 qpn_msk;
1002 u8 dst_gid[16];
1003 u8 dst_gid_msk[16];
1004 };
1005
1006 struct mlx4_spec_vxlan {
1007 __be32 vni;
1008 __be32 vni_mask;
1009
1010 };
1011
1012 struct mlx4_spec_list {
1013 struct list_head list;
1014 enum mlx4_net_trans_rule_id id;
1015 union {
1016 struct mlx4_spec_eth eth;
1017 struct mlx4_spec_ib ib;
1018 struct mlx4_spec_ipv4 ipv4;
1019 struct mlx4_spec_tcp_udp tcp_udp;
1020 struct mlx4_spec_vxlan vxlan;
1021 };
1022 };
1023
1024 enum mlx4_net_trans_hw_rule_queue {
1025 MLX4_NET_TRANS_Q_FIFO,
1026 MLX4_NET_TRANS_Q_LIFO,
1027 };
1028
1029 struct mlx4_net_trans_rule {
1030 struct list_head list;
1031 enum mlx4_net_trans_hw_rule_queue queue_mode;
1032 bool exclusive;
1033 bool allow_loopback;
1034 enum mlx4_net_trans_promisc_mode promisc_mode;
1035 u8 port;
1036 u16 priority;
1037 u32 qpn;
1038 };
1039
1040 struct mlx4_net_trans_rule_hw_ctrl {
1041 __be16 prio;
1042 u8 type;
1043 u8 flags;
1044 u8 rsvd1;
1045 u8 funcid;
1046 u8 vep;
1047 u8 port;
1048 __be32 qpn;
1049 __be32 rsvd2;
1050 };
1051
1052 struct mlx4_net_trans_rule_hw_ib {
1053 u8 size;
1054 u8 rsvd1;
1055 __be16 id;
1056 u32 rsvd2;
1057 __be32 l3_qpn;
1058 __be32 qpn_mask;
1059 u8 dst_gid[16];
1060 u8 dst_gid_msk[16];
1061 } __packed;
1062
1063 struct mlx4_net_trans_rule_hw_eth {
1064 u8 size;
1065 u8 rsvd;
1066 __be16 id;
1067 u8 rsvd1[6];
1068 u8 dst_mac[6];
1069 u16 rsvd2;
1070 u8 dst_mac_msk[6];
1071 u16 rsvd3;
1072 u8 src_mac[6];
1073 u16 rsvd4;
1074 u8 src_mac_msk[6];
1075 u8 rsvd5;
1076 u8 ether_type_enable;
1077 __be16 ether_type;
1078 __be16 vlan_tag_msk;
1079 __be16 vlan_tag;
1080 } __packed;
1081
1082 struct mlx4_net_trans_rule_hw_tcp_udp {
1083 u8 size;
1084 u8 rsvd;
1085 __be16 id;
1086 __be16 rsvd1[3];
1087 __be16 dst_port;
1088 __be16 rsvd2;
1089 __be16 dst_port_msk;
1090 __be16 rsvd3;
1091 __be16 src_port;
1092 __be16 rsvd4;
1093 __be16 src_port_msk;
1094 } __packed;
1095
1096 struct mlx4_net_trans_rule_hw_ipv4 {
1097 u8 size;
1098 u8 rsvd;
1099 __be16 id;
1100 __be32 rsvd1;
1101 __be32 dst_ip;
1102 __be32 dst_ip_msk;
1103 __be32 src_ip;
1104 __be32 src_ip_msk;
1105 } __packed;
1106
1107 struct mlx4_net_trans_rule_hw_vxlan {
1108 u8 size;
1109 u8 rsvd;
1110 __be16 id;
1111 __be32 rsvd1;
1112 __be32 vni;
1113 __be32 vni_mask;
1114 } __packed;
1115
1116 struct _rule_hw {
1117 union {
1118 struct {
1119 u8 size;
1120 u8 rsvd;
1121 __be16 id;
1122 };
1123 struct mlx4_net_trans_rule_hw_eth eth;
1124 struct mlx4_net_trans_rule_hw_ib ib;
1125 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1126 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1127 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1128 };
1129 };
1130
1131 enum {
1132 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1133 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1134 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1135 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1136 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1137 };
1138
1139
1140 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1141 enum mlx4_net_trans_promisc_mode mode);
1142 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1143 enum mlx4_net_trans_promisc_mode mode);
1144 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1145 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1146 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1147 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1148 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1149
1150 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1151 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1152 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1153 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1154 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1155 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1156 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1157 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1158 u8 promisc);
1159 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1160 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1161 u8 *pg, u16 *ratelimit);
1162 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1163 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1164 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1165 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1166 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1167
1168 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1169 int npages, u64 iova, u32 *lkey, u32 *rkey);
1170 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1171 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1172 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1173 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1174 u32 *lkey, u32 *rkey);
1175 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1176 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1177 int mlx4_test_interrupts(struct mlx4_dev *dev);
1178 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1179 int *vector);
1180 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1181
1182 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1183
1184 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1185 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1186 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1187
1188 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1189 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1190
1191 int mlx4_flow_attach(struct mlx4_dev *dev,
1192 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1193 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1194 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1195 enum mlx4_net_trans_promisc_mode flow_type);
1196 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1197 enum mlx4_net_trans_rule_id id);
1198 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1199
1200 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1201 int port, int qpn, u16 prio, u64 *reg_id);
1202
1203 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1204 int i, int val);
1205
1206 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1207
1208 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1209 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1210 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1211 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1212 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1213 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1214 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1215
1216 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1217 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1218
1219 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1220 int *slave_id);
1221 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1222 u8 *gid);
1223
1224 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1225 u32 max_range_qpn);
1226
1227 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1228
1229 struct mlx4_active_ports {
1230 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1231 };
1232 /* Returns a bitmap of the physical ports which are assigned to slave */
1233 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1234
1235 /* Returns the physical port that represents the virtual port of the slave, */
1236 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1237 /* mapping is returned. */
1238 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1239
1240 struct mlx4_slaves_pport {
1241 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1242 };
1243 /* Returns a bitmap of all slaves that are assigned to port. */
1244 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1245 int port);
1246
1247 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1248 /* the ports that are set in crit_ports. */
1249 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1250 struct mlx4_dev *dev,
1251 const struct mlx4_active_ports *crit_ports);
1252
1253 /* Returns the slave's virtual port that represents the physical port. */
1254 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1255
1256 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1257
1258 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1259 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1260 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1261 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1262 int enable);
1263 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1264 struct mlx4_mpt_entry ***mpt_entry);
1265 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1266 struct mlx4_mpt_entry **mpt_entry);
1267 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1268 u32 pdn);
1269 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1270 struct mlx4_mpt_entry *mpt_entry,
1271 u32 access);
1272 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1273 struct mlx4_mpt_entry **mpt_entry);
1274 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1275 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1276 u64 iova, u64 size, int npages,
1277 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1278
1279 /* Returns true if running in low memory profile (kdump kernel) */
1280 static inline bool mlx4_low_memory_profile(void)
1281 {
1282 return is_kdump_kernel();
1283 }
1284
1285 #endif /* MLX4_DEVICE_H */
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