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[mirror_ubuntu-artful-kernel.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/atomic.h>
44
45 #include <linux/timecounter.h>
46
47 #define DEFAULT_UAR_PAGE_SHIFT 12
48
49 #define MAX_MSIX_P_PORT 17
50 #define MAX_MSIX 64
51 #define MIN_MSIX_P_PORT 5
52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
54
55 #define MLX4_MAX_100M_UNITS_VAL 255 /*
56 * work around: can't set values
57 * greater then this value when
58 * using 100 Mbps units.
59 */
60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63
64 #define MLX4_ROCE_MAX_GIDS 128
65 #define MLX4_ROCE_PF_GIDS 16
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7
75 };
76
77 enum {
78 MLX4_PORT_CAP_IS_SM = 1 << 1,
79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
80 };
81
82 enum {
83 MLX4_MAX_PORTS = 2,
84 MLX4_MAX_PORT_PKEYS = 128,
85 MLX4_MAX_PORT_GIDS = 128
86 };
87
88 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
89 * These qkeys must not be allowed for general use. This is a 64k range,
90 * and to test for violation, we use the mask (protect against future chg).
91 */
92 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
93 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
94
95 enum {
96 MLX4_BOARD_ID_LEN = 64
97 };
98
99 enum {
100 MLX4_MAX_NUM_PF = 16,
101 MLX4_MAX_NUM_VF = 126,
102 MLX4_MAX_NUM_VF_P_PORT = 64,
103 MLX4_MFUNC_MAX = 128,
104 MLX4_MAX_EQ_NUM = 1024,
105 MLX4_MFUNC_EQ_NUM = 4,
106 MLX4_MFUNC_MAX_EQES = 8,
107 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
108 };
109
110 /* Driver supports 3 diffrent device methods to manage traffic steering:
111 * -device managed - High level API for ib and eth flow steering. FW is
112 * managing flow steering tables.
113 * - B0 steering mode - Common low level API for ib and (if supported) eth.
114 * - A0 steering mode - Limited low level API for eth. In case of IB,
115 * B0 mode is in use.
116 */
117 enum {
118 MLX4_STEERING_MODE_A0,
119 MLX4_STEERING_MODE_B0,
120 MLX4_STEERING_MODE_DEVICE_MANAGED
121 };
122
123 enum {
124 MLX4_STEERING_DMFS_A0_DEFAULT,
125 MLX4_STEERING_DMFS_A0_DYNAMIC,
126 MLX4_STEERING_DMFS_A0_STATIC,
127 MLX4_STEERING_DMFS_A0_DISABLE,
128 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
129 };
130
131 static inline const char *mlx4_steering_mode_str(int steering_mode)
132 {
133 switch (steering_mode) {
134 case MLX4_STEERING_MODE_A0:
135 return "A0 steering";
136
137 case MLX4_STEERING_MODE_B0:
138 return "B0 steering";
139
140 case MLX4_STEERING_MODE_DEVICE_MANAGED:
141 return "Device managed flow steering";
142
143 default:
144 return "Unrecognize steering mode";
145 }
146 }
147
148 enum {
149 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
150 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
151 };
152
153 enum {
154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
185 };
186
187 enum {
188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
219 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
220 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
221 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
222 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
223 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
224 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
225 };
226
227 enum {
228 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
229 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
230 };
231
232 enum {
233 MLX4_VF_CAP_FLAG_RESET = 1 << 0
234 };
235
236 /* bit enums for an 8-bit flags field indicating special use
237 * QPs which require special handling in qp_reserve_range.
238 * Currently, this only includes QPs used by the ETH interface,
239 * where we expect to use blueflame. These QPs must not have
240 * bits 6 and 7 set in their qp number.
241 *
242 * This enum may use only bits 0..7.
243 */
244 enum {
245 MLX4_RESERVE_A0_QP = 1 << 6,
246 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
247 };
248
249 enum {
250 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
251 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
252 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
253 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
254 };
255
256 enum {
257 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
258 };
259
260 enum {
261 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
262 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
263 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
264 };
265
266
267 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
268
269 enum {
270 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
271 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
272 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
273 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
274 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
275 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
276 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
277 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
278 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
279 };
280
281 enum {
282 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
283 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
284 };
285
286 enum mlx4_event {
287 MLX4_EVENT_TYPE_COMP = 0x00,
288 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
289 MLX4_EVENT_TYPE_COMM_EST = 0x02,
290 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
291 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
292 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
293 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
294 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
295 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
296 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
297 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
298 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
299 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
300 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
301 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
302 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
303 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
304 MLX4_EVENT_TYPE_CMD = 0x0a,
305 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
306 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
307 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
308 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
309 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
310 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
311 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
312 MLX4_EVENT_TYPE_NONE = 0xff,
313 };
314
315 enum {
316 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
317 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
318 };
319
320 enum {
321 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
322 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
323 };
324
325 enum {
326 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
327 };
328
329 enum slave_port_state {
330 SLAVE_PORT_DOWN = 0,
331 SLAVE_PENDING_UP,
332 SLAVE_PORT_UP,
333 };
334
335 enum slave_port_gen_event {
336 SLAVE_PORT_GEN_EVENT_DOWN = 0,
337 SLAVE_PORT_GEN_EVENT_UP,
338 SLAVE_PORT_GEN_EVENT_NONE,
339 };
340
341 enum slave_port_state_event {
342 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
343 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
344 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
345 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
346 };
347
348 enum {
349 MLX4_PERM_LOCAL_READ = 1 << 10,
350 MLX4_PERM_LOCAL_WRITE = 1 << 11,
351 MLX4_PERM_REMOTE_READ = 1 << 12,
352 MLX4_PERM_REMOTE_WRITE = 1 << 13,
353 MLX4_PERM_ATOMIC = 1 << 14,
354 MLX4_PERM_BIND_MW = 1 << 15,
355 MLX4_PERM_MASK = 0xFC00
356 };
357
358 enum {
359 MLX4_OPCODE_NOP = 0x00,
360 MLX4_OPCODE_SEND_INVAL = 0x01,
361 MLX4_OPCODE_RDMA_WRITE = 0x08,
362 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
363 MLX4_OPCODE_SEND = 0x0a,
364 MLX4_OPCODE_SEND_IMM = 0x0b,
365 MLX4_OPCODE_LSO = 0x0e,
366 MLX4_OPCODE_RDMA_READ = 0x10,
367 MLX4_OPCODE_ATOMIC_CS = 0x11,
368 MLX4_OPCODE_ATOMIC_FA = 0x12,
369 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
370 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
371 MLX4_OPCODE_BIND_MW = 0x18,
372 MLX4_OPCODE_FMR = 0x19,
373 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
374 MLX4_OPCODE_CONFIG_CMD = 0x1f,
375
376 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
377 MLX4_RECV_OPCODE_SEND = 0x01,
378 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
379 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
380
381 MLX4_CQE_OPCODE_ERROR = 0x1e,
382 MLX4_CQE_OPCODE_RESIZE = 0x16,
383 };
384
385 enum {
386 MLX4_STAT_RATE_OFFSET = 5
387 };
388
389 enum mlx4_protocol {
390 MLX4_PROT_IB_IPV6 = 0,
391 MLX4_PROT_ETH,
392 MLX4_PROT_IB_IPV4,
393 MLX4_PROT_FCOE
394 };
395
396 enum {
397 MLX4_MTT_FLAG_PRESENT = 1
398 };
399
400 enum mlx4_qp_region {
401 MLX4_QP_REGION_FW = 0,
402 MLX4_QP_REGION_RSS_RAW_ETH,
403 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
404 MLX4_QP_REGION_ETH_ADDR,
405 MLX4_QP_REGION_FC_ADDR,
406 MLX4_QP_REGION_FC_EXCH,
407 MLX4_NUM_QP_REGION
408 };
409
410 enum mlx4_port_type {
411 MLX4_PORT_TYPE_NONE = 0,
412 MLX4_PORT_TYPE_IB = 1,
413 MLX4_PORT_TYPE_ETH = 2,
414 MLX4_PORT_TYPE_AUTO = 3
415 };
416
417 enum mlx4_special_vlan_idx {
418 MLX4_NO_VLAN_IDX = 0,
419 MLX4_VLAN_MISS_IDX,
420 MLX4_VLAN_REGULAR
421 };
422
423 enum mlx4_steer_type {
424 MLX4_MC_STEER = 0,
425 MLX4_UC_STEER,
426 MLX4_NUM_STEERS
427 };
428
429 enum {
430 MLX4_NUM_FEXCH = 64 * 1024,
431 };
432
433 enum {
434 MLX4_MAX_FAST_REG_PAGES = 511,
435 };
436
437 enum {
438 /*
439 * Max wqe size for rdma read is 512 bytes, so this
440 * limits our max_sge_rd as the wqe needs to fit:
441 * - ctrl segment (16 bytes)
442 * - rdma segment (16 bytes)
443 * - scatter elements (16 bytes each)
444 */
445 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
446 };
447
448 enum {
449 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
450 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
451 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
452 };
453
454 /* Port mgmt change event handling */
455 enum {
456 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
457 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
458 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
459 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
460 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
461 };
462
463 enum {
464 MLX4_DEVICE_STATE_UP = 1 << 0,
465 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
466 };
467
468 enum {
469 MLX4_INTERFACE_STATE_UP = 1 << 0,
470 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
471 MLX4_INTERFACE_STATE_SHUTDOWN = 1 << 2,
472 };
473
474 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
475 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
476
477 enum mlx4_module_id {
478 MLX4_MODULE_ID_SFP = 0x3,
479 MLX4_MODULE_ID_QSFP = 0xC,
480 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
481 MLX4_MODULE_ID_QSFP28 = 0x11,
482 };
483
484 enum { /* rl */
485 MLX4_QP_RATE_LIMIT_NONE = 0,
486 MLX4_QP_RATE_LIMIT_KBS = 1,
487 MLX4_QP_RATE_LIMIT_MBS = 2,
488 MLX4_QP_RATE_LIMIT_GBS = 3
489 };
490
491 struct mlx4_rate_limit_caps {
492 u16 num_rates; /* Number of different rates */
493 u8 min_unit;
494 u16 min_val;
495 u8 max_unit;
496 u16 max_val;
497 };
498
499 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
500 {
501 return (major << 32) | (minor << 16) | subminor;
502 }
503
504 struct mlx4_phys_caps {
505 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
506 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
507 u32 num_phys_eqs;
508 u32 base_sqpn;
509 u32 base_proxy_sqpn;
510 u32 base_tunnel_sqpn;
511 };
512
513 struct mlx4_caps {
514 u64 fw_ver;
515 u32 function;
516 int num_ports;
517 int vl_cap[MLX4_MAX_PORTS + 1];
518 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
519 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
520 u64 def_mac[MLX4_MAX_PORTS + 1];
521 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
522 int gid_table_len[MLX4_MAX_PORTS + 1];
523 int pkey_table_len[MLX4_MAX_PORTS + 1];
524 int trans_type[MLX4_MAX_PORTS + 1];
525 int vendor_oui[MLX4_MAX_PORTS + 1];
526 int wavelength[MLX4_MAX_PORTS + 1];
527 u64 trans_code[MLX4_MAX_PORTS + 1];
528 int local_ca_ack_delay;
529 int num_uars;
530 u32 uar_page_size;
531 int bf_reg_size;
532 int bf_regs_per_page;
533 int max_sq_sg;
534 int max_rq_sg;
535 int num_qps;
536 int max_wqes;
537 int max_sq_desc_sz;
538 int max_rq_desc_sz;
539 int max_qp_init_rdma;
540 int max_qp_dest_rdma;
541 int max_tc_eth;
542 u32 *qp0_qkey;
543 u32 *qp0_proxy;
544 u32 *qp1_proxy;
545 u32 *qp0_tunnel;
546 u32 *qp1_tunnel;
547 int num_srqs;
548 int max_srq_wqes;
549 int max_srq_sge;
550 int reserved_srqs;
551 int num_cqs;
552 int max_cqes;
553 int reserved_cqs;
554 int num_sys_eqs;
555 int num_eqs;
556 int reserved_eqs;
557 int num_comp_vectors;
558 int num_mpts;
559 int max_fmr_maps;
560 int num_mtts;
561 int fmr_reserved_mtts;
562 int reserved_mtts;
563 int reserved_mrws;
564 int reserved_uars;
565 int num_mgms;
566 int num_amgms;
567 int reserved_mcgs;
568 int num_qp_per_mgm;
569 int steering_mode;
570 int dmfs_high_steer_mode;
571 int fs_log_max_ucast_qp_range_size;
572 int num_pds;
573 int reserved_pds;
574 int max_xrcds;
575 int reserved_xrcds;
576 int mtt_entry_sz;
577 u32 max_msg_sz;
578 u32 page_size_cap;
579 u64 flags;
580 u64 flags2;
581 u32 bmme_flags;
582 u32 reserved_lkey;
583 u16 stat_rate_support;
584 u8 port_width_cap[MLX4_MAX_PORTS + 1];
585 int max_gso_sz;
586 int max_rss_tbl_sz;
587 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
588 int reserved_qps;
589 int reserved_qps_base[MLX4_NUM_QP_REGION];
590 int log_num_macs;
591 int log_num_vlans;
592 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
593 u8 supported_type[MLX4_MAX_PORTS + 1];
594 u8 suggested_type[MLX4_MAX_PORTS + 1];
595 u8 default_sense[MLX4_MAX_PORTS + 1];
596 u32 port_mask[MLX4_MAX_PORTS + 1];
597 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
598 u32 max_counters;
599 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
600 u16 sqp_demux;
601 u32 eqe_size;
602 u32 cqe_size;
603 u8 eqe_factor;
604 u32 userspace_caps; /* userspace must be aware of these */
605 u32 function_caps; /* VFs must be aware of these */
606 u16 hca_core_clock;
607 u64 phys_port_id[MLX4_MAX_PORTS + 1];
608 int tunnel_offload_mode;
609 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
610 u8 phv_bit[MLX4_MAX_PORTS + 1];
611 u8 alloc_res_qp_mask;
612 u32 dmfs_high_rate_qpn_base;
613 u32 dmfs_high_rate_qpn_range;
614 u32 vf_caps;
615 struct mlx4_rate_limit_caps rl_caps;
616 };
617
618 struct mlx4_buf_list {
619 void *buf;
620 dma_addr_t map;
621 };
622
623 struct mlx4_buf {
624 struct mlx4_buf_list direct;
625 struct mlx4_buf_list *page_list;
626 int nbufs;
627 int npages;
628 int page_shift;
629 };
630
631 struct mlx4_mtt {
632 u32 offset;
633 int order;
634 int page_shift;
635 };
636
637 enum {
638 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
639 };
640
641 struct mlx4_db_pgdir {
642 struct list_head list;
643 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
644 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
645 unsigned long *bits[2];
646 __be32 *db_page;
647 dma_addr_t db_dma;
648 };
649
650 struct mlx4_ib_user_db_page;
651
652 struct mlx4_db {
653 __be32 *db;
654 union {
655 struct mlx4_db_pgdir *pgdir;
656 struct mlx4_ib_user_db_page *user_page;
657 } u;
658 dma_addr_t dma;
659 int index;
660 int order;
661 };
662
663 struct mlx4_hwq_resources {
664 struct mlx4_db db;
665 struct mlx4_mtt mtt;
666 struct mlx4_buf buf;
667 };
668
669 struct mlx4_mr {
670 struct mlx4_mtt mtt;
671 u64 iova;
672 u64 size;
673 u32 key;
674 u32 pd;
675 u32 access;
676 int enabled;
677 };
678
679 enum mlx4_mw_type {
680 MLX4_MW_TYPE_1 = 1,
681 MLX4_MW_TYPE_2 = 2,
682 };
683
684 struct mlx4_mw {
685 u32 key;
686 u32 pd;
687 enum mlx4_mw_type type;
688 int enabled;
689 };
690
691 struct mlx4_fmr {
692 struct mlx4_mr mr;
693 struct mlx4_mpt_entry *mpt;
694 __be64 *mtts;
695 dma_addr_t dma_handle;
696 int max_pages;
697 int max_maps;
698 int maps;
699 u8 page_shift;
700 };
701
702 struct mlx4_uar {
703 unsigned long pfn;
704 int index;
705 struct list_head bf_list;
706 unsigned free_bf_bmap;
707 void __iomem *map;
708 void __iomem *bf_map;
709 };
710
711 struct mlx4_bf {
712 unsigned int offset;
713 int buf_size;
714 struct mlx4_uar *uar;
715 void __iomem *reg;
716 };
717
718 struct mlx4_cq {
719 void (*comp) (struct mlx4_cq *);
720 void (*event) (struct mlx4_cq *, enum mlx4_event);
721
722 struct mlx4_uar *uar;
723
724 u32 cons_index;
725
726 u16 irq;
727 __be32 *set_ci_db;
728 __be32 *arm_db;
729 int arm_sn;
730
731 int cqn;
732 unsigned vector;
733
734 atomic_t refcount;
735 struct completion free;
736 struct {
737 struct list_head list;
738 void (*comp)(struct mlx4_cq *);
739 void *priv;
740 } tasklet_ctx;
741 int reset_notify_added;
742 struct list_head reset_notify;
743 };
744
745 struct mlx4_qp {
746 void (*event) (struct mlx4_qp *, enum mlx4_event);
747
748 int qpn;
749
750 atomic_t refcount;
751 struct completion free;
752 };
753
754 struct mlx4_srq {
755 void (*event) (struct mlx4_srq *, enum mlx4_event);
756
757 int srqn;
758 int max;
759 int max_gs;
760 int wqe_shift;
761
762 atomic_t refcount;
763 struct completion free;
764 };
765
766 struct mlx4_av {
767 __be32 port_pd;
768 u8 reserved1;
769 u8 g_slid;
770 __be16 dlid;
771 u8 reserved2;
772 u8 gid_index;
773 u8 stat_rate;
774 u8 hop_limit;
775 __be32 sl_tclass_flowlabel;
776 u8 dgid[16];
777 };
778
779 struct mlx4_eth_av {
780 __be32 port_pd;
781 u8 reserved1;
782 u8 smac_idx;
783 u16 reserved2;
784 u8 reserved3;
785 u8 gid_index;
786 u8 stat_rate;
787 u8 hop_limit;
788 __be32 sl_tclass_flowlabel;
789 u8 dgid[16];
790 u8 s_mac[6];
791 u8 reserved4[2];
792 __be16 vlan;
793 u8 mac[ETH_ALEN];
794 };
795
796 union mlx4_ext_av {
797 struct mlx4_av ib;
798 struct mlx4_eth_av eth;
799 };
800
801 /* Counters should be saturate once they reach their maximum value */
802 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
803 if ((value) > U32_MAX) \
804 counter = cpu_to_be32(U32_MAX); \
805 else \
806 counter = cpu_to_be32(value); \
807 } while (0)
808
809 struct mlx4_counter {
810 u8 reserved1[3];
811 u8 counter_mode;
812 __be32 num_ifc;
813 u32 reserved2[2];
814 __be64 rx_frames;
815 __be64 rx_bytes;
816 __be64 tx_frames;
817 __be64 tx_bytes;
818 };
819
820 struct mlx4_quotas {
821 int qp;
822 int cq;
823 int srq;
824 int mpt;
825 int mtt;
826 int counter;
827 int xrcd;
828 };
829
830 struct mlx4_vf_dev {
831 u8 min_port;
832 u8 n_ports;
833 };
834
835 enum mlx4_pci_status {
836 MLX4_PCI_STATUS_DISABLED,
837 MLX4_PCI_STATUS_ENABLED,
838 };
839
840 struct mlx4_dev_persistent {
841 struct pci_dev *pdev;
842 struct mlx4_dev *dev;
843 int nvfs[MLX4_MAX_PORTS + 1];
844 int num_vfs;
845 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
846 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
847 struct work_struct catas_work;
848 struct workqueue_struct *catas_wq;
849 struct mutex device_state_mutex; /* protect HW state */
850 u8 state;
851 struct mutex interface_state_mutex; /* protect SW state */
852 u8 interface_state;
853 struct mutex pci_status_mutex; /* sync pci state */
854 enum mlx4_pci_status pci_status;
855 };
856
857 struct mlx4_dev {
858 struct mlx4_dev_persistent *persist;
859 unsigned long flags;
860 unsigned long num_slaves;
861 struct mlx4_caps caps;
862 struct mlx4_phys_caps phys_caps;
863 struct mlx4_quotas quotas;
864 struct radix_tree_root qp_table_tree;
865 u8 rev_id;
866 u8 port_random_macs;
867 char board_id[MLX4_BOARD_ID_LEN];
868 int numa_node;
869 int oper_log_mgm_entry_size;
870 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
871 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
872 struct mlx4_vf_dev *dev_vfs;
873 u8 uar_page_shift;
874 };
875
876 struct mlx4_clock_params {
877 u64 offset;
878 u8 bar;
879 u8 size;
880 };
881
882 struct mlx4_eqe {
883 u8 reserved1;
884 u8 type;
885 u8 reserved2;
886 u8 subtype;
887 union {
888 u32 raw[6];
889 struct {
890 __be32 cqn;
891 } __packed comp;
892 struct {
893 u16 reserved1;
894 __be16 token;
895 u32 reserved2;
896 u8 reserved3[3];
897 u8 status;
898 __be64 out_param;
899 } __packed cmd;
900 struct {
901 __be32 qpn;
902 } __packed qp;
903 struct {
904 __be32 srqn;
905 } __packed srq;
906 struct {
907 __be32 cqn;
908 u32 reserved1;
909 u8 reserved2[3];
910 u8 syndrome;
911 } __packed cq_err;
912 struct {
913 u32 reserved1[2];
914 __be32 port;
915 } __packed port_change;
916 struct {
917 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
918 u32 reserved;
919 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
920 } __packed comm_channel_arm;
921 struct {
922 u8 port;
923 u8 reserved[3];
924 __be64 mac;
925 } __packed mac_update;
926 struct {
927 __be32 slave_id;
928 } __packed flr_event;
929 struct {
930 __be16 current_temperature;
931 __be16 warning_threshold;
932 } __packed warming;
933 struct {
934 u8 reserved[3];
935 u8 port;
936 union {
937 struct {
938 __be16 mstr_sm_lid;
939 __be16 port_lid;
940 __be32 changed_attr;
941 u8 reserved[3];
942 u8 mstr_sm_sl;
943 __be64 gid_prefix;
944 } __packed port_info;
945 struct {
946 __be32 block_ptr;
947 __be32 tbl_entries_mask;
948 } __packed tbl_change_info;
949 } params;
950 } __packed port_mgmt_change;
951 struct {
952 u8 reserved[3];
953 u8 port;
954 u32 reserved1[5];
955 } __packed bad_cable;
956 } event;
957 u8 slave_id;
958 u8 reserved3[2];
959 u8 owner;
960 } __packed;
961
962 struct mlx4_init_port_param {
963 int set_guid0;
964 int set_node_guid;
965 int set_si_guid;
966 u16 mtu;
967 int port_width_cap;
968 u16 vl_cap;
969 u16 max_gid;
970 u16 max_pkey;
971 u64 guid0;
972 u64 node_guid;
973 u64 si_guid;
974 };
975
976 #define MAD_IFC_DATA_SZ 192
977 /* MAD IFC Mailbox */
978 struct mlx4_mad_ifc {
979 u8 base_version;
980 u8 mgmt_class;
981 u8 class_version;
982 u8 method;
983 __be16 status;
984 __be16 class_specific;
985 __be64 tid;
986 __be16 attr_id;
987 __be16 resv;
988 __be32 attr_mod;
989 __be64 mkey;
990 __be16 dr_slid;
991 __be16 dr_dlid;
992 u8 reserved[28];
993 u8 data[MAD_IFC_DATA_SZ];
994 } __packed;
995
996 #define mlx4_foreach_port(port, dev, type) \
997 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
998 if ((type) == (dev)->caps.port_mask[(port)])
999
1000 #define mlx4_foreach_ib_transport_port(port, dev) \
1001 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1002 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1003 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \
1004 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2))
1005
1006 #define MLX4_INVALID_SLAVE_ID 0xFF
1007 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1008
1009 void handle_port_mgmt_change_event(struct work_struct *work);
1010
1011 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1012 {
1013 return dev->caps.function;
1014 }
1015
1016 static inline int mlx4_is_master(struct mlx4_dev *dev)
1017 {
1018 return dev->flags & MLX4_FLAG_MASTER;
1019 }
1020
1021 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1022 {
1023 return dev->phys_caps.base_sqpn + 8 +
1024 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1025 }
1026
1027 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1028 {
1029 return (qpn < dev->phys_caps.base_sqpn + 8 +
1030 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1031 qpn >= dev->phys_caps.base_sqpn) ||
1032 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1033 }
1034
1035 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1036 {
1037 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1038
1039 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1040 return 1;
1041
1042 return 0;
1043 }
1044
1045 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1046 {
1047 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1048 }
1049
1050 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1051 {
1052 return dev->flags & MLX4_FLAG_SLAVE;
1053 }
1054
1055 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1056 {
1057 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1058 }
1059
1060 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1061 struct mlx4_buf *buf, gfp_t gfp);
1062 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1063 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1064 {
1065 if (buf->nbufs == 1)
1066 return buf->direct.buf + offset;
1067 else
1068 return buf->page_list[offset >> PAGE_SHIFT].buf +
1069 (offset & (PAGE_SIZE - 1));
1070 }
1071
1072 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1073 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1074 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1075 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1076
1077 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1078 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1079 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1080 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1081
1082 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1083 struct mlx4_mtt *mtt);
1084 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1085 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1086
1087 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1088 int npages, int page_shift, struct mlx4_mr *mr);
1089 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1090 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1091 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1092 struct mlx4_mw *mw);
1093 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1094 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1095 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1096 int start_index, int npages, u64 *page_list);
1097 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1098 struct mlx4_buf *buf, gfp_t gfp);
1099
1100 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1101 gfp_t gfp);
1102 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1103
1104 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1105 int size);
1106 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1107 int size);
1108
1109 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1110 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1111 unsigned vector, int collapsed, int timestamp_en);
1112 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1113 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1114 int *base, u8 flags);
1115 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1116
1117 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1118 gfp_t gfp);
1119 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1120
1121 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1122 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1123 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1124 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1125 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1126
1127 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1128 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1129
1130 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1131 int block_mcast_loopback, enum mlx4_protocol prot);
1132 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1133 enum mlx4_protocol prot);
1134 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1135 u8 port, int block_mcast_loopback,
1136 enum mlx4_protocol protocol, u64 *reg_id);
1137 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1138 enum mlx4_protocol protocol, u64 reg_id);
1139
1140 enum {
1141 MLX4_DOMAIN_UVERBS = 0x1000,
1142 MLX4_DOMAIN_ETHTOOL = 0x2000,
1143 MLX4_DOMAIN_RFS = 0x3000,
1144 MLX4_DOMAIN_NIC = 0x5000,
1145 };
1146
1147 enum mlx4_net_trans_rule_id {
1148 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1149 MLX4_NET_TRANS_RULE_ID_IB,
1150 MLX4_NET_TRANS_RULE_ID_IPV6,
1151 MLX4_NET_TRANS_RULE_ID_IPV4,
1152 MLX4_NET_TRANS_RULE_ID_TCP,
1153 MLX4_NET_TRANS_RULE_ID_UDP,
1154 MLX4_NET_TRANS_RULE_ID_VXLAN,
1155 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1156 };
1157
1158 extern const u16 __sw_id_hw[];
1159
1160 static inline int map_hw_to_sw_id(u16 header_id)
1161 {
1162
1163 int i;
1164 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1165 if (header_id == __sw_id_hw[i])
1166 return i;
1167 }
1168 return -EINVAL;
1169 }
1170
1171 enum mlx4_net_trans_promisc_mode {
1172 MLX4_FS_REGULAR = 1,
1173 MLX4_FS_ALL_DEFAULT,
1174 MLX4_FS_MC_DEFAULT,
1175 MLX4_FS_MIRROR_RX_PORT,
1176 MLX4_FS_MIRROR_SX_PORT,
1177 MLX4_FS_UC_SNIFFER,
1178 MLX4_FS_MC_SNIFFER,
1179 MLX4_FS_MODE_NUM, /* should be last */
1180 };
1181
1182 struct mlx4_spec_eth {
1183 u8 dst_mac[ETH_ALEN];
1184 u8 dst_mac_msk[ETH_ALEN];
1185 u8 src_mac[ETH_ALEN];
1186 u8 src_mac_msk[ETH_ALEN];
1187 u8 ether_type_enable;
1188 __be16 ether_type;
1189 __be16 vlan_id_msk;
1190 __be16 vlan_id;
1191 };
1192
1193 struct mlx4_spec_tcp_udp {
1194 __be16 dst_port;
1195 __be16 dst_port_msk;
1196 __be16 src_port;
1197 __be16 src_port_msk;
1198 };
1199
1200 struct mlx4_spec_ipv4 {
1201 __be32 dst_ip;
1202 __be32 dst_ip_msk;
1203 __be32 src_ip;
1204 __be32 src_ip_msk;
1205 };
1206
1207 struct mlx4_spec_ib {
1208 __be32 l3_qpn;
1209 __be32 qpn_msk;
1210 u8 dst_gid[16];
1211 u8 dst_gid_msk[16];
1212 };
1213
1214 struct mlx4_spec_vxlan {
1215 __be32 vni;
1216 __be32 vni_mask;
1217
1218 };
1219
1220 struct mlx4_spec_list {
1221 struct list_head list;
1222 enum mlx4_net_trans_rule_id id;
1223 union {
1224 struct mlx4_spec_eth eth;
1225 struct mlx4_spec_ib ib;
1226 struct mlx4_spec_ipv4 ipv4;
1227 struct mlx4_spec_tcp_udp tcp_udp;
1228 struct mlx4_spec_vxlan vxlan;
1229 };
1230 };
1231
1232 enum mlx4_net_trans_hw_rule_queue {
1233 MLX4_NET_TRANS_Q_FIFO,
1234 MLX4_NET_TRANS_Q_LIFO,
1235 };
1236
1237 struct mlx4_net_trans_rule {
1238 struct list_head list;
1239 enum mlx4_net_trans_hw_rule_queue queue_mode;
1240 bool exclusive;
1241 bool allow_loopback;
1242 enum mlx4_net_trans_promisc_mode promisc_mode;
1243 u8 port;
1244 u16 priority;
1245 u32 qpn;
1246 };
1247
1248 struct mlx4_net_trans_rule_hw_ctrl {
1249 __be16 prio;
1250 u8 type;
1251 u8 flags;
1252 u8 rsvd1;
1253 u8 funcid;
1254 u8 vep;
1255 u8 port;
1256 __be32 qpn;
1257 __be32 rsvd2;
1258 };
1259
1260 struct mlx4_net_trans_rule_hw_ib {
1261 u8 size;
1262 u8 rsvd1;
1263 __be16 id;
1264 u32 rsvd2;
1265 __be32 l3_qpn;
1266 __be32 qpn_mask;
1267 u8 dst_gid[16];
1268 u8 dst_gid_msk[16];
1269 } __packed;
1270
1271 struct mlx4_net_trans_rule_hw_eth {
1272 u8 size;
1273 u8 rsvd;
1274 __be16 id;
1275 u8 rsvd1[6];
1276 u8 dst_mac[6];
1277 u16 rsvd2;
1278 u8 dst_mac_msk[6];
1279 u16 rsvd3;
1280 u8 src_mac[6];
1281 u16 rsvd4;
1282 u8 src_mac_msk[6];
1283 u8 rsvd5;
1284 u8 ether_type_enable;
1285 __be16 ether_type;
1286 __be16 vlan_tag_msk;
1287 __be16 vlan_tag;
1288 } __packed;
1289
1290 struct mlx4_net_trans_rule_hw_tcp_udp {
1291 u8 size;
1292 u8 rsvd;
1293 __be16 id;
1294 __be16 rsvd1[3];
1295 __be16 dst_port;
1296 __be16 rsvd2;
1297 __be16 dst_port_msk;
1298 __be16 rsvd3;
1299 __be16 src_port;
1300 __be16 rsvd4;
1301 __be16 src_port_msk;
1302 } __packed;
1303
1304 struct mlx4_net_trans_rule_hw_ipv4 {
1305 u8 size;
1306 u8 rsvd;
1307 __be16 id;
1308 __be32 rsvd1;
1309 __be32 dst_ip;
1310 __be32 dst_ip_msk;
1311 __be32 src_ip;
1312 __be32 src_ip_msk;
1313 } __packed;
1314
1315 struct mlx4_net_trans_rule_hw_vxlan {
1316 u8 size;
1317 u8 rsvd;
1318 __be16 id;
1319 __be32 rsvd1;
1320 __be32 vni;
1321 __be32 vni_mask;
1322 } __packed;
1323
1324 struct _rule_hw {
1325 union {
1326 struct {
1327 u8 size;
1328 u8 rsvd;
1329 __be16 id;
1330 };
1331 struct mlx4_net_trans_rule_hw_eth eth;
1332 struct mlx4_net_trans_rule_hw_ib ib;
1333 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1334 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1335 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1336 };
1337 };
1338
1339 enum {
1340 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1341 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1342 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1343 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1344 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1345 };
1346
1347 enum {
1348 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1349 };
1350
1351 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1352 enum mlx4_net_trans_promisc_mode mode);
1353 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1354 enum mlx4_net_trans_promisc_mode mode);
1355 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1356 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1357 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1358 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1359 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1360
1361 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1362 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1363 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1364 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1365 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1366 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1367 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1368 u8 promisc);
1369 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1370 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1371 u8 ignore_fcs_value);
1372 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1373 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1374 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1375 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1376 bool *vlan_offload_disabled);
1377 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1378 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1379 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1380 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1381
1382 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1383 int npages, u64 iova, u32 *lkey, u32 *rkey);
1384 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1385 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1386 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1387 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1388 u32 *lkey, u32 *rkey);
1389 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1390 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1391 int mlx4_test_interrupts(struct mlx4_dev *dev);
1392 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1393 const u32 offset[], u32 value[],
1394 size_t array_len, u8 port);
1395 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1396 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1397 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1398 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1399 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1400
1401 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1402 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1403
1404 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1405 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1406 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1407
1408 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1409 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1410 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1411
1412 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1413 int port);
1414 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1415 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1416 int mlx4_flow_attach(struct mlx4_dev *dev,
1417 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1418 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1419 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1420 enum mlx4_net_trans_promisc_mode flow_type);
1421 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1422 enum mlx4_net_trans_rule_id id);
1423 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1424
1425 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1426 int port, int qpn, u16 prio, u64 *reg_id);
1427
1428 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1429 int i, int val);
1430
1431 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1432
1433 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1434 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1435 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1436 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1437 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1438 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1439 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1440
1441 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1442 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1443
1444 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1445 int *slave_id);
1446 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1447 u8 *gid);
1448
1449 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1450 u32 max_range_qpn);
1451
1452 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1453
1454 struct mlx4_active_ports {
1455 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1456 };
1457 /* Returns a bitmap of the physical ports which are assigned to slave */
1458 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1459
1460 /* Returns the physical port that represents the virtual port of the slave, */
1461 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1462 /* mapping is returned. */
1463 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1464
1465 struct mlx4_slaves_pport {
1466 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1467 };
1468 /* Returns a bitmap of all slaves that are assigned to port. */
1469 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1470 int port);
1471
1472 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1473 /* the ports that are set in crit_ports. */
1474 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1475 struct mlx4_dev *dev,
1476 const struct mlx4_active_ports *crit_ports);
1477
1478 /* Returns the slave's virtual port that represents the physical port. */
1479 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1480
1481 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1482
1483 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1484 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1485 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1486 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1487 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1488 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1489 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1490 int enable);
1491 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1492 struct mlx4_mpt_entry ***mpt_entry);
1493 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1494 struct mlx4_mpt_entry **mpt_entry);
1495 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1496 u32 pdn);
1497 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1498 struct mlx4_mpt_entry *mpt_entry,
1499 u32 access);
1500 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1501 struct mlx4_mpt_entry **mpt_entry);
1502 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1503 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1504 u64 iova, u64 size, int npages,
1505 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1506
1507 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1508 u16 offset, u16 size, u8 *data);
1509 int mlx4_max_tc(struct mlx4_dev *dev);
1510
1511 /* Returns true if running in low memory profile (kdump kernel) */
1512 static inline bool mlx4_low_memory_profile(void)
1513 {
1514 return is_kdump_kernel();
1515 }
1516
1517 /* ACCESS REG commands */
1518 enum mlx4_access_reg_method {
1519 MLX4_ACCESS_REG_QUERY = 0x1,
1520 MLX4_ACCESS_REG_WRITE = 0x2,
1521 };
1522
1523 /* ACCESS PTYS Reg command */
1524 enum mlx4_ptys_proto {
1525 MLX4_PTYS_IB = 1<<0,
1526 MLX4_PTYS_EN = 1<<2,
1527 };
1528
1529 struct mlx4_ptys_reg {
1530 u8 resrvd1;
1531 u8 local_port;
1532 u8 resrvd2;
1533 u8 proto_mask;
1534 __be32 resrvd3[2];
1535 __be32 eth_proto_cap;
1536 __be16 ib_width_cap;
1537 __be16 ib_speed_cap;
1538 __be32 resrvd4;
1539 __be32 eth_proto_admin;
1540 __be16 ib_width_admin;
1541 __be16 ib_speed_admin;
1542 __be32 resrvd5;
1543 __be32 eth_proto_oper;
1544 __be16 ib_width_oper;
1545 __be16 ib_speed_oper;
1546 __be32 resrvd6;
1547 __be32 eth_proto_lp_adv;
1548 } __packed;
1549
1550 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1551 enum mlx4_access_reg_method method,
1552 struct mlx4_ptys_reg *ptys_reg);
1553
1554 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1555 struct mlx4_clock_params *params);
1556
1557 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1558 {
1559 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1560 }
1561
1562 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1563 {
1564 /* The first 128 UARs are used for EQ doorbells */
1565 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1566 }
1567 #endif /* MLX4_DEVICE_H */
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