2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
42 #include <linux/atomic.h>
44 #include <linux/clocksource.h>
46 #define MAX_MSIX_P_PORT 17
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
52 MLX4_FLAG_MSI_X
= 1 << 0,
53 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
54 MLX4_FLAG_MASTER
= 1 << 2,
55 MLX4_FLAG_SLAVE
= 1 << 3,
56 MLX4_FLAG_SRIOV
= 1 << 4,
57 MLX4_FLAG_OLD_REG_MAC
= 1 << 6,
61 MLX4_PORT_CAP_IS_SM
= 1 << 1,
62 MLX4_PORT_CAP_DEV_MGMT_SUP
= 1 << 19,
67 MLX4_MAX_PORT_PKEYS
= 128
70 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
71 * These qkeys must not be allowed for general use. This is a 64k range,
72 * and to test for violation, we use the mask (protect against future chg).
74 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
75 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
78 MLX4_BOARD_ID_LEN
= 64
85 MLX4_MAX_EQ_NUM
= 1024,
86 MLX4_MFUNC_EQ_NUM
= 4,
87 MLX4_MFUNC_MAX_EQES
= 8,
88 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
91 /* Driver supports 3 diffrent device methods to manage traffic steering:
92 * -device managed - High level API for ib and eth flow steering. FW is
93 * managing flow steering tables.
94 * - B0 steering mode - Common low level API for ib and (if supported) eth.
95 * - A0 steering mode - Limited low level API for eth. In case of IB,
99 MLX4_STEERING_MODE_A0
,
100 MLX4_STEERING_MODE_B0
,
101 MLX4_STEERING_MODE_DEVICE_MANAGED
104 static inline const char *mlx4_steering_mode_str(int steering_mode
)
106 switch (steering_mode
) {
107 case MLX4_STEERING_MODE_A0
:
108 return "A0 steering";
110 case MLX4_STEERING_MODE_B0
:
111 return "B0 steering";
113 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
114 return "Device managed flow steering";
117 return "Unrecognize steering mode";
122 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
123 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
124 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
125 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
126 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
127 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
128 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
129 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
130 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
131 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
132 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
133 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
134 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
135 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
136 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
137 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
138 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
139 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
140 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
141 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
142 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
143 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
144 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
145 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
146 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
147 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED
= 1LL << 53,
148 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55,
149 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
= 1LL << 59,
150 MLX4_DEV_CAP_FLAG_64B_EQE
= 1LL << 61,
151 MLX4_DEV_CAP_FLAG_64B_CQE
= 1LL << 62
155 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
156 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
157 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
158 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3,
159 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
= 1LL << 4,
160 MLX4_DEV_CAP_FLAG2_TS
= 1LL << 5,
161 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
= 1LL << 6,
162 MLX4_DEV_CAP_FLAG2_FSM
= 1LL << 7,
163 MLX4_DEV_CAP_FLAG2_UPDATE_QP
= 1LL << 8
167 MLX4_DEV_CAP_64B_EQE_ENABLED
= 1LL << 0,
168 MLX4_DEV_CAP_64B_CQE_ENABLED
= 1LL << 1
172 MLX4_USER_DEV_CAP_64B_CQE
= 1L << 0
176 MLX4_FUNC_CAP_64B_EQE_CQE
= 1L << 0
180 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
183 MLX4_BMME_FLAG_WIN_TYPE_2B
= 1 << 1,
184 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
185 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
186 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
187 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
188 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
192 MLX4_EVENT_TYPE_COMP
= 0x00,
193 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
194 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
195 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
196 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
197 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
198 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
199 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
200 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
201 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
202 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
203 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
204 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
205 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
206 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
207 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
208 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
209 MLX4_EVENT_TYPE_CMD
= 0x0a,
210 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
211 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
212 MLX4_EVENT_TYPE_OP_REQUIRED
= 0x1a,
213 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
214 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
215 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT
= 0x1d,
216 MLX4_EVENT_TYPE_NONE
= 0xff,
220 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
221 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
225 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
228 enum slave_port_state
{
234 enum slave_port_gen_event
{
235 SLAVE_PORT_GEN_EVENT_DOWN
= 0,
236 SLAVE_PORT_GEN_EVENT_UP
,
237 SLAVE_PORT_GEN_EVENT_NONE
,
240 enum slave_port_state_event
{
241 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN
,
242 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
,
243 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID
,
244 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
,
248 MLX4_PERM_LOCAL_READ
= 1 << 10,
249 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
250 MLX4_PERM_REMOTE_READ
= 1 << 12,
251 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
252 MLX4_PERM_ATOMIC
= 1 << 14,
253 MLX4_PERM_BIND_MW
= 1 << 15,
257 MLX4_OPCODE_NOP
= 0x00,
258 MLX4_OPCODE_SEND_INVAL
= 0x01,
259 MLX4_OPCODE_RDMA_WRITE
= 0x08,
260 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
261 MLX4_OPCODE_SEND
= 0x0a,
262 MLX4_OPCODE_SEND_IMM
= 0x0b,
263 MLX4_OPCODE_LSO
= 0x0e,
264 MLX4_OPCODE_RDMA_READ
= 0x10,
265 MLX4_OPCODE_ATOMIC_CS
= 0x11,
266 MLX4_OPCODE_ATOMIC_FA
= 0x12,
267 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
268 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
269 MLX4_OPCODE_BIND_MW
= 0x18,
270 MLX4_OPCODE_FMR
= 0x19,
271 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
272 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
274 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
275 MLX4_RECV_OPCODE_SEND
= 0x01,
276 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
277 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
279 MLX4_CQE_OPCODE_ERROR
= 0x1e,
280 MLX4_CQE_OPCODE_RESIZE
= 0x16,
284 MLX4_STAT_RATE_OFFSET
= 5
288 MLX4_PROT_IB_IPV6
= 0,
295 MLX4_MTT_FLAG_PRESENT
= 1
298 enum mlx4_qp_region
{
299 MLX4_QP_REGION_FW
= 0,
300 MLX4_QP_REGION_ETH_ADDR
,
301 MLX4_QP_REGION_FC_ADDR
,
302 MLX4_QP_REGION_FC_EXCH
,
306 enum mlx4_port_type
{
307 MLX4_PORT_TYPE_NONE
= 0,
308 MLX4_PORT_TYPE_IB
= 1,
309 MLX4_PORT_TYPE_ETH
= 2,
310 MLX4_PORT_TYPE_AUTO
= 3
313 enum mlx4_special_vlan_idx
{
314 MLX4_NO_VLAN_IDX
= 0,
319 enum mlx4_steer_type
{
326 MLX4_NUM_FEXCH
= 64 * 1024,
330 MLX4_MAX_FAST_REG_PAGES
= 511,
334 MLX4_DEV_PMC_SUBTYPE_GUID_INFO
= 0x14,
335 MLX4_DEV_PMC_SUBTYPE_PORT_INFO
= 0x15,
336 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE
= 0x16,
339 /* Port mgmt change event handling */
341 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK
= 1 << 0,
342 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK
= 1 << 1,
343 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK
= 1 << 2,
344 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK
= 1 << 3,
345 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK
= 1 << 4,
348 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
349 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
351 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
353 return (major
<< 32) | (minor
<< 16) | subminor
;
356 struct mlx4_phys_caps
{
357 u32 gid_phys_table_len
[MLX4_MAX_PORTS
+ 1];
358 u32 pkey_phys_table_len
[MLX4_MAX_PORTS
+ 1];
362 u32 base_tunnel_sqpn
;
369 int vl_cap
[MLX4_MAX_PORTS
+ 1];
370 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
371 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
372 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
373 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
374 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
375 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
376 int trans_type
[MLX4_MAX_PORTS
+ 1];
377 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
378 int wavelength
[MLX4_MAX_PORTS
+ 1];
379 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
380 int local_ca_ack_delay
;
384 int bf_regs_per_page
;
391 int max_qp_init_rdma
;
392 int max_qp_dest_rdma
;
406 int num_comp_vectors
;
411 int fmr_reserved_mtts
;
420 int fs_log_max_ucast_qp_range_size
;
432 u16 stat_rate_support
;
433 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
436 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
438 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
442 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
443 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
444 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
445 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
446 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
447 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
449 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
454 u32 userspace_caps
; /* userspace must be aware of these */
455 u32 function_caps
; /* VFs must be aware of these */
459 struct mlx4_buf_list
{
465 struct mlx4_buf_list direct
;
466 struct mlx4_buf_list
*page_list
;
479 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
482 struct mlx4_db_pgdir
{
483 struct list_head list
;
484 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
485 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
486 unsigned long *bits
[2];
491 struct mlx4_ib_user_db_page
;
496 struct mlx4_db_pgdir
*pgdir
;
497 struct mlx4_ib_user_db_page
*user_page
;
504 struct mlx4_hwq_resources
{
528 enum mlx4_mw_type type
;
534 struct mlx4_mpt_entry
*mpt
;
536 dma_addr_t dma_handle
;
546 struct list_head bf_list
;
547 unsigned free_bf_bmap
;
549 void __iomem
*bf_map
;
553 unsigned long offset
;
555 struct mlx4_uar
*uar
;
560 void (*comp
) (struct mlx4_cq
*);
561 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
563 struct mlx4_uar
*uar
;
575 struct completion free
;
579 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
584 struct completion free
;
588 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
596 struct completion free
;
608 __be32 sl_tclass_flowlabel
;
621 __be32 sl_tclass_flowlabel
;
630 struct mlx4_eth_av eth
;
633 struct mlx4_counter
{
655 struct pci_dev
*pdev
;
657 unsigned long num_slaves
;
658 struct mlx4_caps caps
;
659 struct mlx4_phys_caps phys_caps
;
660 struct mlx4_quotas quotas
;
661 struct radix_tree_root qp_table_tree
;
663 char board_id
[MLX4_BOARD_ID_LEN
];
665 int oper_log_mgm_entry_size
;
666 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
667 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
703 } __packed port_change
;
705 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
707 u32 bit_vec
[COMM_CHANNEL_BIT_ARRAY_SIZE
];
708 } __packed comm_channel_arm
;
713 } __packed mac_update
;
716 } __packed flr_event
;
718 __be16 current_temperature
;
719 __be16 warning_threshold
;
732 } __packed port_info
;
735 __be32 tbl_entries_mask
;
736 } __packed tbl_change_info
;
738 } __packed port_mgmt_change
;
745 struct mlx4_init_port_param
{
759 #define mlx4_foreach_port(port, dev, type) \
760 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
761 if ((type) == (dev)->caps.port_mask[(port)])
763 #define mlx4_foreach_non_ib_transport_port(port, dev) \
764 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
765 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
767 #define mlx4_foreach_ib_transport_port(port, dev) \
768 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
769 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
770 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
772 #define MLX4_INVALID_SLAVE_ID 0xFF
774 void handle_port_mgmt_change_event(struct work_struct
*work
);
776 static inline int mlx4_master_func_num(struct mlx4_dev
*dev
)
778 return dev
->caps
.function
;
781 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
783 return dev
->flags
& MLX4_FLAG_MASTER
;
786 static inline int mlx4_num_reserved_sqps(struct mlx4_dev
*dev
)
788 return dev
->phys_caps
.base_sqpn
+ 8 +
789 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
);
792 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
794 return (qpn
< dev
->phys_caps
.base_sqpn
+ 8 +
795 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
));
798 static inline int mlx4_is_guest_proxy(struct mlx4_dev
*dev
, int slave
, u32 qpn
)
800 int guest_proxy_base
= dev
->phys_caps
.base_proxy_sqpn
+ slave
* 8;
802 if (qpn
>= guest_proxy_base
&& qpn
< guest_proxy_base
+ 8)
808 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
810 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
813 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
815 return dev
->flags
& MLX4_FLAG_SLAVE
;
818 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
819 struct mlx4_buf
*buf
);
820 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
821 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
823 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
824 return buf
->direct
.buf
+ offset
;
826 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
827 (offset
& (PAGE_SIZE
- 1));
830 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
831 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
832 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
833 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
835 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
836 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
837 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
838 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
840 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
841 struct mlx4_mtt
*mtt
);
842 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
843 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
845 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
846 int npages
, int page_shift
, struct mlx4_mr
*mr
);
847 int mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
848 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
849 int mlx4_mw_alloc(struct mlx4_dev
*dev
, u32 pd
, enum mlx4_mw_type type
,
851 void mlx4_mw_free(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
852 int mlx4_mw_enable(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
853 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
854 int start_index
, int npages
, u64
*page_list
);
855 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
856 struct mlx4_buf
*buf
);
858 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
);
859 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
861 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
862 int size
, int max_direct
);
863 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
866 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
867 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
868 unsigned vector
, int collapsed
, int timestamp_en
);
869 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
871 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
872 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
874 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
);
875 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
877 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
878 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
879 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
880 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
881 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
883 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
884 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
886 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
887 int block_mcast_loopback
, enum mlx4_protocol prot
);
888 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
889 enum mlx4_protocol prot
);
890 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
891 u8 port
, int block_mcast_loopback
,
892 enum mlx4_protocol protocol
, u64
*reg_id
);
893 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
894 enum mlx4_protocol protocol
, u64 reg_id
);
897 MLX4_DOMAIN_UVERBS
= 0x1000,
898 MLX4_DOMAIN_ETHTOOL
= 0x2000,
899 MLX4_DOMAIN_RFS
= 0x3000,
900 MLX4_DOMAIN_NIC
= 0x5000,
903 enum mlx4_net_trans_rule_id
{
904 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
905 MLX4_NET_TRANS_RULE_ID_IB
,
906 MLX4_NET_TRANS_RULE_ID_IPV6
,
907 MLX4_NET_TRANS_RULE_ID_IPV4
,
908 MLX4_NET_TRANS_RULE_ID_TCP
,
909 MLX4_NET_TRANS_RULE_ID_UDP
,
910 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
913 extern const u16 __sw_id_hw
[];
915 static inline int map_hw_to_sw_id(u16 header_id
)
919 for (i
= 0; i
< MLX4_NET_TRANS_RULE_NUM
; i
++) {
920 if (header_id
== __sw_id_hw
[i
])
926 enum mlx4_net_trans_promisc_mode
{
932 MLX4_FS_MODE_NUM
, /* should be last */
935 struct mlx4_spec_eth
{
936 u8 dst_mac
[ETH_ALEN
];
937 u8 dst_mac_msk
[ETH_ALEN
];
938 u8 src_mac
[ETH_ALEN
];
939 u8 src_mac_msk
[ETH_ALEN
];
940 u8 ether_type_enable
;
946 struct mlx4_spec_tcp_udp
{
953 struct mlx4_spec_ipv4
{
960 struct mlx4_spec_ib
{
967 struct mlx4_spec_list
{
968 struct list_head list
;
969 enum mlx4_net_trans_rule_id id
;
971 struct mlx4_spec_eth eth
;
972 struct mlx4_spec_ib ib
;
973 struct mlx4_spec_ipv4 ipv4
;
974 struct mlx4_spec_tcp_udp tcp_udp
;
978 enum mlx4_net_trans_hw_rule_queue
{
979 MLX4_NET_TRANS_Q_FIFO
,
980 MLX4_NET_TRANS_Q_LIFO
,
983 struct mlx4_net_trans_rule
{
984 struct list_head list
;
985 enum mlx4_net_trans_hw_rule_queue queue_mode
;
988 enum mlx4_net_trans_promisc_mode promisc_mode
;
994 struct mlx4_net_trans_rule_hw_ctrl
{
1006 struct mlx4_net_trans_rule_hw_ib
{
1017 struct mlx4_net_trans_rule_hw_eth
{
1030 u8 ether_type_enable
;
1032 __be16 vlan_tag_msk
;
1036 struct mlx4_net_trans_rule_hw_tcp_udp
{
1043 __be16 dst_port_msk
;
1047 __be16 src_port_msk
;
1050 struct mlx4_net_trans_rule_hw_ipv4
{
1068 struct mlx4_net_trans_rule_hw_eth eth
;
1069 struct mlx4_net_trans_rule_hw_ib ib
;
1070 struct mlx4_net_trans_rule_hw_ipv4 ipv4
;
1071 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp
;
1075 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
1076 enum mlx4_net_trans_promisc_mode mode
);
1077 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
1078 enum mlx4_net_trans_promisc_mode mode
);
1079 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1080 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1081 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1082 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1083 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
1085 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1086 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1087 int mlx4_get_base_qpn(struct mlx4_dev
*dev
, u8 port
);
1088 int __mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
1089 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
1090 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
1091 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
1092 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
1094 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
1095 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
1096 u8
*pg
, u16
*ratelimit
);
1097 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
1098 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
1099 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
);
1101 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
1102 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
1103 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
1104 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
1105 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1106 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
1107 u32
*lkey
, u32
*rkey
);
1108 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1109 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
1110 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
1111 int mlx4_assign_eq(struct mlx4_dev
*dev
, char *name
, struct cpu_rmap
*rmap
,
1113 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
1115 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
1116 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
1118 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
1119 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
1121 int mlx4_flow_attach(struct mlx4_dev
*dev
,
1122 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
1123 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
1124 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev
*dev
,
1125 enum mlx4_net_trans_promisc_mode flow_type
);
1126 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev
*dev
,
1127 enum mlx4_net_trans_rule_id id
);
1128 int mlx4_hw_rule_sz(struct mlx4_dev
*dev
, enum mlx4_net_trans_rule_id id
);
1130 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
,
1133 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
);
1135 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
);
1136 int mlx4_gen_pkey_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1137 int mlx4_gen_guid_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1138 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev
*dev
, u8 port
, int attr
);
1139 int mlx4_gen_port_state_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
, u8 port_subtype_change
);
1140 enum slave_port_state
mlx4_get_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
);
1141 int set_and_calc_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
, int event
, enum slave_port_gen_event
*gen_event
);
1143 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
);
1144 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
);
1146 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
);
1148 #endif /* MLX4_DEVICE_H */