2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
43 #include <linux/atomic.h>
45 #include <linux/timecounter.h>
47 #define MAX_MSIX_P_PORT 17
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
52 #define MLX4_MAX_100M_UNITS_VAL 255 /*
53 * work around: can't set values
54 * greater then this value when
55 * using 100 Mbps units.
57 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
58 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
59 #define MLX4_RATELIMIT_DEFAULT 0x00ff
61 #define MLX4_ROCE_MAX_GIDS 128
62 #define MLX4_ROCE_PF_GIDS 16
65 MLX4_FLAG_MSI_X
= 1 << 0,
66 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
67 MLX4_FLAG_MASTER
= 1 << 2,
68 MLX4_FLAG_SLAVE
= 1 << 3,
69 MLX4_FLAG_SRIOV
= 1 << 4,
70 MLX4_FLAG_OLD_REG_MAC
= 1 << 6,
71 MLX4_FLAG_BONDED
= 1 << 7
75 MLX4_PORT_CAP_IS_SM
= 1 << 1,
76 MLX4_PORT_CAP_DEV_MGMT_SUP
= 1 << 19,
81 MLX4_MAX_PORT_PKEYS
= 128
84 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
85 * These qkeys must not be allowed for general use. This is a 64k range,
86 * and to test for violation, we use the mask (protect against future chg).
88 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
89 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
92 MLX4_BOARD_ID_LEN
= 64
97 MLX4_MAX_NUM_VF
= 126,
98 MLX4_MAX_NUM_VF_P_PORT
= 64,
100 MLX4_MAX_EQ_NUM
= 1024,
101 MLX4_MFUNC_EQ_NUM
= 4,
102 MLX4_MFUNC_MAX_EQES
= 8,
103 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
106 /* Driver supports 3 diffrent device methods to manage traffic steering:
107 * -device managed - High level API for ib and eth flow steering. FW is
108 * managing flow steering tables.
109 * - B0 steering mode - Common low level API for ib and (if supported) eth.
110 * - A0 steering mode - Limited low level API for eth. In case of IB,
114 MLX4_STEERING_MODE_A0
,
115 MLX4_STEERING_MODE_B0
,
116 MLX4_STEERING_MODE_DEVICE_MANAGED
120 MLX4_STEERING_DMFS_A0_DEFAULT
,
121 MLX4_STEERING_DMFS_A0_DYNAMIC
,
122 MLX4_STEERING_DMFS_A0_STATIC
,
123 MLX4_STEERING_DMFS_A0_DISABLE
,
124 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
127 static inline const char *mlx4_steering_mode_str(int steering_mode
)
129 switch (steering_mode
) {
130 case MLX4_STEERING_MODE_A0
:
131 return "A0 steering";
133 case MLX4_STEERING_MODE_B0
:
134 return "B0 steering";
136 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
137 return "Device managed flow steering";
140 return "Unrecognize steering mode";
145 MLX4_TUNNEL_OFFLOAD_MODE_NONE
,
146 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
150 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
151 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
152 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
153 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
154 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
155 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
156 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
157 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
158 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
159 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
160 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
161 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
162 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
163 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
164 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
165 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
166 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
167 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
168 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
169 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
170 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
171 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
172 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
173 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
174 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
175 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG
= 1LL << 52,
176 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED
= 1LL << 53,
177 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55,
178 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
= 1LL << 59,
179 MLX4_DEV_CAP_FLAG_64B_EQE
= 1LL << 61,
180 MLX4_DEV_CAP_FLAG_64B_CQE
= 1LL << 62
184 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
185 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
186 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
187 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3,
188 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
= 1LL << 4,
189 MLX4_DEV_CAP_FLAG2_TS
= 1LL << 5,
190 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
= 1LL << 6,
191 MLX4_DEV_CAP_FLAG2_FSM
= 1LL << 7,
192 MLX4_DEV_CAP_FLAG2_UPDATE_QP
= 1LL << 8,
193 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB
= 1LL << 9,
194 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
= 1LL << 10,
195 MLX4_DEV_CAP_FLAG2_MAD_DEMUX
= 1LL << 11,
196 MLX4_DEV_CAP_FLAG2_CQE_STRIDE
= 1LL << 12,
197 MLX4_DEV_CAP_FLAG2_EQE_STRIDE
= 1LL << 13,
198 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL
= 1LL << 14,
199 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP
= 1LL << 15,
200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV
= 1LL << 16,
201 MLX4_DEV_CAP_FLAG2_SYS_EQS
= 1LL << 17,
202 MLX4_DEV_CAP_FLAG2_80_VFS
= 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0
= 1LL << 19,
204 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT
= 1LL << 20,
205 MLX4_DEV_CAP_FLAG2_PORT_REMAP
= 1LL << 21,
206 MLX4_DEV_CAP_FLAG2_QCN
= 1LL << 22,
207 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT
= 1LL << 23,
208 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN
= 1LL << 24,
209 MLX4_DEV_CAP_FLAG2_QOS_VPP
= 1LL << 25,
210 MLX4_DEV_CAP_FLAG2_ETS_CFG
= 1LL << 26,
211 MLX4_DEV_CAP_FLAG2_PORT_BEACON
= 1LL << 27,
212 MLX4_DEV_CAP_FLAG2_IGNORE_FCS
= 1LL << 28,
216 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP
= 1LL << 0,
217 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP
= 1LL << 1
221 MLX4_VF_CAP_FLAG_RESET
= 1 << 0
224 /* bit enums for an 8-bit flags field indicating special use
225 * QPs which require special handling in qp_reserve_range.
226 * Currently, this only includes QPs used by the ETH interface,
227 * where we expect to use blueflame. These QPs must not have
228 * bits 6 and 7 set in their qp number.
230 * This enum may use only bits 0..7.
233 MLX4_RESERVE_A0_QP
= 1 << 6,
234 MLX4_RESERVE_ETH_BF_QP
= 1 << 7,
238 MLX4_DEV_CAP_64B_EQE_ENABLED
= 1LL << 0,
239 MLX4_DEV_CAP_64B_CQE_ENABLED
= 1LL << 1,
240 MLX4_DEV_CAP_CQE_STRIDE_ENABLED
= 1LL << 2,
241 MLX4_DEV_CAP_EQE_STRIDE_ENABLED
= 1LL << 3
245 MLX4_USER_DEV_CAP_LARGE_CQE
= 1L << 0
249 MLX4_FUNC_CAP_64B_EQE_CQE
= 1L << 0,
250 MLX4_FUNC_CAP_EQE_CQE_STRIDE
= 1L << 1,
251 MLX4_FUNC_CAP_DMFS_A0_STATIC
= 1L << 2
255 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
258 MLX4_BMME_FLAG_WIN_TYPE_2B
= 1 << 1,
259 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
260 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
261 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
262 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
263 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
264 MLX4_BMME_FLAG_PORT_REMAP
= 1 << 24,
265 MLX4_BMME_FLAG_VSD_INIT2RTR
= 1 << 28,
269 MLX4_FLAG_PORT_REMAP
= MLX4_BMME_FLAG_PORT_REMAP
273 MLX4_EVENT_TYPE_COMP
= 0x00,
274 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
275 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
276 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
277 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
278 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
279 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
280 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
281 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
282 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
283 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
284 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
285 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
286 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
287 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
288 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
289 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
290 MLX4_EVENT_TYPE_CMD
= 0x0a,
291 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
292 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
293 MLX4_EVENT_TYPE_OP_REQUIRED
= 0x1a,
294 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
295 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
296 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT
= 0x1d,
297 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT
= 0x3e,
298 MLX4_EVENT_TYPE_NONE
= 0xff,
302 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
303 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
307 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE
= 1,
308 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE
= 2,
312 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
315 enum slave_port_state
{
321 enum slave_port_gen_event
{
322 SLAVE_PORT_GEN_EVENT_DOWN
= 0,
323 SLAVE_PORT_GEN_EVENT_UP
,
324 SLAVE_PORT_GEN_EVENT_NONE
,
327 enum slave_port_state_event
{
328 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN
,
329 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
,
330 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID
,
331 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
,
335 MLX4_PERM_LOCAL_READ
= 1 << 10,
336 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
337 MLX4_PERM_REMOTE_READ
= 1 << 12,
338 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
339 MLX4_PERM_ATOMIC
= 1 << 14,
340 MLX4_PERM_BIND_MW
= 1 << 15,
341 MLX4_PERM_MASK
= 0xFC00
345 MLX4_OPCODE_NOP
= 0x00,
346 MLX4_OPCODE_SEND_INVAL
= 0x01,
347 MLX4_OPCODE_RDMA_WRITE
= 0x08,
348 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
349 MLX4_OPCODE_SEND
= 0x0a,
350 MLX4_OPCODE_SEND_IMM
= 0x0b,
351 MLX4_OPCODE_LSO
= 0x0e,
352 MLX4_OPCODE_RDMA_READ
= 0x10,
353 MLX4_OPCODE_ATOMIC_CS
= 0x11,
354 MLX4_OPCODE_ATOMIC_FA
= 0x12,
355 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
356 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
357 MLX4_OPCODE_BIND_MW
= 0x18,
358 MLX4_OPCODE_FMR
= 0x19,
359 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
360 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
362 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
363 MLX4_RECV_OPCODE_SEND
= 0x01,
364 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
365 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
367 MLX4_CQE_OPCODE_ERROR
= 0x1e,
368 MLX4_CQE_OPCODE_RESIZE
= 0x16,
372 MLX4_STAT_RATE_OFFSET
= 5
376 MLX4_PROT_IB_IPV6
= 0,
383 MLX4_MTT_FLAG_PRESENT
= 1
386 enum mlx4_qp_region
{
387 MLX4_QP_REGION_FW
= 0,
388 MLX4_QP_REGION_RSS_RAW_ETH
,
389 MLX4_QP_REGION_BOTTOM
= MLX4_QP_REGION_RSS_RAW_ETH
,
390 MLX4_QP_REGION_ETH_ADDR
,
391 MLX4_QP_REGION_FC_ADDR
,
392 MLX4_QP_REGION_FC_EXCH
,
396 enum mlx4_port_type
{
397 MLX4_PORT_TYPE_NONE
= 0,
398 MLX4_PORT_TYPE_IB
= 1,
399 MLX4_PORT_TYPE_ETH
= 2,
400 MLX4_PORT_TYPE_AUTO
= 3
403 enum mlx4_special_vlan_idx
{
404 MLX4_NO_VLAN_IDX
= 0,
409 enum mlx4_steer_type
{
416 MLX4_NUM_FEXCH
= 64 * 1024,
420 MLX4_MAX_FAST_REG_PAGES
= 511,
424 MLX4_DEV_PMC_SUBTYPE_GUID_INFO
= 0x14,
425 MLX4_DEV_PMC_SUBTYPE_PORT_INFO
= 0x15,
426 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE
= 0x16,
429 /* Port mgmt change event handling */
431 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK
= 1 << 0,
432 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK
= 1 << 1,
433 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK
= 1 << 2,
434 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK
= 1 << 3,
435 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK
= 1 << 4,
439 MLX4_DEVICE_STATE_UP
= 1 << 0,
440 MLX4_DEVICE_STATE_INTERNAL_ERROR
= 1 << 1,
444 MLX4_INTERFACE_STATE_UP
= 1 << 0,
445 MLX4_INTERFACE_STATE_DELETION
= 1 << 1,
448 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
449 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
451 enum mlx4_module_id
{
452 MLX4_MODULE_ID_SFP
= 0x3,
453 MLX4_MODULE_ID_QSFP
= 0xC,
454 MLX4_MODULE_ID_QSFP_PLUS
= 0xD,
455 MLX4_MODULE_ID_QSFP28
= 0x11,
459 MLX4_QP_RATE_LIMIT_NONE
= 0,
460 MLX4_QP_RATE_LIMIT_KBS
= 1,
461 MLX4_QP_RATE_LIMIT_MBS
= 2,
462 MLX4_QP_RATE_LIMIT_GBS
= 3
465 struct mlx4_rate_limit_caps
{
466 u16 num_rates
; /* Number of different rates */
473 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
475 return (major
<< 32) | (minor
<< 16) | subminor
;
478 struct mlx4_phys_caps
{
479 u32 gid_phys_table_len
[MLX4_MAX_PORTS
+ 1];
480 u32 pkey_phys_table_len
[MLX4_MAX_PORTS
+ 1];
484 u32 base_tunnel_sqpn
;
491 int vl_cap
[MLX4_MAX_PORTS
+ 1];
492 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
493 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
494 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
495 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
496 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
497 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
498 int trans_type
[MLX4_MAX_PORTS
+ 1];
499 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
500 int wavelength
[MLX4_MAX_PORTS
+ 1];
501 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
502 int local_ca_ack_delay
;
506 int bf_regs_per_page
;
513 int max_qp_init_rdma
;
514 int max_qp_dest_rdma
;
530 int num_comp_vectors
;
535 int fmr_reserved_mtts
;
544 int dmfs_high_steer_mode
;
545 int fs_log_max_ucast_qp_range_size
;
557 u16 stat_rate_support
;
558 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
561 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
563 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
566 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
567 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
568 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
569 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
570 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
571 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
573 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
578 u32 userspace_caps
; /* userspace must be aware of these */
579 u32 function_caps
; /* VFs must be aware of these */
581 u64 phys_port_id
[MLX4_MAX_PORTS
+ 1];
582 int tunnel_offload_mode
;
583 u8 rx_checksum_flags_port
[MLX4_MAX_PORTS
+ 1];
584 u8 alloc_res_qp_mask
;
585 u32 dmfs_high_rate_qpn_base
;
586 u32 dmfs_high_rate_qpn_range
;
588 struct mlx4_rate_limit_caps rl_caps
;
591 struct mlx4_buf_list
{
597 struct mlx4_buf_list direct
;
598 struct mlx4_buf_list
*page_list
;
611 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
614 struct mlx4_db_pgdir
{
615 struct list_head list
;
616 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
617 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
618 unsigned long *bits
[2];
623 struct mlx4_ib_user_db_page
;
628 struct mlx4_db_pgdir
*pgdir
;
629 struct mlx4_ib_user_db_page
*user_page
;
636 struct mlx4_hwq_resources
{
660 enum mlx4_mw_type type
;
666 struct mlx4_mpt_entry
*mpt
;
668 dma_addr_t dma_handle
;
678 struct list_head bf_list
;
679 unsigned free_bf_bmap
;
681 void __iomem
*bf_map
;
687 struct mlx4_uar
*uar
;
692 void (*comp
) (struct mlx4_cq
*);
693 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
695 struct mlx4_uar
*uar
;
708 struct completion free
;
710 struct list_head list
;
711 void (*comp
)(struct mlx4_cq
*);
714 int reset_notify_added
;
715 struct list_head reset_notify
;
719 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
724 struct completion free
;
728 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
736 struct completion free
;
748 __be32 sl_tclass_flowlabel
;
761 __be32 sl_tclass_flowlabel
;
771 struct mlx4_eth_av eth
;
774 struct mlx4_counter
{
800 struct mlx4_dev_persistent
{
801 struct pci_dev
*pdev
;
802 struct mlx4_dev
*dev
;
803 int nvfs
[MLX4_MAX_PORTS
+ 1];
805 enum mlx4_port_type curr_port_type
[MLX4_MAX_PORTS
+ 1];
806 enum mlx4_port_type curr_port_poss_type
[MLX4_MAX_PORTS
+ 1];
807 struct work_struct catas_work
;
808 struct workqueue_struct
*catas_wq
;
809 struct mutex device_state_mutex
; /* protect HW state */
811 struct mutex interface_state_mutex
; /* protect SW state */
816 struct mlx4_dev_persistent
*persist
;
818 unsigned long num_slaves
;
819 struct mlx4_caps caps
;
820 struct mlx4_phys_caps phys_caps
;
821 struct mlx4_quotas quotas
;
822 struct radix_tree_root qp_table_tree
;
824 char board_id
[MLX4_BOARD_ID_LEN
];
826 int oper_log_mgm_entry_size
;
827 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
828 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
829 struct mlx4_vf_dev
*dev_vfs
;
832 struct mlx4_clock_params
{
871 } __packed port_change
;
873 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
875 u32 bit_vec
[COMM_CHANNEL_BIT_ARRAY_SIZE
];
876 } __packed comm_channel_arm
;
881 } __packed mac_update
;
884 } __packed flr_event
;
886 __be16 current_temperature
;
887 __be16 warning_threshold
;
900 } __packed port_info
;
903 __be32 tbl_entries_mask
;
904 } __packed tbl_change_info
;
906 } __packed port_mgmt_change
;
911 } __packed bad_cable
;
918 struct mlx4_init_port_param
{
932 #define MAD_IFC_DATA_SZ 192
933 /* MAD IFC Mailbox */
934 struct mlx4_mad_ifc
{
940 __be16 class_specific
;
949 u8 data
[MAD_IFC_DATA_SZ
];
952 #define mlx4_foreach_port(port, dev, type) \
953 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
954 if ((type) == (dev)->caps.port_mask[(port)])
956 #define mlx4_foreach_non_ib_transport_port(port, dev) \
957 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
958 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
960 #define mlx4_foreach_ib_transport_port(port, dev) \
961 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
962 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
963 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
965 #define MLX4_INVALID_SLAVE_ID 0xFF
967 void handle_port_mgmt_change_event(struct work_struct
*work
);
969 static inline int mlx4_master_func_num(struct mlx4_dev
*dev
)
971 return dev
->caps
.function
;
974 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
976 return dev
->flags
& MLX4_FLAG_MASTER
;
979 static inline int mlx4_num_reserved_sqps(struct mlx4_dev
*dev
)
981 return dev
->phys_caps
.base_sqpn
+ 8 +
982 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
);
985 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
987 return (qpn
< dev
->phys_caps
.base_sqpn
+ 8 +
988 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
) &&
989 qpn
>= dev
->phys_caps
.base_sqpn
) ||
990 (qpn
< dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
]);
993 static inline int mlx4_is_guest_proxy(struct mlx4_dev
*dev
, int slave
, u32 qpn
)
995 int guest_proxy_base
= dev
->phys_caps
.base_proxy_sqpn
+ slave
* 8;
997 if (qpn
>= guest_proxy_base
&& qpn
< guest_proxy_base
+ 8)
1003 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
1005 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
1008 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
1010 return dev
->flags
& MLX4_FLAG_SLAVE
;
1013 static inline int mlx4_is_eth(struct mlx4_dev
*dev
, int port
)
1015 return dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
? 0 : 1;
1018 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
1019 struct mlx4_buf
*buf
, gfp_t gfp
);
1020 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
1021 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
1023 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
1024 return buf
->direct
.buf
+ offset
;
1026 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
1027 (offset
& (PAGE_SIZE
- 1));
1030 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
1031 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
1032 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
1033 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
1035 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
1036 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
1037 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
, int node
);
1038 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
1040 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
1041 struct mlx4_mtt
*mtt
);
1042 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
1043 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
1045 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
1046 int npages
, int page_shift
, struct mlx4_mr
*mr
);
1047 int mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
1048 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
1049 int mlx4_mw_alloc(struct mlx4_dev
*dev
, u32 pd
, enum mlx4_mw_type type
,
1050 struct mlx4_mw
*mw
);
1051 void mlx4_mw_free(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
1052 int mlx4_mw_enable(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
1053 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
1054 int start_index
, int npages
, u64
*page_list
);
1055 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
1056 struct mlx4_buf
*buf
, gfp_t gfp
);
1058 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
,
1060 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
1062 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
1063 int size
, int max_direct
);
1064 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
1067 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
1068 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
1069 unsigned vector
, int collapsed
, int timestamp_en
);
1070 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
1071 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
,
1072 int *base
, u8 flags
);
1073 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
1075 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
,
1077 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
1079 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
1080 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
1081 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
1082 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
1083 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
1085 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
1086 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
1088 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1089 int block_mcast_loopback
, enum mlx4_protocol prot
);
1090 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1091 enum mlx4_protocol prot
);
1092 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1093 u8 port
, int block_mcast_loopback
,
1094 enum mlx4_protocol protocol
, u64
*reg_id
);
1095 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1096 enum mlx4_protocol protocol
, u64 reg_id
);
1099 MLX4_DOMAIN_UVERBS
= 0x1000,
1100 MLX4_DOMAIN_ETHTOOL
= 0x2000,
1101 MLX4_DOMAIN_RFS
= 0x3000,
1102 MLX4_DOMAIN_NIC
= 0x5000,
1105 enum mlx4_net_trans_rule_id
{
1106 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
1107 MLX4_NET_TRANS_RULE_ID_IB
,
1108 MLX4_NET_TRANS_RULE_ID_IPV6
,
1109 MLX4_NET_TRANS_RULE_ID_IPV4
,
1110 MLX4_NET_TRANS_RULE_ID_TCP
,
1111 MLX4_NET_TRANS_RULE_ID_UDP
,
1112 MLX4_NET_TRANS_RULE_ID_VXLAN
,
1113 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
1116 extern const u16 __sw_id_hw
[];
1118 static inline int map_hw_to_sw_id(u16 header_id
)
1122 for (i
= 0; i
< MLX4_NET_TRANS_RULE_NUM
; i
++) {
1123 if (header_id
== __sw_id_hw
[i
])
1129 enum mlx4_net_trans_promisc_mode
{
1130 MLX4_FS_REGULAR
= 1,
1131 MLX4_FS_ALL_DEFAULT
,
1135 MLX4_FS_MODE_NUM
, /* should be last */
1138 struct mlx4_spec_eth
{
1139 u8 dst_mac
[ETH_ALEN
];
1140 u8 dst_mac_msk
[ETH_ALEN
];
1141 u8 src_mac
[ETH_ALEN
];
1142 u8 src_mac_msk
[ETH_ALEN
];
1143 u8 ether_type_enable
;
1149 struct mlx4_spec_tcp_udp
{
1151 __be16 dst_port_msk
;
1153 __be16 src_port_msk
;
1156 struct mlx4_spec_ipv4
{
1163 struct mlx4_spec_ib
{
1170 struct mlx4_spec_vxlan
{
1176 struct mlx4_spec_list
{
1177 struct list_head list
;
1178 enum mlx4_net_trans_rule_id id
;
1180 struct mlx4_spec_eth eth
;
1181 struct mlx4_spec_ib ib
;
1182 struct mlx4_spec_ipv4 ipv4
;
1183 struct mlx4_spec_tcp_udp tcp_udp
;
1184 struct mlx4_spec_vxlan vxlan
;
1188 enum mlx4_net_trans_hw_rule_queue
{
1189 MLX4_NET_TRANS_Q_FIFO
,
1190 MLX4_NET_TRANS_Q_LIFO
,
1193 struct mlx4_net_trans_rule
{
1194 struct list_head list
;
1195 enum mlx4_net_trans_hw_rule_queue queue_mode
;
1197 bool allow_loopback
;
1198 enum mlx4_net_trans_promisc_mode promisc_mode
;
1204 struct mlx4_net_trans_rule_hw_ctrl
{
1216 struct mlx4_net_trans_rule_hw_ib
{
1227 struct mlx4_net_trans_rule_hw_eth
{
1240 u8 ether_type_enable
;
1242 __be16 vlan_tag_msk
;
1246 struct mlx4_net_trans_rule_hw_tcp_udp
{
1253 __be16 dst_port_msk
;
1257 __be16 src_port_msk
;
1260 struct mlx4_net_trans_rule_hw_ipv4
{
1271 struct mlx4_net_trans_rule_hw_vxlan
{
1287 struct mlx4_net_trans_rule_hw_eth eth
;
1288 struct mlx4_net_trans_rule_hw_ib ib
;
1289 struct mlx4_net_trans_rule_hw_ipv4 ipv4
;
1290 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp
;
1291 struct mlx4_net_trans_rule_hw_vxlan vxlan
;
1296 VXLAN_STEER_BY_OUTER_MAC
= 1 << 0,
1297 VXLAN_STEER_BY_OUTER_VLAN
= 1 << 1,
1298 VXLAN_STEER_BY_VSID_VNI
= 1 << 2,
1299 VXLAN_STEER_BY_INNER_MAC
= 1 << 3,
1300 VXLAN_STEER_BY_INNER_VLAN
= 1 << 4,
1304 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
1305 enum mlx4_net_trans_promisc_mode mode
);
1306 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
1307 enum mlx4_net_trans_promisc_mode mode
);
1308 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1309 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1310 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1311 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1312 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
1314 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1315 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1316 int mlx4_get_base_qpn(struct mlx4_dev
*dev
, u8 port
);
1317 int __mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
1318 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
1319 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
1320 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
1322 int mlx4_SET_PORT_BEACON(struct mlx4_dev
*dev
, u8 port
, u16 time
);
1323 int mlx4_SET_PORT_fcs_check(struct mlx4_dev
*dev
, u8 port
,
1324 u8 ignore_fcs_value
);
1325 int mlx4_SET_PORT_VXLAN(struct mlx4_dev
*dev
, u8 port
, u8 steering
, int enable
);
1326 int mlx4_find_cached_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *idx
);
1327 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
1328 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
1329 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
);
1331 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
1332 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
1333 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
1334 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
1335 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1336 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
1337 u32
*lkey
, u32
*rkey
);
1338 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1339 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
1340 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
1341 int mlx4_assign_eq(struct mlx4_dev
*dev
, char *name
, struct cpu_rmap
*rmap
,
1343 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
1345 int mlx4_eq_get_irq(struct mlx4_dev
*dev
, int vec
);
1347 int mlx4_get_phys_port_id(struct mlx4_dev
*dev
);
1348 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
1349 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
1351 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
1352 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
1354 void mlx4_set_admin_guid(struct mlx4_dev
*dev
, __be64 guid
, int entry
,
1356 __be64
mlx4_get_admin_guid(struct mlx4_dev
*dev
, int entry
, int port
);
1357 void mlx4_set_random_admin_guid(struct mlx4_dev
*dev
, int entry
, int port
);
1358 int mlx4_flow_attach(struct mlx4_dev
*dev
,
1359 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
1360 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
1361 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev
*dev
,
1362 enum mlx4_net_trans_promisc_mode flow_type
);
1363 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev
*dev
,
1364 enum mlx4_net_trans_rule_id id
);
1365 int mlx4_hw_rule_sz(struct mlx4_dev
*dev
, enum mlx4_net_trans_rule_id id
);
1367 int mlx4_tunnel_steer_add(struct mlx4_dev
*dev
, unsigned char *addr
,
1368 int port
, int qpn
, u16 prio
, u64
*reg_id
);
1370 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
,
1373 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
);
1375 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
);
1376 int mlx4_gen_pkey_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1377 int mlx4_gen_guid_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1378 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev
*dev
, u8 port
, int attr
);
1379 int mlx4_gen_port_state_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
, u8 port_subtype_change
);
1380 enum slave_port_state
mlx4_get_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
);
1381 int set_and_calc_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
, int event
, enum slave_port_gen_event
*gen_event
);
1383 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
);
1384 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
);
1386 int mlx4_get_slave_from_roce_gid(struct mlx4_dev
*dev
, int port
, u8
*gid
,
1388 int mlx4_get_roce_gid_from_slave(struct mlx4_dev
*dev
, int port
, int slave_id
,
1391 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev
*dev
, u32 min_range_qpn
,
1394 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
);
1396 struct mlx4_active_ports
{
1397 DECLARE_BITMAP(ports
, MLX4_MAX_PORTS
);
1399 /* Returns a bitmap of the physical ports which are assigned to slave */
1400 struct mlx4_active_ports
mlx4_get_active_ports(struct mlx4_dev
*dev
, int slave
);
1402 /* Returns the physical port that represents the virtual port of the slave, */
1403 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1404 /* mapping is returned. */
1405 int mlx4_slave_convert_port(struct mlx4_dev
*dev
, int slave
, int port
);
1407 struct mlx4_slaves_pport
{
1408 DECLARE_BITMAP(slaves
, MLX4_MFUNC_MAX
);
1410 /* Returns a bitmap of all slaves that are assigned to port. */
1411 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport(struct mlx4_dev
*dev
,
1414 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1415 /* the ports that are set in crit_ports. */
1416 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport_actv(
1417 struct mlx4_dev
*dev
,
1418 const struct mlx4_active_ports
*crit_ports
);
1420 /* Returns the slave's virtual port that represents the physical port. */
1421 int mlx4_phys_to_slave_port(struct mlx4_dev
*dev
, int slave
, int port
);
1423 int mlx4_get_base_gid_ix(struct mlx4_dev
*dev
, int slave
, int port
);
1425 int mlx4_config_vxlan_port(struct mlx4_dev
*dev
, __be16 udp_port
);
1426 int mlx4_disable_rx_port_check(struct mlx4_dev
*dev
, bool dis
);
1427 int mlx4_virt2phy_port_map(struct mlx4_dev
*dev
, u32 port1
, u32 port2
);
1428 int mlx4_vf_smi_enabled(struct mlx4_dev
*dev
, int slave
, int port
);
1429 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
);
1430 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
,
1432 int mlx4_mr_hw_get_mpt(struct mlx4_dev
*dev
, struct mlx4_mr
*mmr
,
1433 struct mlx4_mpt_entry
***mpt_entry
);
1434 int mlx4_mr_hw_write_mpt(struct mlx4_dev
*dev
, struct mlx4_mr
*mmr
,
1435 struct mlx4_mpt_entry
**mpt_entry
);
1436 int mlx4_mr_hw_change_pd(struct mlx4_dev
*dev
, struct mlx4_mpt_entry
*mpt_entry
,
1438 int mlx4_mr_hw_change_access(struct mlx4_dev
*dev
,
1439 struct mlx4_mpt_entry
*mpt_entry
,
1441 void mlx4_mr_hw_put_mpt(struct mlx4_dev
*dev
,
1442 struct mlx4_mpt_entry
**mpt_entry
);
1443 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
1444 int mlx4_mr_rereg_mem_write(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
,
1445 u64 iova
, u64 size
, int npages
,
1446 int page_shift
, struct mlx4_mpt_entry
*mpt_entry
);
1448 int mlx4_get_module_info(struct mlx4_dev
*dev
, u8 port
,
1449 u16 offset
, u16 size
, u8
*data
);
1451 /* Returns true if running in low memory profile (kdump kernel) */
1452 static inline bool mlx4_low_memory_profile(void)
1454 return is_kdump_kernel();
1457 /* ACCESS REG commands */
1458 enum mlx4_access_reg_method
{
1459 MLX4_ACCESS_REG_QUERY
= 0x1,
1460 MLX4_ACCESS_REG_WRITE
= 0x2,
1463 /* ACCESS PTYS Reg command */
1464 enum mlx4_ptys_proto
{
1465 MLX4_PTYS_IB
= 1<<0,
1466 MLX4_PTYS_EN
= 1<<2,
1469 struct mlx4_ptys_reg
{
1475 __be32 eth_proto_cap
;
1476 __be16 ib_width_cap
;
1477 __be16 ib_speed_cap
;
1479 __be32 eth_proto_admin
;
1480 __be16 ib_width_admin
;
1481 __be16 ib_speed_admin
;
1483 __be32 eth_proto_oper
;
1484 __be16 ib_width_oper
;
1485 __be16 ib_speed_oper
;
1487 __be32 eth_proto_lp_adv
;
1490 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev
*dev
,
1491 enum mlx4_access_reg_method method
,
1492 struct mlx4_ptys_reg
*ptys_reg
);
1494 int mlx4_get_internal_clock_params(struct mlx4_dev
*dev
,
1495 struct mlx4_clock_params
*params
);
1497 #endif /* MLX4_DEVICE_H */