2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
42 #include <linux/atomic.h>
44 #include <linux/clocksource.h>
46 #define MAX_MSIX_P_PORT 17
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
53 #define MLX4_MAX_100M_UNITS_VAL 255 /*
54 * work around: can't set values
55 * greater then this value when
56 * using 100 Mbps units.
58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
60 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62 #define MLX4_ROCE_MAX_GIDS 128
63 #define MLX4_ROCE_PF_GIDS 16
66 MLX4_FLAG_MSI_X
= 1 << 0,
67 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
68 MLX4_FLAG_MASTER
= 1 << 2,
69 MLX4_FLAG_SLAVE
= 1 << 3,
70 MLX4_FLAG_SRIOV
= 1 << 4,
71 MLX4_FLAG_OLD_REG_MAC
= 1 << 6,
75 MLX4_PORT_CAP_IS_SM
= 1 << 1,
76 MLX4_PORT_CAP_DEV_MGMT_SUP
= 1 << 19,
81 MLX4_MAX_PORT_PKEYS
= 128
84 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
85 * These qkeys must not be allowed for general use. This is a 64k range,
86 * and to test for violation, we use the mask (protect against future chg).
88 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
89 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
92 MLX4_BOARD_ID_LEN
= 64
98 MLX4_MAX_NUM_VF_P_PORT
= 64,
100 MLX4_MAX_EQ_NUM
= 1024,
101 MLX4_MFUNC_EQ_NUM
= 4,
102 MLX4_MFUNC_MAX_EQES
= 8,
103 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
106 /* Driver supports 3 diffrent device methods to manage traffic steering:
107 * -device managed - High level API for ib and eth flow steering. FW is
108 * managing flow steering tables.
109 * - B0 steering mode - Common low level API for ib and (if supported) eth.
110 * - A0 steering mode - Limited low level API for eth. In case of IB,
114 MLX4_STEERING_MODE_A0
,
115 MLX4_STEERING_MODE_B0
,
116 MLX4_STEERING_MODE_DEVICE_MANAGED
119 static inline const char *mlx4_steering_mode_str(int steering_mode
)
121 switch (steering_mode
) {
122 case MLX4_STEERING_MODE_A0
:
123 return "A0 steering";
125 case MLX4_STEERING_MODE_B0
:
126 return "B0 steering";
128 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
129 return "Device managed flow steering";
132 return "Unrecognize steering mode";
137 MLX4_TUNNEL_OFFLOAD_MODE_NONE
,
138 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
142 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
143 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
144 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
145 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
146 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
147 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
148 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
149 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
150 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
151 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
152 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
153 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
154 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
155 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
156 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
157 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
158 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
159 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
160 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
161 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
162 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
163 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
164 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
165 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
166 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
167 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED
= 1LL << 53,
168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55,
169 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
= 1LL << 59,
170 MLX4_DEV_CAP_FLAG_64B_EQE
= 1LL << 61,
171 MLX4_DEV_CAP_FLAG_64B_CQE
= 1LL << 62
175 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
176 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
177 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
178 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3,
179 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
= 1LL << 4,
180 MLX4_DEV_CAP_FLAG2_TS
= 1LL << 5,
181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
= 1LL << 6,
182 MLX4_DEV_CAP_FLAG2_FSM
= 1LL << 7,
183 MLX4_DEV_CAP_FLAG2_UPDATE_QP
= 1LL << 8,
184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB
= 1LL << 9,
185 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
= 1LL << 10,
186 MLX4_DEV_CAP_FLAG2_MAD_DEMUX
= 1LL << 11,
190 MLX4_DEV_CAP_64B_EQE_ENABLED
= 1LL << 0,
191 MLX4_DEV_CAP_64B_CQE_ENABLED
= 1LL << 1
195 MLX4_USER_DEV_CAP_64B_CQE
= 1L << 0
199 MLX4_FUNC_CAP_64B_EQE_CQE
= 1L << 0
203 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
206 MLX4_BMME_FLAG_WIN_TYPE_2B
= 1 << 1,
207 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
208 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
209 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
210 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
211 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
215 MLX4_EVENT_TYPE_COMP
= 0x00,
216 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
217 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
218 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
219 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
220 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
221 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
222 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
223 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
224 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
225 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
226 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
227 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
228 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
229 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
230 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
231 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
232 MLX4_EVENT_TYPE_CMD
= 0x0a,
233 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
234 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
235 MLX4_EVENT_TYPE_OP_REQUIRED
= 0x1a,
236 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
237 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
238 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT
= 0x1d,
239 MLX4_EVENT_TYPE_NONE
= 0xff,
243 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
244 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
248 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
251 enum slave_port_state
{
257 enum slave_port_gen_event
{
258 SLAVE_PORT_GEN_EVENT_DOWN
= 0,
259 SLAVE_PORT_GEN_EVENT_UP
,
260 SLAVE_PORT_GEN_EVENT_NONE
,
263 enum slave_port_state_event
{
264 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN
,
265 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
,
266 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID
,
267 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
,
271 MLX4_PERM_LOCAL_READ
= 1 << 10,
272 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
273 MLX4_PERM_REMOTE_READ
= 1 << 12,
274 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
275 MLX4_PERM_ATOMIC
= 1 << 14,
276 MLX4_PERM_BIND_MW
= 1 << 15,
277 MLX4_PERM_MASK
= 0xFC00
281 MLX4_OPCODE_NOP
= 0x00,
282 MLX4_OPCODE_SEND_INVAL
= 0x01,
283 MLX4_OPCODE_RDMA_WRITE
= 0x08,
284 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
285 MLX4_OPCODE_SEND
= 0x0a,
286 MLX4_OPCODE_SEND_IMM
= 0x0b,
287 MLX4_OPCODE_LSO
= 0x0e,
288 MLX4_OPCODE_RDMA_READ
= 0x10,
289 MLX4_OPCODE_ATOMIC_CS
= 0x11,
290 MLX4_OPCODE_ATOMIC_FA
= 0x12,
291 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
292 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
293 MLX4_OPCODE_BIND_MW
= 0x18,
294 MLX4_OPCODE_FMR
= 0x19,
295 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
296 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
298 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
299 MLX4_RECV_OPCODE_SEND
= 0x01,
300 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
301 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
303 MLX4_CQE_OPCODE_ERROR
= 0x1e,
304 MLX4_CQE_OPCODE_RESIZE
= 0x16,
308 MLX4_STAT_RATE_OFFSET
= 5
312 MLX4_PROT_IB_IPV6
= 0,
319 MLX4_MTT_FLAG_PRESENT
= 1
322 enum mlx4_qp_region
{
323 MLX4_QP_REGION_FW
= 0,
324 MLX4_QP_REGION_ETH_ADDR
,
325 MLX4_QP_REGION_FC_ADDR
,
326 MLX4_QP_REGION_FC_EXCH
,
330 enum mlx4_port_type
{
331 MLX4_PORT_TYPE_NONE
= 0,
332 MLX4_PORT_TYPE_IB
= 1,
333 MLX4_PORT_TYPE_ETH
= 2,
334 MLX4_PORT_TYPE_AUTO
= 3
337 enum mlx4_special_vlan_idx
{
338 MLX4_NO_VLAN_IDX
= 0,
343 enum mlx4_steer_type
{
350 MLX4_NUM_FEXCH
= 64 * 1024,
354 MLX4_MAX_FAST_REG_PAGES
= 511,
358 MLX4_DEV_PMC_SUBTYPE_GUID_INFO
= 0x14,
359 MLX4_DEV_PMC_SUBTYPE_PORT_INFO
= 0x15,
360 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE
= 0x16,
363 /* Port mgmt change event handling */
365 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK
= 1 << 0,
366 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK
= 1 << 1,
367 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK
= 1 << 2,
368 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK
= 1 << 3,
369 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK
= 1 << 4,
372 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
373 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
375 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
377 return (major
<< 32) | (minor
<< 16) | subminor
;
380 struct mlx4_phys_caps
{
381 u32 gid_phys_table_len
[MLX4_MAX_PORTS
+ 1];
382 u32 pkey_phys_table_len
[MLX4_MAX_PORTS
+ 1];
386 u32 base_tunnel_sqpn
;
393 int vl_cap
[MLX4_MAX_PORTS
+ 1];
394 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
395 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
396 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
397 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
398 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
399 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
400 int trans_type
[MLX4_MAX_PORTS
+ 1];
401 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
402 int wavelength
[MLX4_MAX_PORTS
+ 1];
403 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
404 int local_ca_ack_delay
;
408 int bf_regs_per_page
;
415 int max_qp_init_rdma
;
416 int max_qp_dest_rdma
;
431 int num_comp_vectors
;
436 int fmr_reserved_mtts
;
445 int fs_log_max_ucast_qp_range_size
;
457 u16 stat_rate_support
;
458 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
461 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
463 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
466 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
467 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
468 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
469 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
470 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
471 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
473 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
478 u32 userspace_caps
; /* userspace must be aware of these */
479 u32 function_caps
; /* VFs must be aware of these */
481 u64 phys_port_id
[MLX4_MAX_PORTS
+ 1];
482 int tunnel_offload_mode
;
485 struct mlx4_buf_list
{
491 struct mlx4_buf_list direct
;
492 struct mlx4_buf_list
*page_list
;
505 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
508 struct mlx4_db_pgdir
{
509 struct list_head list
;
510 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
511 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
512 unsigned long *bits
[2];
517 struct mlx4_ib_user_db_page
;
522 struct mlx4_db_pgdir
*pgdir
;
523 struct mlx4_ib_user_db_page
*user_page
;
530 struct mlx4_hwq_resources
{
554 enum mlx4_mw_type type
;
560 struct mlx4_mpt_entry
*mpt
;
562 dma_addr_t dma_handle
;
572 struct list_head bf_list
;
573 unsigned free_bf_bmap
;
575 void __iomem
*bf_map
;
579 unsigned long offset
;
581 struct mlx4_uar
*uar
;
586 void (*comp
) (struct mlx4_cq
*);
587 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
589 struct mlx4_uar
*uar
;
602 struct completion free
;
606 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
611 struct completion free
;
615 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
623 struct completion free
;
635 __be32 sl_tclass_flowlabel
;
648 __be32 sl_tclass_flowlabel
;
658 struct mlx4_eth_av eth
;
661 struct mlx4_counter
{
688 struct pci_dev
*pdev
;
690 unsigned long num_slaves
;
691 struct mlx4_caps caps
;
692 struct mlx4_phys_caps phys_caps
;
693 struct mlx4_quotas quotas
;
694 struct radix_tree_root qp_table_tree
;
696 char board_id
[MLX4_BOARD_ID_LEN
];
699 int oper_log_mgm_entry_size
;
700 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
701 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
702 struct mlx4_vf_dev
*dev_vfs
;
738 } __packed port_change
;
740 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
742 u32 bit_vec
[COMM_CHANNEL_BIT_ARRAY_SIZE
];
743 } __packed comm_channel_arm
;
748 } __packed mac_update
;
751 } __packed flr_event
;
753 __be16 current_temperature
;
754 __be16 warning_threshold
;
767 } __packed port_info
;
770 __be32 tbl_entries_mask
;
771 } __packed tbl_change_info
;
773 } __packed port_mgmt_change
;
780 struct mlx4_init_port_param
{
794 #define mlx4_foreach_port(port, dev, type) \
795 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
796 if ((type) == (dev)->caps.port_mask[(port)])
798 #define mlx4_foreach_non_ib_transport_port(port, dev) \
799 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
800 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
802 #define mlx4_foreach_ib_transport_port(port, dev) \
803 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
804 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
805 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
807 #define MLX4_INVALID_SLAVE_ID 0xFF
809 void handle_port_mgmt_change_event(struct work_struct
*work
);
811 static inline int mlx4_master_func_num(struct mlx4_dev
*dev
)
813 return dev
->caps
.function
;
816 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
818 return dev
->flags
& MLX4_FLAG_MASTER
;
821 static inline int mlx4_num_reserved_sqps(struct mlx4_dev
*dev
)
823 return dev
->phys_caps
.base_sqpn
+ 8 +
824 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
);
827 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
829 return (qpn
< dev
->phys_caps
.base_sqpn
+ 8 +
830 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
));
833 static inline int mlx4_is_guest_proxy(struct mlx4_dev
*dev
, int slave
, u32 qpn
)
835 int guest_proxy_base
= dev
->phys_caps
.base_proxy_sqpn
+ slave
* 8;
837 if (qpn
>= guest_proxy_base
&& qpn
< guest_proxy_base
+ 8)
843 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
845 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
848 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
850 return dev
->flags
& MLX4_FLAG_SLAVE
;
853 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
854 struct mlx4_buf
*buf
, gfp_t gfp
);
855 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
856 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
858 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
859 return buf
->direct
.buf
+ offset
;
861 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
862 (offset
& (PAGE_SIZE
- 1));
865 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
866 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
867 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
868 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
870 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
871 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
872 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
, int node
);
873 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
875 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
876 struct mlx4_mtt
*mtt
);
877 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
878 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
880 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
881 int npages
, int page_shift
, struct mlx4_mr
*mr
);
882 int mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
883 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
884 int mlx4_mw_alloc(struct mlx4_dev
*dev
, u32 pd
, enum mlx4_mw_type type
,
886 void mlx4_mw_free(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
887 int mlx4_mw_enable(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
888 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
889 int start_index
, int npages
, u64
*page_list
);
890 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
891 struct mlx4_buf
*buf
, gfp_t gfp
);
893 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
,
895 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
897 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
898 int size
, int max_direct
);
899 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
902 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
903 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
904 unsigned vector
, int collapsed
, int timestamp_en
);
905 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
907 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
908 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
910 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
,
912 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
914 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
915 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
916 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
917 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
918 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
920 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
921 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
923 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
924 int block_mcast_loopback
, enum mlx4_protocol prot
);
925 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
926 enum mlx4_protocol prot
);
927 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
928 u8 port
, int block_mcast_loopback
,
929 enum mlx4_protocol protocol
, u64
*reg_id
);
930 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
931 enum mlx4_protocol protocol
, u64 reg_id
);
934 MLX4_DOMAIN_UVERBS
= 0x1000,
935 MLX4_DOMAIN_ETHTOOL
= 0x2000,
936 MLX4_DOMAIN_RFS
= 0x3000,
937 MLX4_DOMAIN_NIC
= 0x5000,
940 enum mlx4_net_trans_rule_id
{
941 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
942 MLX4_NET_TRANS_RULE_ID_IB
,
943 MLX4_NET_TRANS_RULE_ID_IPV6
,
944 MLX4_NET_TRANS_RULE_ID_IPV4
,
945 MLX4_NET_TRANS_RULE_ID_TCP
,
946 MLX4_NET_TRANS_RULE_ID_UDP
,
947 MLX4_NET_TRANS_RULE_ID_VXLAN
,
948 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
951 extern const u16 __sw_id_hw
[];
953 static inline int map_hw_to_sw_id(u16 header_id
)
957 for (i
= 0; i
< MLX4_NET_TRANS_RULE_NUM
; i
++) {
958 if (header_id
== __sw_id_hw
[i
])
964 enum mlx4_net_trans_promisc_mode
{
970 MLX4_FS_MODE_NUM
, /* should be last */
973 struct mlx4_spec_eth
{
974 u8 dst_mac
[ETH_ALEN
];
975 u8 dst_mac_msk
[ETH_ALEN
];
976 u8 src_mac
[ETH_ALEN
];
977 u8 src_mac_msk
[ETH_ALEN
];
978 u8 ether_type_enable
;
984 struct mlx4_spec_tcp_udp
{
991 struct mlx4_spec_ipv4
{
998 struct mlx4_spec_ib
{
1005 struct mlx4_spec_vxlan
{
1011 struct mlx4_spec_list
{
1012 struct list_head list
;
1013 enum mlx4_net_trans_rule_id id
;
1015 struct mlx4_spec_eth eth
;
1016 struct mlx4_spec_ib ib
;
1017 struct mlx4_spec_ipv4 ipv4
;
1018 struct mlx4_spec_tcp_udp tcp_udp
;
1019 struct mlx4_spec_vxlan vxlan
;
1023 enum mlx4_net_trans_hw_rule_queue
{
1024 MLX4_NET_TRANS_Q_FIFO
,
1025 MLX4_NET_TRANS_Q_LIFO
,
1028 struct mlx4_net_trans_rule
{
1029 struct list_head list
;
1030 enum mlx4_net_trans_hw_rule_queue queue_mode
;
1032 bool allow_loopback
;
1033 enum mlx4_net_trans_promisc_mode promisc_mode
;
1039 struct mlx4_net_trans_rule_hw_ctrl
{
1051 struct mlx4_net_trans_rule_hw_ib
{
1062 struct mlx4_net_trans_rule_hw_eth
{
1075 u8 ether_type_enable
;
1077 __be16 vlan_tag_msk
;
1081 struct mlx4_net_trans_rule_hw_tcp_udp
{
1088 __be16 dst_port_msk
;
1092 __be16 src_port_msk
;
1095 struct mlx4_net_trans_rule_hw_ipv4
{
1106 struct mlx4_net_trans_rule_hw_vxlan
{
1122 struct mlx4_net_trans_rule_hw_eth eth
;
1123 struct mlx4_net_trans_rule_hw_ib ib
;
1124 struct mlx4_net_trans_rule_hw_ipv4 ipv4
;
1125 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp
;
1126 struct mlx4_net_trans_rule_hw_vxlan vxlan
;
1131 VXLAN_STEER_BY_OUTER_MAC
= 1 << 0,
1132 VXLAN_STEER_BY_OUTER_VLAN
= 1 << 1,
1133 VXLAN_STEER_BY_VSID_VNI
= 1 << 2,
1134 VXLAN_STEER_BY_INNER_MAC
= 1 << 3,
1135 VXLAN_STEER_BY_INNER_VLAN
= 1 << 4,
1139 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
1140 enum mlx4_net_trans_promisc_mode mode
);
1141 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
1142 enum mlx4_net_trans_promisc_mode mode
);
1143 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1144 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1145 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1146 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1147 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
1149 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1150 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1151 int mlx4_get_base_qpn(struct mlx4_dev
*dev
, u8 port
);
1152 int __mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
1153 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
1154 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
1155 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
1156 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
1158 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
1159 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
1160 u8
*pg
, u16
*ratelimit
);
1161 int mlx4_SET_PORT_VXLAN(struct mlx4_dev
*dev
, u8 port
, u8 steering
, int enable
);
1162 int mlx4_find_cached_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *idx
);
1163 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
1164 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
1165 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
);
1167 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
1168 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
1169 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
1170 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
1171 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1172 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
1173 u32
*lkey
, u32
*rkey
);
1174 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1175 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
1176 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
1177 int mlx4_assign_eq(struct mlx4_dev
*dev
, char *name
, struct cpu_rmap
*rmap
,
1179 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
1181 int mlx4_eq_get_irq(struct mlx4_dev
*dev
, int vec
);
1183 int mlx4_get_phys_port_id(struct mlx4_dev
*dev
);
1184 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
1185 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
1187 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
1188 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
1190 int mlx4_flow_attach(struct mlx4_dev
*dev
,
1191 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
1192 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
1193 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev
*dev
,
1194 enum mlx4_net_trans_promisc_mode flow_type
);
1195 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev
*dev
,
1196 enum mlx4_net_trans_rule_id id
);
1197 int mlx4_hw_rule_sz(struct mlx4_dev
*dev
, enum mlx4_net_trans_rule_id id
);
1199 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
,
1202 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
);
1204 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
);
1205 int mlx4_gen_pkey_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1206 int mlx4_gen_guid_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1207 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev
*dev
, u8 port
, int attr
);
1208 int mlx4_gen_port_state_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
, u8 port_subtype_change
);
1209 enum slave_port_state
mlx4_get_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
);
1210 int set_and_calc_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
, int event
, enum slave_port_gen_event
*gen_event
);
1212 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
);
1213 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
);
1215 int mlx4_get_slave_from_roce_gid(struct mlx4_dev
*dev
, int port
, u8
*gid
,
1217 int mlx4_get_roce_gid_from_slave(struct mlx4_dev
*dev
, int port
, int slave_id
,
1220 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev
*dev
, u32 min_range_qpn
,
1223 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
);
1225 struct mlx4_active_ports
{
1226 DECLARE_BITMAP(ports
, MLX4_MAX_PORTS
);
1228 /* Returns a bitmap of the physical ports which are assigned to slave */
1229 struct mlx4_active_ports
mlx4_get_active_ports(struct mlx4_dev
*dev
, int slave
);
1231 /* Returns the physical port that represents the virtual port of the slave, */
1232 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1233 /* mapping is returned. */
1234 int mlx4_slave_convert_port(struct mlx4_dev
*dev
, int slave
, int port
);
1236 struct mlx4_slaves_pport
{
1237 DECLARE_BITMAP(slaves
, MLX4_MFUNC_MAX
);
1239 /* Returns a bitmap of all slaves that are assigned to port. */
1240 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport(struct mlx4_dev
*dev
,
1243 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1244 /* the ports that are set in crit_ports. */
1245 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport_actv(
1246 struct mlx4_dev
*dev
,
1247 const struct mlx4_active_ports
*crit_ports
);
1249 /* Returns the slave's virtual port that represents the physical port. */
1250 int mlx4_phys_to_slave_port(struct mlx4_dev
*dev
, int slave
, int port
);
1252 int mlx4_get_base_gid_ix(struct mlx4_dev
*dev
, int slave
, int port
);
1254 int mlx4_config_vxlan_port(struct mlx4_dev
*dev
, __be16 udp_port
);
1255 int mlx4_vf_smi_enabled(struct mlx4_dev
*dev
, int slave
, int port
);
1256 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
);
1257 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
,
1259 int mlx4_mr_hw_get_mpt(struct mlx4_dev
*dev
, struct mlx4_mr
*mmr
,
1260 struct mlx4_mpt_entry
***mpt_entry
);
1261 int mlx4_mr_hw_write_mpt(struct mlx4_dev
*dev
, struct mlx4_mr
*mmr
,
1262 struct mlx4_mpt_entry
**mpt_entry
);
1263 int mlx4_mr_hw_change_pd(struct mlx4_dev
*dev
, struct mlx4_mpt_entry
*mpt_entry
,
1265 int mlx4_mr_hw_change_access(struct mlx4_dev
*dev
,
1266 struct mlx4_mpt_entry
*mpt_entry
,
1268 void mlx4_mr_hw_put_mpt(struct mlx4_dev
*dev
,
1269 struct mlx4_mpt_entry
**mpt_entry
);
1270 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
1271 int mlx4_mr_rereg_mem_write(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
,
1272 u64 iova
, u64 size
, int npages
,
1273 int page_shift
, struct mlx4_mpt_entry
*mpt_entry
);
1275 /* Returns true if running in low memory profile (kdump kernel) */
1276 static inline bool mlx4_low_memory_profile(void)
1278 return reset_devices
;
1281 #endif /* MLX4_DEVICE_H */