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Merge tag 'master-2014-09-04' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[mirror_ubuntu-zesty-kernel.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41
42 #include <linux/atomic.h>
43
44 #include <linux/clocksource.h>
45
46 #define MAX_MSIX_P_PORT 17
47 #define MAX_MSIX 64
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
50
51 #define MLX4_NUM_UP 8
52 #define MLX4_NUM_TC 8
53 #define MLX4_MAX_100M_UNITS_VAL 255 /*
54 * work around: can't set values
55 * greater then this value when
56 * using 100 Mbps units.
57 */
58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
60 #define MLX4_RATELIMIT_DEFAULT 0x00ff
61
62 #define MLX4_ROCE_MAX_GIDS 128
63 #define MLX4_ROCE_PF_GIDS 16
64
65 enum {
66 MLX4_FLAG_MSI_X = 1 << 0,
67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
68 MLX4_FLAG_MASTER = 1 << 2,
69 MLX4_FLAG_SLAVE = 1 << 3,
70 MLX4_FLAG_SRIOV = 1 << 4,
71 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
72 };
73
74 enum {
75 MLX4_PORT_CAP_IS_SM = 1 << 1,
76 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
77 };
78
79 enum {
80 MLX4_MAX_PORTS = 2,
81 MLX4_MAX_PORT_PKEYS = 128
82 };
83
84 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
85 * These qkeys must not be allowed for general use. This is a 64k range,
86 * and to test for violation, we use the mask (protect against future chg).
87 */
88 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
89 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
90
91 enum {
92 MLX4_BOARD_ID_LEN = 64
93 };
94
95 enum {
96 MLX4_MAX_NUM_PF = 16,
97 MLX4_MAX_NUM_VF = 64,
98 MLX4_MAX_NUM_VF_P_PORT = 64,
99 MLX4_MFUNC_MAX = 80,
100 MLX4_MAX_EQ_NUM = 1024,
101 MLX4_MFUNC_EQ_NUM = 4,
102 MLX4_MFUNC_MAX_EQES = 8,
103 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
104 };
105
106 /* Driver supports 3 diffrent device methods to manage traffic steering:
107 * -device managed - High level API for ib and eth flow steering. FW is
108 * managing flow steering tables.
109 * - B0 steering mode - Common low level API for ib and (if supported) eth.
110 * - A0 steering mode - Limited low level API for eth. In case of IB,
111 * B0 mode is in use.
112 */
113 enum {
114 MLX4_STEERING_MODE_A0,
115 MLX4_STEERING_MODE_B0,
116 MLX4_STEERING_MODE_DEVICE_MANAGED
117 };
118
119 static inline const char *mlx4_steering_mode_str(int steering_mode)
120 {
121 switch (steering_mode) {
122 case MLX4_STEERING_MODE_A0:
123 return "A0 steering";
124
125 case MLX4_STEERING_MODE_B0:
126 return "B0 steering";
127
128 case MLX4_STEERING_MODE_DEVICE_MANAGED:
129 return "Device managed flow steering";
130
131 default:
132 return "Unrecognize steering mode";
133 }
134 }
135
136 enum {
137 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
138 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
139 };
140
141 enum {
142 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
143 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
144 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
145 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
146 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
147 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
148 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
149 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
150 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
151 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
152 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
153 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
154 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
155 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
156 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
157 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
158 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
159 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
160 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
161 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
162 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
163 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
164 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
165 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
166 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
167 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
169 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
170 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
171 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
172 };
173
174 enum {
175 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
176 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
177 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
178 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
179 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
180 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
182 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
183 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
185 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
186 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
187 };
188
189 enum {
190 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
191 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
192 };
193
194 enum {
195 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
196 };
197
198 enum {
199 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
200 };
201
202
203 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
204
205 enum {
206 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
207 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
208 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
209 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
210 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
211 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
212 };
213
214 enum mlx4_event {
215 MLX4_EVENT_TYPE_COMP = 0x00,
216 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
217 MLX4_EVENT_TYPE_COMM_EST = 0x02,
218 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
219 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
220 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
221 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
222 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
223 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
224 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
225 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
226 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
227 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
228 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
229 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
230 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
231 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
232 MLX4_EVENT_TYPE_CMD = 0x0a,
233 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
234 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
235 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
236 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
237 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
238 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
239 MLX4_EVENT_TYPE_NONE = 0xff,
240 };
241
242 enum {
243 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
244 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
245 };
246
247 enum {
248 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
249 };
250
251 enum slave_port_state {
252 SLAVE_PORT_DOWN = 0,
253 SLAVE_PENDING_UP,
254 SLAVE_PORT_UP,
255 };
256
257 enum slave_port_gen_event {
258 SLAVE_PORT_GEN_EVENT_DOWN = 0,
259 SLAVE_PORT_GEN_EVENT_UP,
260 SLAVE_PORT_GEN_EVENT_NONE,
261 };
262
263 enum slave_port_state_event {
264 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
265 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
266 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
267 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
268 };
269
270 enum {
271 MLX4_PERM_LOCAL_READ = 1 << 10,
272 MLX4_PERM_LOCAL_WRITE = 1 << 11,
273 MLX4_PERM_REMOTE_READ = 1 << 12,
274 MLX4_PERM_REMOTE_WRITE = 1 << 13,
275 MLX4_PERM_ATOMIC = 1 << 14,
276 MLX4_PERM_BIND_MW = 1 << 15,
277 MLX4_PERM_MASK = 0xFC00
278 };
279
280 enum {
281 MLX4_OPCODE_NOP = 0x00,
282 MLX4_OPCODE_SEND_INVAL = 0x01,
283 MLX4_OPCODE_RDMA_WRITE = 0x08,
284 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
285 MLX4_OPCODE_SEND = 0x0a,
286 MLX4_OPCODE_SEND_IMM = 0x0b,
287 MLX4_OPCODE_LSO = 0x0e,
288 MLX4_OPCODE_RDMA_READ = 0x10,
289 MLX4_OPCODE_ATOMIC_CS = 0x11,
290 MLX4_OPCODE_ATOMIC_FA = 0x12,
291 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
292 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
293 MLX4_OPCODE_BIND_MW = 0x18,
294 MLX4_OPCODE_FMR = 0x19,
295 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
296 MLX4_OPCODE_CONFIG_CMD = 0x1f,
297
298 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
299 MLX4_RECV_OPCODE_SEND = 0x01,
300 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
301 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
302
303 MLX4_CQE_OPCODE_ERROR = 0x1e,
304 MLX4_CQE_OPCODE_RESIZE = 0x16,
305 };
306
307 enum {
308 MLX4_STAT_RATE_OFFSET = 5
309 };
310
311 enum mlx4_protocol {
312 MLX4_PROT_IB_IPV6 = 0,
313 MLX4_PROT_ETH,
314 MLX4_PROT_IB_IPV4,
315 MLX4_PROT_FCOE
316 };
317
318 enum {
319 MLX4_MTT_FLAG_PRESENT = 1
320 };
321
322 enum mlx4_qp_region {
323 MLX4_QP_REGION_FW = 0,
324 MLX4_QP_REGION_ETH_ADDR,
325 MLX4_QP_REGION_FC_ADDR,
326 MLX4_QP_REGION_FC_EXCH,
327 MLX4_NUM_QP_REGION
328 };
329
330 enum mlx4_port_type {
331 MLX4_PORT_TYPE_NONE = 0,
332 MLX4_PORT_TYPE_IB = 1,
333 MLX4_PORT_TYPE_ETH = 2,
334 MLX4_PORT_TYPE_AUTO = 3
335 };
336
337 enum mlx4_special_vlan_idx {
338 MLX4_NO_VLAN_IDX = 0,
339 MLX4_VLAN_MISS_IDX,
340 MLX4_VLAN_REGULAR
341 };
342
343 enum mlx4_steer_type {
344 MLX4_MC_STEER = 0,
345 MLX4_UC_STEER,
346 MLX4_NUM_STEERS
347 };
348
349 enum {
350 MLX4_NUM_FEXCH = 64 * 1024,
351 };
352
353 enum {
354 MLX4_MAX_FAST_REG_PAGES = 511,
355 };
356
357 enum {
358 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
359 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
360 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
361 };
362
363 /* Port mgmt change event handling */
364 enum {
365 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
366 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
367 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
368 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
369 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
370 };
371
372 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
373 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
374
375 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
376 {
377 return (major << 32) | (minor << 16) | subminor;
378 }
379
380 struct mlx4_phys_caps {
381 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
382 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
383 u32 num_phys_eqs;
384 u32 base_sqpn;
385 u32 base_proxy_sqpn;
386 u32 base_tunnel_sqpn;
387 };
388
389 struct mlx4_caps {
390 u64 fw_ver;
391 u32 function;
392 int num_ports;
393 int vl_cap[MLX4_MAX_PORTS + 1];
394 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
395 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
396 u64 def_mac[MLX4_MAX_PORTS + 1];
397 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
398 int gid_table_len[MLX4_MAX_PORTS + 1];
399 int pkey_table_len[MLX4_MAX_PORTS + 1];
400 int trans_type[MLX4_MAX_PORTS + 1];
401 int vendor_oui[MLX4_MAX_PORTS + 1];
402 int wavelength[MLX4_MAX_PORTS + 1];
403 u64 trans_code[MLX4_MAX_PORTS + 1];
404 int local_ca_ack_delay;
405 int num_uars;
406 u32 uar_page_size;
407 int bf_reg_size;
408 int bf_regs_per_page;
409 int max_sq_sg;
410 int max_rq_sg;
411 int num_qps;
412 int max_wqes;
413 int max_sq_desc_sz;
414 int max_rq_desc_sz;
415 int max_qp_init_rdma;
416 int max_qp_dest_rdma;
417 u32 *qp0_qkey;
418 u32 *qp0_proxy;
419 u32 *qp1_proxy;
420 u32 *qp0_tunnel;
421 u32 *qp1_tunnel;
422 int num_srqs;
423 int max_srq_wqes;
424 int max_srq_sge;
425 int reserved_srqs;
426 int num_cqs;
427 int max_cqes;
428 int reserved_cqs;
429 int num_eqs;
430 int reserved_eqs;
431 int num_comp_vectors;
432 int comp_pool;
433 int num_mpts;
434 int max_fmr_maps;
435 int num_mtts;
436 int fmr_reserved_mtts;
437 int reserved_mtts;
438 int reserved_mrws;
439 int reserved_uars;
440 int num_mgms;
441 int num_amgms;
442 int reserved_mcgs;
443 int num_qp_per_mgm;
444 int steering_mode;
445 int fs_log_max_ucast_qp_range_size;
446 int num_pds;
447 int reserved_pds;
448 int max_xrcds;
449 int reserved_xrcds;
450 int mtt_entry_sz;
451 u32 max_msg_sz;
452 u32 page_size_cap;
453 u64 flags;
454 u64 flags2;
455 u32 bmme_flags;
456 u32 reserved_lkey;
457 u16 stat_rate_support;
458 u8 port_width_cap[MLX4_MAX_PORTS + 1];
459 int max_gso_sz;
460 int max_rss_tbl_sz;
461 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
462 int reserved_qps;
463 int reserved_qps_base[MLX4_NUM_QP_REGION];
464 int log_num_macs;
465 int log_num_vlans;
466 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
467 u8 supported_type[MLX4_MAX_PORTS + 1];
468 u8 suggested_type[MLX4_MAX_PORTS + 1];
469 u8 default_sense[MLX4_MAX_PORTS + 1];
470 u32 port_mask[MLX4_MAX_PORTS + 1];
471 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
472 u32 max_counters;
473 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
474 u16 sqp_demux;
475 u32 eqe_size;
476 u32 cqe_size;
477 u8 eqe_factor;
478 u32 userspace_caps; /* userspace must be aware of these */
479 u32 function_caps; /* VFs must be aware of these */
480 u16 hca_core_clock;
481 u64 phys_port_id[MLX4_MAX_PORTS + 1];
482 int tunnel_offload_mode;
483 };
484
485 struct mlx4_buf_list {
486 void *buf;
487 dma_addr_t map;
488 };
489
490 struct mlx4_buf {
491 struct mlx4_buf_list direct;
492 struct mlx4_buf_list *page_list;
493 int nbufs;
494 int npages;
495 int page_shift;
496 };
497
498 struct mlx4_mtt {
499 u32 offset;
500 int order;
501 int page_shift;
502 };
503
504 enum {
505 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
506 };
507
508 struct mlx4_db_pgdir {
509 struct list_head list;
510 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
511 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
512 unsigned long *bits[2];
513 __be32 *db_page;
514 dma_addr_t db_dma;
515 };
516
517 struct mlx4_ib_user_db_page;
518
519 struct mlx4_db {
520 __be32 *db;
521 union {
522 struct mlx4_db_pgdir *pgdir;
523 struct mlx4_ib_user_db_page *user_page;
524 } u;
525 dma_addr_t dma;
526 int index;
527 int order;
528 };
529
530 struct mlx4_hwq_resources {
531 struct mlx4_db db;
532 struct mlx4_mtt mtt;
533 struct mlx4_buf buf;
534 };
535
536 struct mlx4_mr {
537 struct mlx4_mtt mtt;
538 u64 iova;
539 u64 size;
540 u32 key;
541 u32 pd;
542 u32 access;
543 int enabled;
544 };
545
546 enum mlx4_mw_type {
547 MLX4_MW_TYPE_1 = 1,
548 MLX4_MW_TYPE_2 = 2,
549 };
550
551 struct mlx4_mw {
552 u32 key;
553 u32 pd;
554 enum mlx4_mw_type type;
555 int enabled;
556 };
557
558 struct mlx4_fmr {
559 struct mlx4_mr mr;
560 struct mlx4_mpt_entry *mpt;
561 __be64 *mtts;
562 dma_addr_t dma_handle;
563 int max_pages;
564 int max_maps;
565 int maps;
566 u8 page_shift;
567 };
568
569 struct mlx4_uar {
570 unsigned long pfn;
571 int index;
572 struct list_head bf_list;
573 unsigned free_bf_bmap;
574 void __iomem *map;
575 void __iomem *bf_map;
576 };
577
578 struct mlx4_bf {
579 unsigned long offset;
580 int buf_size;
581 struct mlx4_uar *uar;
582 void __iomem *reg;
583 };
584
585 struct mlx4_cq {
586 void (*comp) (struct mlx4_cq *);
587 void (*event) (struct mlx4_cq *, enum mlx4_event);
588
589 struct mlx4_uar *uar;
590
591 u32 cons_index;
592
593 u16 irq;
594 __be32 *set_ci_db;
595 __be32 *arm_db;
596 int arm_sn;
597
598 int cqn;
599 unsigned vector;
600
601 atomic_t refcount;
602 struct completion free;
603 };
604
605 struct mlx4_qp {
606 void (*event) (struct mlx4_qp *, enum mlx4_event);
607
608 int qpn;
609
610 atomic_t refcount;
611 struct completion free;
612 };
613
614 struct mlx4_srq {
615 void (*event) (struct mlx4_srq *, enum mlx4_event);
616
617 int srqn;
618 int max;
619 int max_gs;
620 int wqe_shift;
621
622 atomic_t refcount;
623 struct completion free;
624 };
625
626 struct mlx4_av {
627 __be32 port_pd;
628 u8 reserved1;
629 u8 g_slid;
630 __be16 dlid;
631 u8 reserved2;
632 u8 gid_index;
633 u8 stat_rate;
634 u8 hop_limit;
635 __be32 sl_tclass_flowlabel;
636 u8 dgid[16];
637 };
638
639 struct mlx4_eth_av {
640 __be32 port_pd;
641 u8 reserved1;
642 u8 smac_idx;
643 u16 reserved2;
644 u8 reserved3;
645 u8 gid_index;
646 u8 stat_rate;
647 u8 hop_limit;
648 __be32 sl_tclass_flowlabel;
649 u8 dgid[16];
650 u8 s_mac[6];
651 u8 reserved4[2];
652 __be16 vlan;
653 u8 mac[ETH_ALEN];
654 };
655
656 union mlx4_ext_av {
657 struct mlx4_av ib;
658 struct mlx4_eth_av eth;
659 };
660
661 struct mlx4_counter {
662 u8 reserved1[3];
663 u8 counter_mode;
664 __be32 num_ifc;
665 u32 reserved2[2];
666 __be64 rx_frames;
667 __be64 rx_bytes;
668 __be64 tx_frames;
669 __be64 tx_bytes;
670 };
671
672 struct mlx4_quotas {
673 int qp;
674 int cq;
675 int srq;
676 int mpt;
677 int mtt;
678 int counter;
679 int xrcd;
680 };
681
682 struct mlx4_vf_dev {
683 u8 min_port;
684 u8 n_ports;
685 };
686
687 struct mlx4_dev {
688 struct pci_dev *pdev;
689 unsigned long flags;
690 unsigned long num_slaves;
691 struct mlx4_caps caps;
692 struct mlx4_phys_caps phys_caps;
693 struct mlx4_quotas quotas;
694 struct radix_tree_root qp_table_tree;
695 u8 rev_id;
696 char board_id[MLX4_BOARD_ID_LEN];
697 int num_vfs;
698 int numa_node;
699 int oper_log_mgm_entry_size;
700 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
701 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
702 struct mlx4_vf_dev *dev_vfs;
703 };
704
705 struct mlx4_eqe {
706 u8 reserved1;
707 u8 type;
708 u8 reserved2;
709 u8 subtype;
710 union {
711 u32 raw[6];
712 struct {
713 __be32 cqn;
714 } __packed comp;
715 struct {
716 u16 reserved1;
717 __be16 token;
718 u32 reserved2;
719 u8 reserved3[3];
720 u8 status;
721 __be64 out_param;
722 } __packed cmd;
723 struct {
724 __be32 qpn;
725 } __packed qp;
726 struct {
727 __be32 srqn;
728 } __packed srq;
729 struct {
730 __be32 cqn;
731 u32 reserved1;
732 u8 reserved2[3];
733 u8 syndrome;
734 } __packed cq_err;
735 struct {
736 u32 reserved1[2];
737 __be32 port;
738 } __packed port_change;
739 struct {
740 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
741 u32 reserved;
742 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
743 } __packed comm_channel_arm;
744 struct {
745 u8 port;
746 u8 reserved[3];
747 __be64 mac;
748 } __packed mac_update;
749 struct {
750 __be32 slave_id;
751 } __packed flr_event;
752 struct {
753 __be16 current_temperature;
754 __be16 warning_threshold;
755 } __packed warming;
756 struct {
757 u8 reserved[3];
758 u8 port;
759 union {
760 struct {
761 __be16 mstr_sm_lid;
762 __be16 port_lid;
763 __be32 changed_attr;
764 u8 reserved[3];
765 u8 mstr_sm_sl;
766 __be64 gid_prefix;
767 } __packed port_info;
768 struct {
769 __be32 block_ptr;
770 __be32 tbl_entries_mask;
771 } __packed tbl_change_info;
772 } params;
773 } __packed port_mgmt_change;
774 } event;
775 u8 slave_id;
776 u8 reserved3[2];
777 u8 owner;
778 } __packed;
779
780 struct mlx4_init_port_param {
781 int set_guid0;
782 int set_node_guid;
783 int set_si_guid;
784 u16 mtu;
785 int port_width_cap;
786 u16 vl_cap;
787 u16 max_gid;
788 u16 max_pkey;
789 u64 guid0;
790 u64 node_guid;
791 u64 si_guid;
792 };
793
794 #define mlx4_foreach_port(port, dev, type) \
795 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
796 if ((type) == (dev)->caps.port_mask[(port)])
797
798 #define mlx4_foreach_non_ib_transport_port(port, dev) \
799 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
800 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
801
802 #define mlx4_foreach_ib_transport_port(port, dev) \
803 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
804 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
805 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
806
807 #define MLX4_INVALID_SLAVE_ID 0xFF
808
809 void handle_port_mgmt_change_event(struct work_struct *work);
810
811 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
812 {
813 return dev->caps.function;
814 }
815
816 static inline int mlx4_is_master(struct mlx4_dev *dev)
817 {
818 return dev->flags & MLX4_FLAG_MASTER;
819 }
820
821 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
822 {
823 return dev->phys_caps.base_sqpn + 8 +
824 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
825 }
826
827 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
828 {
829 return (qpn < dev->phys_caps.base_sqpn + 8 +
830 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
831 }
832
833 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
834 {
835 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
836
837 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
838 return 1;
839
840 return 0;
841 }
842
843 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
844 {
845 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
846 }
847
848 static inline int mlx4_is_slave(struct mlx4_dev *dev)
849 {
850 return dev->flags & MLX4_FLAG_SLAVE;
851 }
852
853 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
854 struct mlx4_buf *buf, gfp_t gfp);
855 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
856 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
857 {
858 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
859 return buf->direct.buf + offset;
860 else
861 return buf->page_list[offset >> PAGE_SHIFT].buf +
862 (offset & (PAGE_SIZE - 1));
863 }
864
865 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
866 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
867 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
868 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
869
870 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
871 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
872 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
873 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
874
875 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
876 struct mlx4_mtt *mtt);
877 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
878 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
879
880 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
881 int npages, int page_shift, struct mlx4_mr *mr);
882 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
883 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
884 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
885 struct mlx4_mw *mw);
886 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
887 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
888 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
889 int start_index, int npages, u64 *page_list);
890 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
891 struct mlx4_buf *buf, gfp_t gfp);
892
893 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
894 gfp_t gfp);
895 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
896
897 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
898 int size, int max_direct);
899 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
900 int size);
901
902 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
903 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
904 unsigned vector, int collapsed, int timestamp_en);
905 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
906
907 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
908 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
909
910 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
911 gfp_t gfp);
912 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
913
914 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
915 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
916 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
917 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
918 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
919
920 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
921 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
922
923 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
924 int block_mcast_loopback, enum mlx4_protocol prot);
925 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
926 enum mlx4_protocol prot);
927 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
928 u8 port, int block_mcast_loopback,
929 enum mlx4_protocol protocol, u64 *reg_id);
930 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
931 enum mlx4_protocol protocol, u64 reg_id);
932
933 enum {
934 MLX4_DOMAIN_UVERBS = 0x1000,
935 MLX4_DOMAIN_ETHTOOL = 0x2000,
936 MLX4_DOMAIN_RFS = 0x3000,
937 MLX4_DOMAIN_NIC = 0x5000,
938 };
939
940 enum mlx4_net_trans_rule_id {
941 MLX4_NET_TRANS_RULE_ID_ETH = 0,
942 MLX4_NET_TRANS_RULE_ID_IB,
943 MLX4_NET_TRANS_RULE_ID_IPV6,
944 MLX4_NET_TRANS_RULE_ID_IPV4,
945 MLX4_NET_TRANS_RULE_ID_TCP,
946 MLX4_NET_TRANS_RULE_ID_UDP,
947 MLX4_NET_TRANS_RULE_ID_VXLAN,
948 MLX4_NET_TRANS_RULE_NUM, /* should be last */
949 };
950
951 extern const u16 __sw_id_hw[];
952
953 static inline int map_hw_to_sw_id(u16 header_id)
954 {
955
956 int i;
957 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
958 if (header_id == __sw_id_hw[i])
959 return i;
960 }
961 return -EINVAL;
962 }
963
964 enum mlx4_net_trans_promisc_mode {
965 MLX4_FS_REGULAR = 1,
966 MLX4_FS_ALL_DEFAULT,
967 MLX4_FS_MC_DEFAULT,
968 MLX4_FS_UC_SNIFFER,
969 MLX4_FS_MC_SNIFFER,
970 MLX4_FS_MODE_NUM, /* should be last */
971 };
972
973 struct mlx4_spec_eth {
974 u8 dst_mac[ETH_ALEN];
975 u8 dst_mac_msk[ETH_ALEN];
976 u8 src_mac[ETH_ALEN];
977 u8 src_mac_msk[ETH_ALEN];
978 u8 ether_type_enable;
979 __be16 ether_type;
980 __be16 vlan_id_msk;
981 __be16 vlan_id;
982 };
983
984 struct mlx4_spec_tcp_udp {
985 __be16 dst_port;
986 __be16 dst_port_msk;
987 __be16 src_port;
988 __be16 src_port_msk;
989 };
990
991 struct mlx4_spec_ipv4 {
992 __be32 dst_ip;
993 __be32 dst_ip_msk;
994 __be32 src_ip;
995 __be32 src_ip_msk;
996 };
997
998 struct mlx4_spec_ib {
999 __be32 l3_qpn;
1000 __be32 qpn_msk;
1001 u8 dst_gid[16];
1002 u8 dst_gid_msk[16];
1003 };
1004
1005 struct mlx4_spec_vxlan {
1006 __be32 vni;
1007 __be32 vni_mask;
1008
1009 };
1010
1011 struct mlx4_spec_list {
1012 struct list_head list;
1013 enum mlx4_net_trans_rule_id id;
1014 union {
1015 struct mlx4_spec_eth eth;
1016 struct mlx4_spec_ib ib;
1017 struct mlx4_spec_ipv4 ipv4;
1018 struct mlx4_spec_tcp_udp tcp_udp;
1019 struct mlx4_spec_vxlan vxlan;
1020 };
1021 };
1022
1023 enum mlx4_net_trans_hw_rule_queue {
1024 MLX4_NET_TRANS_Q_FIFO,
1025 MLX4_NET_TRANS_Q_LIFO,
1026 };
1027
1028 struct mlx4_net_trans_rule {
1029 struct list_head list;
1030 enum mlx4_net_trans_hw_rule_queue queue_mode;
1031 bool exclusive;
1032 bool allow_loopback;
1033 enum mlx4_net_trans_promisc_mode promisc_mode;
1034 u8 port;
1035 u16 priority;
1036 u32 qpn;
1037 };
1038
1039 struct mlx4_net_trans_rule_hw_ctrl {
1040 __be16 prio;
1041 u8 type;
1042 u8 flags;
1043 u8 rsvd1;
1044 u8 funcid;
1045 u8 vep;
1046 u8 port;
1047 __be32 qpn;
1048 __be32 rsvd2;
1049 };
1050
1051 struct mlx4_net_trans_rule_hw_ib {
1052 u8 size;
1053 u8 rsvd1;
1054 __be16 id;
1055 u32 rsvd2;
1056 __be32 l3_qpn;
1057 __be32 qpn_mask;
1058 u8 dst_gid[16];
1059 u8 dst_gid_msk[16];
1060 } __packed;
1061
1062 struct mlx4_net_trans_rule_hw_eth {
1063 u8 size;
1064 u8 rsvd;
1065 __be16 id;
1066 u8 rsvd1[6];
1067 u8 dst_mac[6];
1068 u16 rsvd2;
1069 u8 dst_mac_msk[6];
1070 u16 rsvd3;
1071 u8 src_mac[6];
1072 u16 rsvd4;
1073 u8 src_mac_msk[6];
1074 u8 rsvd5;
1075 u8 ether_type_enable;
1076 __be16 ether_type;
1077 __be16 vlan_tag_msk;
1078 __be16 vlan_tag;
1079 } __packed;
1080
1081 struct mlx4_net_trans_rule_hw_tcp_udp {
1082 u8 size;
1083 u8 rsvd;
1084 __be16 id;
1085 __be16 rsvd1[3];
1086 __be16 dst_port;
1087 __be16 rsvd2;
1088 __be16 dst_port_msk;
1089 __be16 rsvd3;
1090 __be16 src_port;
1091 __be16 rsvd4;
1092 __be16 src_port_msk;
1093 } __packed;
1094
1095 struct mlx4_net_trans_rule_hw_ipv4 {
1096 u8 size;
1097 u8 rsvd;
1098 __be16 id;
1099 __be32 rsvd1;
1100 __be32 dst_ip;
1101 __be32 dst_ip_msk;
1102 __be32 src_ip;
1103 __be32 src_ip_msk;
1104 } __packed;
1105
1106 struct mlx4_net_trans_rule_hw_vxlan {
1107 u8 size;
1108 u8 rsvd;
1109 __be16 id;
1110 __be32 rsvd1;
1111 __be32 vni;
1112 __be32 vni_mask;
1113 } __packed;
1114
1115 struct _rule_hw {
1116 union {
1117 struct {
1118 u8 size;
1119 u8 rsvd;
1120 __be16 id;
1121 };
1122 struct mlx4_net_trans_rule_hw_eth eth;
1123 struct mlx4_net_trans_rule_hw_ib ib;
1124 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1125 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1126 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1127 };
1128 };
1129
1130 enum {
1131 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1132 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1133 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1134 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1135 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1136 };
1137
1138
1139 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1140 enum mlx4_net_trans_promisc_mode mode);
1141 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1142 enum mlx4_net_trans_promisc_mode mode);
1143 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1144 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1145 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1146 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1147 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1148
1149 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1150 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1151 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1152 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1153 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1154 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1155 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1156 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1157 u8 promisc);
1158 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1159 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1160 u8 *pg, u16 *ratelimit);
1161 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1162 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1163 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1164 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1165 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1166
1167 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1168 int npages, u64 iova, u32 *lkey, u32 *rkey);
1169 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1170 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1171 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1172 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1173 u32 *lkey, u32 *rkey);
1174 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1175 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1176 int mlx4_test_interrupts(struct mlx4_dev *dev);
1177 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1178 int *vector);
1179 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1180
1181 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1182
1183 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1184 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1185 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1186
1187 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1188 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1189
1190 int mlx4_flow_attach(struct mlx4_dev *dev,
1191 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1192 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1193 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1194 enum mlx4_net_trans_promisc_mode flow_type);
1195 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1196 enum mlx4_net_trans_rule_id id);
1197 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1198
1199 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1200 int port, int qpn, u16 prio, u64 *reg_id);
1201
1202 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1203 int i, int val);
1204
1205 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1206
1207 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1208 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1209 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1210 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1211 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1212 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1213 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1214
1215 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1216 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1217
1218 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1219 int *slave_id);
1220 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1221 u8 *gid);
1222
1223 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1224 u32 max_range_qpn);
1225
1226 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1227
1228 struct mlx4_active_ports {
1229 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1230 };
1231 /* Returns a bitmap of the physical ports which are assigned to slave */
1232 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1233
1234 /* Returns the physical port that represents the virtual port of the slave, */
1235 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1236 /* mapping is returned. */
1237 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1238
1239 struct mlx4_slaves_pport {
1240 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1241 };
1242 /* Returns a bitmap of all slaves that are assigned to port. */
1243 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1244 int port);
1245
1246 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1247 /* the ports that are set in crit_ports. */
1248 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1249 struct mlx4_dev *dev,
1250 const struct mlx4_active_ports *crit_ports);
1251
1252 /* Returns the slave's virtual port that represents the physical port. */
1253 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1254
1255 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1256
1257 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1258 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1259 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1260 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1261 int enable);
1262 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1263 struct mlx4_mpt_entry ***mpt_entry);
1264 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1265 struct mlx4_mpt_entry **mpt_entry);
1266 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1267 u32 pdn);
1268 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1269 struct mlx4_mpt_entry *mpt_entry,
1270 u32 access);
1271 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1272 struct mlx4_mpt_entry **mpt_entry);
1273 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1274 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1275 u64 iova, u64 size, int npages,
1276 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1277
1278 /* Returns true if running in low memory profile (kdump kernel) */
1279 static inline bool mlx4_low_memory_profile(void)
1280 {
1281 return reset_devices;
1282 }
1283
1284 #endif /* MLX4_DEVICE_H */
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