2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
43 #include <linux/atomic.h>
45 #include <linux/clocksource.h>
47 #define MAX_MSIX_P_PORT 17
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
67 MLX4_FLAG_MSI_X
= 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
69 MLX4_FLAG_MASTER
= 1 << 2,
70 MLX4_FLAG_SLAVE
= 1 << 3,
71 MLX4_FLAG_SRIOV
= 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC
= 1 << 6,
76 MLX4_PORT_CAP_IS_SM
= 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP
= 1 << 19,
82 MLX4_MAX_PORT_PKEYS
= 128
85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
86 * These qkeys must not be allowed for general use. This is a 64k range,
87 * and to test for violation, we use the mask (protect against future chg).
89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
93 MLX4_BOARD_ID_LEN
= 64
99 MLX4_MAX_NUM_VF_P_PORT
= 64,
101 MLX4_MAX_EQ_NUM
= 1024,
102 MLX4_MFUNC_EQ_NUM
= 4,
103 MLX4_MFUNC_MAX_EQES
= 8,
104 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
107 /* Driver supports 3 diffrent device methods to manage traffic steering:
108 * -device managed - High level API for ib and eth flow steering. FW is
109 * managing flow steering tables.
110 * - B0 steering mode - Common low level API for ib and (if supported) eth.
111 * - A0 steering mode - Limited low level API for eth. In case of IB,
115 MLX4_STEERING_MODE_A0
,
116 MLX4_STEERING_MODE_B0
,
117 MLX4_STEERING_MODE_DEVICE_MANAGED
120 static inline const char *mlx4_steering_mode_str(int steering_mode
)
122 switch (steering_mode
) {
123 case MLX4_STEERING_MODE_A0
:
124 return "A0 steering";
126 case MLX4_STEERING_MODE_B0
:
127 return "B0 steering";
129 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
130 return "Device managed flow steering";
133 return "Unrecognize steering mode";
138 MLX4_TUNNEL_OFFLOAD_MODE_NONE
,
139 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
143 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
144 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
145 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
146 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
147 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
148 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
149 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
150 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
151 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
152 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
153 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
154 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
155 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
156 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
157 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
158 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
159 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
160 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
161 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
162 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
163 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
164 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
165 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
166 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
167 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
168 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED
= 1LL << 53,
169 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55,
170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
= 1LL << 59,
171 MLX4_DEV_CAP_FLAG_64B_EQE
= 1LL << 61,
172 MLX4_DEV_CAP_FLAG_64B_CQE
= 1LL << 62
176 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
177 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
178 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
179 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3,
180 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
= 1LL << 4,
181 MLX4_DEV_CAP_FLAG2_TS
= 1LL << 5,
182 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
= 1LL << 6,
183 MLX4_DEV_CAP_FLAG2_FSM
= 1LL << 7,
184 MLX4_DEV_CAP_FLAG2_UPDATE_QP
= 1LL << 8,
185 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB
= 1LL << 9,
186 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
= 1LL << 10,
187 MLX4_DEV_CAP_FLAG2_MAD_DEMUX
= 1LL << 11,
191 MLX4_DEV_CAP_64B_EQE_ENABLED
= 1LL << 0,
192 MLX4_DEV_CAP_64B_CQE_ENABLED
= 1LL << 1
196 MLX4_USER_DEV_CAP_64B_CQE
= 1L << 0
200 MLX4_FUNC_CAP_64B_EQE_CQE
= 1L << 0
204 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
207 MLX4_BMME_FLAG_WIN_TYPE_2B
= 1 << 1,
208 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
209 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
210 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
211 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
212 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
216 MLX4_EVENT_TYPE_COMP
= 0x00,
217 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
218 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
219 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
220 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
221 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
222 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
223 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
224 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
225 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
226 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
227 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
228 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
229 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
230 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
231 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
232 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
233 MLX4_EVENT_TYPE_CMD
= 0x0a,
234 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
235 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
236 MLX4_EVENT_TYPE_OP_REQUIRED
= 0x1a,
237 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
238 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
239 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT
= 0x1d,
240 MLX4_EVENT_TYPE_NONE
= 0xff,
244 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
245 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
249 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
252 enum slave_port_state
{
258 enum slave_port_gen_event
{
259 SLAVE_PORT_GEN_EVENT_DOWN
= 0,
260 SLAVE_PORT_GEN_EVENT_UP
,
261 SLAVE_PORT_GEN_EVENT_NONE
,
264 enum slave_port_state_event
{
265 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN
,
266 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
,
267 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID
,
268 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
,
272 MLX4_PERM_LOCAL_READ
= 1 << 10,
273 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
274 MLX4_PERM_REMOTE_READ
= 1 << 12,
275 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
276 MLX4_PERM_ATOMIC
= 1 << 14,
277 MLX4_PERM_BIND_MW
= 1 << 15,
278 MLX4_PERM_MASK
= 0xFC00
282 MLX4_OPCODE_NOP
= 0x00,
283 MLX4_OPCODE_SEND_INVAL
= 0x01,
284 MLX4_OPCODE_RDMA_WRITE
= 0x08,
285 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
286 MLX4_OPCODE_SEND
= 0x0a,
287 MLX4_OPCODE_SEND_IMM
= 0x0b,
288 MLX4_OPCODE_LSO
= 0x0e,
289 MLX4_OPCODE_RDMA_READ
= 0x10,
290 MLX4_OPCODE_ATOMIC_CS
= 0x11,
291 MLX4_OPCODE_ATOMIC_FA
= 0x12,
292 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
293 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
294 MLX4_OPCODE_BIND_MW
= 0x18,
295 MLX4_OPCODE_FMR
= 0x19,
296 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
297 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
299 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
300 MLX4_RECV_OPCODE_SEND
= 0x01,
301 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
302 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
304 MLX4_CQE_OPCODE_ERROR
= 0x1e,
305 MLX4_CQE_OPCODE_RESIZE
= 0x16,
309 MLX4_STAT_RATE_OFFSET
= 5
313 MLX4_PROT_IB_IPV6
= 0,
320 MLX4_MTT_FLAG_PRESENT
= 1
323 enum mlx4_qp_region
{
324 MLX4_QP_REGION_FW
= 0,
325 MLX4_QP_REGION_ETH_ADDR
,
326 MLX4_QP_REGION_FC_ADDR
,
327 MLX4_QP_REGION_FC_EXCH
,
331 enum mlx4_port_type
{
332 MLX4_PORT_TYPE_NONE
= 0,
333 MLX4_PORT_TYPE_IB
= 1,
334 MLX4_PORT_TYPE_ETH
= 2,
335 MLX4_PORT_TYPE_AUTO
= 3
338 enum mlx4_special_vlan_idx
{
339 MLX4_NO_VLAN_IDX
= 0,
344 enum mlx4_steer_type
{
351 MLX4_NUM_FEXCH
= 64 * 1024,
355 MLX4_MAX_FAST_REG_PAGES
= 511,
359 MLX4_DEV_PMC_SUBTYPE_GUID_INFO
= 0x14,
360 MLX4_DEV_PMC_SUBTYPE_PORT_INFO
= 0x15,
361 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE
= 0x16,
364 /* Port mgmt change event handling */
366 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK
= 1 << 0,
367 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK
= 1 << 1,
368 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK
= 1 << 2,
369 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK
= 1 << 3,
370 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK
= 1 << 4,
373 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
374 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
376 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
378 return (major
<< 32) | (minor
<< 16) | subminor
;
381 struct mlx4_phys_caps
{
382 u32 gid_phys_table_len
[MLX4_MAX_PORTS
+ 1];
383 u32 pkey_phys_table_len
[MLX4_MAX_PORTS
+ 1];
387 u32 base_tunnel_sqpn
;
394 int vl_cap
[MLX4_MAX_PORTS
+ 1];
395 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
396 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
397 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
398 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
399 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
400 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
401 int trans_type
[MLX4_MAX_PORTS
+ 1];
402 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
403 int wavelength
[MLX4_MAX_PORTS
+ 1];
404 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
405 int local_ca_ack_delay
;
409 int bf_regs_per_page
;
416 int max_qp_init_rdma
;
417 int max_qp_dest_rdma
;
432 int num_comp_vectors
;
437 int fmr_reserved_mtts
;
446 int fs_log_max_ucast_qp_range_size
;
458 u16 stat_rate_support
;
459 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
462 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
464 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
467 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
468 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
469 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
470 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
471 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
472 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
474 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
479 u32 userspace_caps
; /* userspace must be aware of these */
480 u32 function_caps
; /* VFs must be aware of these */
482 u64 phys_port_id
[MLX4_MAX_PORTS
+ 1];
483 int tunnel_offload_mode
;
486 struct mlx4_buf_list
{
492 struct mlx4_buf_list direct
;
493 struct mlx4_buf_list
*page_list
;
506 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
509 struct mlx4_db_pgdir
{
510 struct list_head list
;
511 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
512 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
513 unsigned long *bits
[2];
518 struct mlx4_ib_user_db_page
;
523 struct mlx4_db_pgdir
*pgdir
;
524 struct mlx4_ib_user_db_page
*user_page
;
531 struct mlx4_hwq_resources
{
555 enum mlx4_mw_type type
;
561 struct mlx4_mpt_entry
*mpt
;
563 dma_addr_t dma_handle
;
573 struct list_head bf_list
;
574 unsigned free_bf_bmap
;
576 void __iomem
*bf_map
;
580 unsigned long offset
;
582 struct mlx4_uar
*uar
;
587 void (*comp
) (struct mlx4_cq
*);
588 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
590 struct mlx4_uar
*uar
;
603 struct completion free
;
607 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
612 struct completion free
;
616 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
624 struct completion free
;
636 __be32 sl_tclass_flowlabel
;
649 __be32 sl_tclass_flowlabel
;
659 struct mlx4_eth_av eth
;
662 struct mlx4_counter
{
689 struct pci_dev
*pdev
;
691 unsigned long num_slaves
;
692 struct mlx4_caps caps
;
693 struct mlx4_phys_caps phys_caps
;
694 struct mlx4_quotas quotas
;
695 struct radix_tree_root qp_table_tree
;
697 char board_id
[MLX4_BOARD_ID_LEN
];
700 int oper_log_mgm_entry_size
;
701 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
702 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
703 struct mlx4_vf_dev
*dev_vfs
;
739 } __packed port_change
;
741 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
743 u32 bit_vec
[COMM_CHANNEL_BIT_ARRAY_SIZE
];
744 } __packed comm_channel_arm
;
749 } __packed mac_update
;
752 } __packed flr_event
;
754 __be16 current_temperature
;
755 __be16 warning_threshold
;
768 } __packed port_info
;
771 __be32 tbl_entries_mask
;
772 } __packed tbl_change_info
;
774 } __packed port_mgmt_change
;
781 struct mlx4_init_port_param
{
795 #define mlx4_foreach_port(port, dev, type) \
796 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
797 if ((type) == (dev)->caps.port_mask[(port)])
799 #define mlx4_foreach_non_ib_transport_port(port, dev) \
800 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
801 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
803 #define mlx4_foreach_ib_transport_port(port, dev) \
804 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
805 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
806 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
808 #define MLX4_INVALID_SLAVE_ID 0xFF
810 void handle_port_mgmt_change_event(struct work_struct
*work
);
812 static inline int mlx4_master_func_num(struct mlx4_dev
*dev
)
814 return dev
->caps
.function
;
817 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
819 return dev
->flags
& MLX4_FLAG_MASTER
;
822 static inline int mlx4_num_reserved_sqps(struct mlx4_dev
*dev
)
824 return dev
->phys_caps
.base_sqpn
+ 8 +
825 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
);
828 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
830 return (qpn
< dev
->phys_caps
.base_sqpn
+ 8 +
831 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
));
834 static inline int mlx4_is_guest_proxy(struct mlx4_dev
*dev
, int slave
, u32 qpn
)
836 int guest_proxy_base
= dev
->phys_caps
.base_proxy_sqpn
+ slave
* 8;
838 if (qpn
>= guest_proxy_base
&& qpn
< guest_proxy_base
+ 8)
844 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
846 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
849 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
851 return dev
->flags
& MLX4_FLAG_SLAVE
;
854 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
855 struct mlx4_buf
*buf
, gfp_t gfp
);
856 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
857 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
859 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
860 return buf
->direct
.buf
+ offset
;
862 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
863 (offset
& (PAGE_SIZE
- 1));
866 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
867 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
868 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
869 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
871 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
872 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
873 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
, int node
);
874 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
876 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
877 struct mlx4_mtt
*mtt
);
878 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
879 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
881 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
882 int npages
, int page_shift
, struct mlx4_mr
*mr
);
883 int mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
884 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
885 int mlx4_mw_alloc(struct mlx4_dev
*dev
, u32 pd
, enum mlx4_mw_type type
,
887 void mlx4_mw_free(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
888 int mlx4_mw_enable(struct mlx4_dev
*dev
, struct mlx4_mw
*mw
);
889 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
890 int start_index
, int npages
, u64
*page_list
);
891 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
892 struct mlx4_buf
*buf
, gfp_t gfp
);
894 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
,
896 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
898 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
899 int size
, int max_direct
);
900 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
903 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
904 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
905 unsigned vector
, int collapsed
, int timestamp_en
);
906 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
908 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
909 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
911 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
,
913 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
915 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
916 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
917 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
918 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
919 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
921 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
922 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
924 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
925 int block_mcast_loopback
, enum mlx4_protocol prot
);
926 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
927 enum mlx4_protocol prot
);
928 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
929 u8 port
, int block_mcast_loopback
,
930 enum mlx4_protocol protocol
, u64
*reg_id
);
931 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
932 enum mlx4_protocol protocol
, u64 reg_id
);
935 MLX4_DOMAIN_UVERBS
= 0x1000,
936 MLX4_DOMAIN_ETHTOOL
= 0x2000,
937 MLX4_DOMAIN_RFS
= 0x3000,
938 MLX4_DOMAIN_NIC
= 0x5000,
941 enum mlx4_net_trans_rule_id
{
942 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
943 MLX4_NET_TRANS_RULE_ID_IB
,
944 MLX4_NET_TRANS_RULE_ID_IPV6
,
945 MLX4_NET_TRANS_RULE_ID_IPV4
,
946 MLX4_NET_TRANS_RULE_ID_TCP
,
947 MLX4_NET_TRANS_RULE_ID_UDP
,
948 MLX4_NET_TRANS_RULE_ID_VXLAN
,
949 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
952 extern const u16 __sw_id_hw
[];
954 static inline int map_hw_to_sw_id(u16 header_id
)
958 for (i
= 0; i
< MLX4_NET_TRANS_RULE_NUM
; i
++) {
959 if (header_id
== __sw_id_hw
[i
])
965 enum mlx4_net_trans_promisc_mode
{
971 MLX4_FS_MODE_NUM
, /* should be last */
974 struct mlx4_spec_eth
{
975 u8 dst_mac
[ETH_ALEN
];
976 u8 dst_mac_msk
[ETH_ALEN
];
977 u8 src_mac
[ETH_ALEN
];
978 u8 src_mac_msk
[ETH_ALEN
];
979 u8 ether_type_enable
;
985 struct mlx4_spec_tcp_udp
{
992 struct mlx4_spec_ipv4
{
999 struct mlx4_spec_ib
{
1006 struct mlx4_spec_vxlan
{
1012 struct mlx4_spec_list
{
1013 struct list_head list
;
1014 enum mlx4_net_trans_rule_id id
;
1016 struct mlx4_spec_eth eth
;
1017 struct mlx4_spec_ib ib
;
1018 struct mlx4_spec_ipv4 ipv4
;
1019 struct mlx4_spec_tcp_udp tcp_udp
;
1020 struct mlx4_spec_vxlan vxlan
;
1024 enum mlx4_net_trans_hw_rule_queue
{
1025 MLX4_NET_TRANS_Q_FIFO
,
1026 MLX4_NET_TRANS_Q_LIFO
,
1029 struct mlx4_net_trans_rule
{
1030 struct list_head list
;
1031 enum mlx4_net_trans_hw_rule_queue queue_mode
;
1033 bool allow_loopback
;
1034 enum mlx4_net_trans_promisc_mode promisc_mode
;
1040 struct mlx4_net_trans_rule_hw_ctrl
{
1052 struct mlx4_net_trans_rule_hw_ib
{
1063 struct mlx4_net_trans_rule_hw_eth
{
1076 u8 ether_type_enable
;
1078 __be16 vlan_tag_msk
;
1082 struct mlx4_net_trans_rule_hw_tcp_udp
{
1089 __be16 dst_port_msk
;
1093 __be16 src_port_msk
;
1096 struct mlx4_net_trans_rule_hw_ipv4
{
1107 struct mlx4_net_trans_rule_hw_vxlan
{
1123 struct mlx4_net_trans_rule_hw_eth eth
;
1124 struct mlx4_net_trans_rule_hw_ib ib
;
1125 struct mlx4_net_trans_rule_hw_ipv4 ipv4
;
1126 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp
;
1127 struct mlx4_net_trans_rule_hw_vxlan vxlan
;
1132 VXLAN_STEER_BY_OUTER_MAC
= 1 << 0,
1133 VXLAN_STEER_BY_OUTER_VLAN
= 1 << 1,
1134 VXLAN_STEER_BY_VSID_VNI
= 1 << 2,
1135 VXLAN_STEER_BY_INNER_MAC
= 1 << 3,
1136 VXLAN_STEER_BY_INNER_VLAN
= 1 << 4,
1140 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
1141 enum mlx4_net_trans_promisc_mode mode
);
1142 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
1143 enum mlx4_net_trans_promisc_mode mode
);
1144 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1145 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1146 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1147 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
1148 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
1150 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1151 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
1152 int mlx4_get_base_qpn(struct mlx4_dev
*dev
, u8 port
);
1153 int __mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
1154 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
1155 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
1156 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
1157 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
1159 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
1160 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
1161 u8
*pg
, u16
*ratelimit
);
1162 int mlx4_SET_PORT_VXLAN(struct mlx4_dev
*dev
, u8 port
, u8 steering
, int enable
);
1163 int mlx4_find_cached_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *idx
);
1164 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
1165 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
1166 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
);
1168 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
1169 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
1170 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
1171 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
1172 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1173 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
1174 u32
*lkey
, u32
*rkey
);
1175 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
1176 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
1177 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
1178 int mlx4_assign_eq(struct mlx4_dev
*dev
, char *name
, struct cpu_rmap
*rmap
,
1180 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
1182 int mlx4_eq_get_irq(struct mlx4_dev
*dev
, int vec
);
1184 int mlx4_get_phys_port_id(struct mlx4_dev
*dev
);
1185 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
1186 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
1188 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
1189 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
1191 int mlx4_flow_attach(struct mlx4_dev
*dev
,
1192 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
1193 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
1194 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev
*dev
,
1195 enum mlx4_net_trans_promisc_mode flow_type
);
1196 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev
*dev
,
1197 enum mlx4_net_trans_rule_id id
);
1198 int mlx4_hw_rule_sz(struct mlx4_dev
*dev
, enum mlx4_net_trans_rule_id id
);
1200 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
,
1203 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
);
1205 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
);
1206 int mlx4_gen_pkey_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1207 int mlx4_gen_guid_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
1208 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev
*dev
, u8 port
, int attr
);
1209 int mlx4_gen_port_state_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
, u8 port_subtype_change
);
1210 enum slave_port_state
mlx4_get_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
);
1211 int set_and_calc_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
, int event
, enum slave_port_gen_event
*gen_event
);
1213 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
);
1214 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
);
1216 int mlx4_get_slave_from_roce_gid(struct mlx4_dev
*dev
, int port
, u8
*gid
,
1218 int mlx4_get_roce_gid_from_slave(struct mlx4_dev
*dev
, int port
, int slave_id
,
1221 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev
*dev
, u32 min_range_qpn
,
1224 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
);
1226 struct mlx4_active_ports
{
1227 DECLARE_BITMAP(ports
, MLX4_MAX_PORTS
);
1229 /* Returns a bitmap of the physical ports which are assigned to slave */
1230 struct mlx4_active_ports
mlx4_get_active_ports(struct mlx4_dev
*dev
, int slave
);
1232 /* Returns the physical port that represents the virtual port of the slave, */
1233 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1234 /* mapping is returned. */
1235 int mlx4_slave_convert_port(struct mlx4_dev
*dev
, int slave
, int port
);
1237 struct mlx4_slaves_pport
{
1238 DECLARE_BITMAP(slaves
, MLX4_MFUNC_MAX
);
1240 /* Returns a bitmap of all slaves that are assigned to port. */
1241 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport(struct mlx4_dev
*dev
,
1244 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1245 /* the ports that are set in crit_ports. */
1246 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport_actv(
1247 struct mlx4_dev
*dev
,
1248 const struct mlx4_active_ports
*crit_ports
);
1250 /* Returns the slave's virtual port that represents the physical port. */
1251 int mlx4_phys_to_slave_port(struct mlx4_dev
*dev
, int slave
, int port
);
1253 int mlx4_get_base_gid_ix(struct mlx4_dev
*dev
, int slave
, int port
);
1255 int mlx4_config_vxlan_port(struct mlx4_dev
*dev
, __be16 udp_port
);
1256 int mlx4_vf_smi_enabled(struct mlx4_dev
*dev
, int slave
, int port
);
1257 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
);
1258 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
,
1260 int mlx4_mr_hw_get_mpt(struct mlx4_dev
*dev
, struct mlx4_mr
*mmr
,
1261 struct mlx4_mpt_entry
***mpt_entry
);
1262 int mlx4_mr_hw_write_mpt(struct mlx4_dev
*dev
, struct mlx4_mr
*mmr
,
1263 struct mlx4_mpt_entry
**mpt_entry
);
1264 int mlx4_mr_hw_change_pd(struct mlx4_dev
*dev
, struct mlx4_mpt_entry
*mpt_entry
,
1266 int mlx4_mr_hw_change_access(struct mlx4_dev
*dev
,
1267 struct mlx4_mpt_entry
*mpt_entry
,
1269 void mlx4_mr_hw_put_mpt(struct mlx4_dev
*dev
,
1270 struct mlx4_mpt_entry
**mpt_entry
);
1271 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
1272 int mlx4_mr_rereg_mem_write(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
,
1273 u64 iova
, u64 size
, int npages
,
1274 int page_shift
, struct mlx4_mpt_entry
*mpt_entry
);
1276 /* Returns true if running in low memory profile (kdump kernel) */
1277 static inline bool mlx4_low_memory_profile(void)
1279 return is_kdump_kernel();
1282 #endif /* MLX4_DEVICE_H */