2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
41 #include <linux/atomic.h>
43 #define MAX_MSIX_P_PORT 17
45 #define MSIX_LEGACY_SZ 4
46 #define MIN_MSIX_P_PORT 5
49 MLX4_FLAG_MSI_X
= 1 << 0,
50 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
51 MLX4_FLAG_MASTER
= 1 << 2,
52 MLX4_FLAG_SLAVE
= 1 << 3,
53 MLX4_FLAG_SRIOV
= 1 << 4,
57 MLX4_PORT_CAP_IS_SM
= 1 << 1,
58 MLX4_PORT_CAP_DEV_MGMT_SUP
= 1 << 19,
63 MLX4_MAX_PORT_PKEYS
= 128
66 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
67 * These qkeys must not be allowed for general use. This is a 64k range,
68 * and to test for violation, we use the mask (protect against future chg).
70 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
71 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
74 MLX4_BOARD_ID_LEN
= 64
81 MLX4_MAX_EQ_NUM
= 1024,
82 MLX4_MFUNC_EQ_NUM
= 4,
83 MLX4_MFUNC_MAX_EQES
= 8,
84 MLX4_MFUNC_EQE_MASK
= (MLX4_MFUNC_MAX_EQES
- 1)
87 /* Driver supports 3 diffrent device methods to manage traffic steering:
88 * -device managed - High level API for ib and eth flow steering. FW is
89 * managing flow steering tables.
90 * - B0 steering mode - Common low level API for ib and (if supported) eth.
91 * - A0 steering mode - Limited low level API for eth. In case of IB,
95 MLX4_STEERING_MODE_A0
,
96 MLX4_STEERING_MODE_B0
,
97 MLX4_STEERING_MODE_DEVICE_MANAGED
100 static inline const char *mlx4_steering_mode_str(int steering_mode
)
102 switch (steering_mode
) {
103 case MLX4_STEERING_MODE_A0
:
104 return "A0 steering";
106 case MLX4_STEERING_MODE_B0
:
107 return "B0 steering";
109 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
110 return "Device managed flow steering";
113 return "Unrecognize steering mode";
118 MLX4_DEV_CAP_FLAG_RC
= 1LL << 0,
119 MLX4_DEV_CAP_FLAG_UC
= 1LL << 1,
120 MLX4_DEV_CAP_FLAG_UD
= 1LL << 2,
121 MLX4_DEV_CAP_FLAG_XRC
= 1LL << 3,
122 MLX4_DEV_CAP_FLAG_SRQ
= 1LL << 6,
123 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1LL << 7,
124 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
125 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
126 MLX4_DEV_CAP_FLAG_DPDP
= 1LL << 12,
127 MLX4_DEV_CAP_FLAG_BLH
= 1LL << 15,
128 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1LL << 16,
129 MLX4_DEV_CAP_FLAG_APM
= 1LL << 17,
130 MLX4_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
131 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1LL << 19,
132 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1LL << 20,
133 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1LL << 21,
134 MLX4_DEV_CAP_FLAG_IBOE
= 1LL << 30,
135 MLX4_DEV_CAP_FLAG_UC_LOOPBACK
= 1LL << 32,
136 MLX4_DEV_CAP_FLAG_FCS_KEEP
= 1LL << 34,
137 MLX4_DEV_CAP_FLAG_WOL_PORT1
= 1LL << 37,
138 MLX4_DEV_CAP_FLAG_WOL_PORT2
= 1LL << 38,
139 MLX4_DEV_CAP_FLAG_UDP_RSS
= 1LL << 40,
140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER
= 1LL << 41,
141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER
= 1LL << 42,
142 MLX4_DEV_CAP_FLAG_COUNTERS
= 1LL << 48,
143 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
= 1LL << 55,
144 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
= 1LL << 59,
148 MLX4_DEV_CAP_FLAG2_RSS
= 1LL << 0,
149 MLX4_DEV_CAP_FLAG2_RSS_TOP
= 1LL << 1,
150 MLX4_DEV_CAP_FLAG2_RSS_XOR
= 1LL << 2,
151 MLX4_DEV_CAP_FLAG2_FS_EN
= 1LL << 3
154 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
157 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
158 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
159 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
160 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
161 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
165 MLX4_EVENT_TYPE_COMP
= 0x00,
166 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
167 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
168 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
169 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
170 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
171 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
172 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
173 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
174 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
175 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
176 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
177 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
178 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
179 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
180 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
181 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
182 MLX4_EVENT_TYPE_CMD
= 0x0a,
183 MLX4_EVENT_TYPE_VEP_UPDATE
= 0x19,
184 MLX4_EVENT_TYPE_COMM_CHANNEL
= 0x18,
185 MLX4_EVENT_TYPE_FATAL_WARNING
= 0x1b,
186 MLX4_EVENT_TYPE_FLR_EVENT
= 0x1c,
187 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT
= 0x1d,
188 MLX4_EVENT_TYPE_NONE
= 0xff,
192 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
193 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
197 MLX4_FATAL_WARNING_SUBTYPE_WARMING
= 0,
200 enum slave_port_state
{
206 enum slave_port_gen_event
{
207 SLAVE_PORT_GEN_EVENT_DOWN
= 0,
208 SLAVE_PORT_GEN_EVENT_UP
,
209 SLAVE_PORT_GEN_EVENT_NONE
,
212 enum slave_port_state_event
{
213 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN
,
214 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
,
215 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID
,
216 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
,
220 MLX4_PERM_LOCAL_READ
= 1 << 10,
221 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
222 MLX4_PERM_REMOTE_READ
= 1 << 12,
223 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
224 MLX4_PERM_ATOMIC
= 1 << 14
228 MLX4_OPCODE_NOP
= 0x00,
229 MLX4_OPCODE_SEND_INVAL
= 0x01,
230 MLX4_OPCODE_RDMA_WRITE
= 0x08,
231 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
232 MLX4_OPCODE_SEND
= 0x0a,
233 MLX4_OPCODE_SEND_IMM
= 0x0b,
234 MLX4_OPCODE_LSO
= 0x0e,
235 MLX4_OPCODE_RDMA_READ
= 0x10,
236 MLX4_OPCODE_ATOMIC_CS
= 0x11,
237 MLX4_OPCODE_ATOMIC_FA
= 0x12,
238 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
239 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
240 MLX4_OPCODE_BIND_MW
= 0x18,
241 MLX4_OPCODE_FMR
= 0x19,
242 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
243 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
245 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
246 MLX4_RECV_OPCODE_SEND
= 0x01,
247 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
248 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
250 MLX4_CQE_OPCODE_ERROR
= 0x1e,
251 MLX4_CQE_OPCODE_RESIZE
= 0x16,
255 MLX4_STAT_RATE_OFFSET
= 5
259 MLX4_PROT_IB_IPV6
= 0,
266 MLX4_MTT_FLAG_PRESENT
= 1
269 enum mlx4_qp_region
{
270 MLX4_QP_REGION_FW
= 0,
271 MLX4_QP_REGION_ETH_ADDR
,
272 MLX4_QP_REGION_FC_ADDR
,
273 MLX4_QP_REGION_FC_EXCH
,
277 enum mlx4_port_type
{
278 MLX4_PORT_TYPE_NONE
= 0,
279 MLX4_PORT_TYPE_IB
= 1,
280 MLX4_PORT_TYPE_ETH
= 2,
281 MLX4_PORT_TYPE_AUTO
= 3
284 enum mlx4_special_vlan_idx
{
285 MLX4_NO_VLAN_IDX
= 0,
290 enum mlx4_steer_type
{
297 MLX4_NUM_FEXCH
= 64 * 1024,
301 MLX4_MAX_FAST_REG_PAGES
= 511,
305 MLX4_DEV_PMC_SUBTYPE_GUID_INFO
= 0x14,
306 MLX4_DEV_PMC_SUBTYPE_PORT_INFO
= 0x15,
307 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE
= 0x16,
310 /* Port mgmt change event handling */
312 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK
= 1 << 0,
313 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK
= 1 << 1,
314 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK
= 1 << 2,
315 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK
= 1 << 3,
316 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK
= 1 << 4,
319 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
320 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
322 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
324 return (major
<< 32) | (minor
<< 16) | subminor
;
327 struct mlx4_phys_caps
{
328 u32 gid_phys_table_len
[MLX4_MAX_PORTS
+ 1];
329 u32 pkey_phys_table_len
[MLX4_MAX_PORTS
+ 1];
337 int vl_cap
[MLX4_MAX_PORTS
+ 1];
338 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
339 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
340 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
341 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
342 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
343 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
344 int trans_type
[MLX4_MAX_PORTS
+ 1];
345 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
346 int wavelength
[MLX4_MAX_PORTS
+ 1];
347 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
348 int local_ca_ack_delay
;
352 int bf_regs_per_page
;
359 int max_qp_init_rdma
;
360 int max_qp_dest_rdma
;
363 u32 base_tunnel_sqpn
;
373 int num_comp_vectors
;
378 int fmr_reserved_mtts
;
387 int fs_log_max_ucast_qp_range_size
;
399 u16 stat_rate_support
;
400 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
403 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
405 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
409 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
410 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
411 u8 suggested_type
[MLX4_MAX_PORTS
+ 1];
412 u8 default_sense
[MLX4_MAX_PORTS
+ 1];
413 u32 port_mask
[MLX4_MAX_PORTS
+ 1];
414 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
416 u8 port_ib_mtu
[MLX4_MAX_PORTS
+ 1];
420 struct mlx4_buf_list
{
426 struct mlx4_buf_list direct
;
427 struct mlx4_buf_list
*page_list
;
440 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
443 struct mlx4_db_pgdir
{
444 struct list_head list
;
445 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
446 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
447 unsigned long *bits
[2];
452 struct mlx4_ib_user_db_page
;
457 struct mlx4_db_pgdir
*pgdir
;
458 struct mlx4_ib_user_db_page
*user_page
;
465 struct mlx4_hwq_resources
{
483 struct mlx4_mpt_entry
*mpt
;
485 dma_addr_t dma_handle
;
495 struct list_head bf_list
;
496 unsigned free_bf_bmap
;
498 void __iomem
*bf_map
;
502 unsigned long offset
;
504 struct mlx4_uar
*uar
;
509 void (*comp
) (struct mlx4_cq
*);
510 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
512 struct mlx4_uar
*uar
;
524 struct completion free
;
528 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
533 struct completion free
;
537 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
545 struct completion free
;
557 __be32 sl_tclass_flowlabel
;
570 __be32 sl_tclass_flowlabel
;
579 struct mlx4_eth_av eth
;
582 struct mlx4_counter
{
594 struct pci_dev
*pdev
;
596 unsigned long num_slaves
;
597 struct mlx4_caps caps
;
598 struct mlx4_phys_caps phys_caps
;
599 struct radix_tree_root qp_table_tree
;
601 char board_id
[MLX4_BOARD_ID_LEN
];
603 u64 regid_promisc_array
[MLX4_MAX_PORTS
+ 1];
604 u64 regid_allmulti_array
[MLX4_MAX_PORTS
+ 1];
640 } __packed port_change
;
642 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
644 u32 bit_vec
[COMM_CHANNEL_BIT_ARRAY_SIZE
];
645 } __packed comm_channel_arm
;
650 } __packed mac_update
;
653 } __packed flr_event
;
655 __be16 current_temperature
;
656 __be16 warning_threshold
;
669 } __packed port_info
;
672 __be32 tbl_entries_mask
;
673 } __packed tbl_change_info
;
675 } __packed port_mgmt_change
;
682 struct mlx4_init_port_param
{
696 #define mlx4_foreach_port(port, dev, type) \
697 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
698 if ((type) == (dev)->caps.port_mask[(port)])
700 #define mlx4_foreach_ib_transport_port(port, dev) \
701 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
702 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
703 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
705 #define MLX4_INVALID_SLAVE_ID 0xFF
707 void handle_port_mgmt_change_event(struct work_struct
*work
);
709 static inline int mlx4_master_func_num(struct mlx4_dev
*dev
)
711 return dev
->caps
.function
;
714 static inline int mlx4_is_master(struct mlx4_dev
*dev
)
716 return dev
->flags
& MLX4_FLAG_MASTER
;
719 static inline int mlx4_is_qp_reserved(struct mlx4_dev
*dev
, u32 qpn
)
721 return (qpn
< dev
->caps
.base_sqpn
+ 8 +
722 16 * MLX4_MFUNC_MAX
* !!mlx4_is_master(dev
));
725 static inline int mlx4_is_guest_proxy(struct mlx4_dev
*dev
, int slave
, u32 qpn
)
727 int base
= dev
->caps
.sqp_start
+ slave
* 8;
729 if (qpn
>= base
&& qpn
< base
+ 8)
735 static inline int mlx4_is_mfunc(struct mlx4_dev
*dev
)
737 return dev
->flags
& (MLX4_FLAG_SLAVE
| MLX4_FLAG_MASTER
);
740 static inline int mlx4_is_slave(struct mlx4_dev
*dev
)
742 return dev
->flags
& MLX4_FLAG_SLAVE
;
745 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
746 struct mlx4_buf
*buf
);
747 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
748 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
750 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
751 return buf
->direct
.buf
+ offset
;
753 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
754 (offset
& (PAGE_SIZE
- 1));
757 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
758 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
759 int mlx4_xrcd_alloc(struct mlx4_dev
*dev
, u32
*xrcdn
);
760 void mlx4_xrcd_free(struct mlx4_dev
*dev
, u32 xrcdn
);
762 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
763 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
764 int mlx4_bf_alloc(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
765 void mlx4_bf_free(struct mlx4_dev
*dev
, struct mlx4_bf
*bf
);
767 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
768 struct mlx4_mtt
*mtt
);
769 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
770 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
772 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
773 int npages
, int page_shift
, struct mlx4_mr
*mr
);
774 void mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
775 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
776 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
777 int start_index
, int npages
, u64
*page_list
);
778 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
779 struct mlx4_buf
*buf
);
781 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
);
782 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
784 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
785 int size
, int max_direct
);
786 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
789 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
790 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
791 unsigned vector
, int collapsed
);
792 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
794 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
795 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
797 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
);
798 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
800 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, u32 cqn
, u16 xrcdn
,
801 struct mlx4_mtt
*mtt
, u64 db_rec
, struct mlx4_srq
*srq
);
802 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
803 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
804 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
806 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
807 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
809 int mlx4_unicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
810 int block_mcast_loopback
, enum mlx4_protocol prot
);
811 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
812 enum mlx4_protocol prot
);
813 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
814 u8 port
, int block_mcast_loopback
,
815 enum mlx4_protocol protocol
, u64
*reg_id
);
816 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
817 enum mlx4_protocol protocol
, u64 reg_id
);
820 MLX4_DOMAIN_UVERBS
= 0x1000,
821 MLX4_DOMAIN_ETHTOOL
= 0x2000,
822 MLX4_DOMAIN_RFS
= 0x3000,
823 MLX4_DOMAIN_NIC
= 0x5000,
826 enum mlx4_net_trans_rule_id
{
827 MLX4_NET_TRANS_RULE_ID_ETH
= 0,
828 MLX4_NET_TRANS_RULE_ID_IB
,
829 MLX4_NET_TRANS_RULE_ID_IPV6
,
830 MLX4_NET_TRANS_RULE_ID_IPV4
,
831 MLX4_NET_TRANS_RULE_ID_TCP
,
832 MLX4_NET_TRANS_RULE_ID_UDP
,
833 MLX4_NET_TRANS_RULE_NUM
, /* should be last */
836 extern const u16 __sw_id_hw
[];
838 static inline int map_hw_to_sw_id(u16 header_id
)
842 for (i
= 0; i
< MLX4_NET_TRANS_RULE_NUM
; i
++) {
843 if (header_id
== __sw_id_hw
[i
])
849 enum mlx4_net_trans_promisc_mode
{
850 MLX4_FS_PROMISC_NONE
= 0,
851 MLX4_FS_PROMISC_UPLINK
,
852 /* For future use. Not implemented yet */
853 MLX4_FS_PROMISC_FUNCTION_PORT
,
854 MLX4_FS_PROMISC_ALL_MULTI
,
857 struct mlx4_spec_eth
{
862 u8 ether_type_enable
;
868 struct mlx4_spec_tcp_udp
{
875 struct mlx4_spec_ipv4
{
882 struct mlx4_spec_ib
{
889 struct mlx4_spec_list
{
890 struct list_head list
;
891 enum mlx4_net_trans_rule_id id
;
893 struct mlx4_spec_eth eth
;
894 struct mlx4_spec_ib ib
;
895 struct mlx4_spec_ipv4 ipv4
;
896 struct mlx4_spec_tcp_udp tcp_udp
;
900 enum mlx4_net_trans_hw_rule_queue
{
901 MLX4_NET_TRANS_Q_FIFO
,
902 MLX4_NET_TRANS_Q_LIFO
,
905 struct mlx4_net_trans_rule
{
906 struct list_head list
;
907 enum mlx4_net_trans_hw_rule_queue queue_mode
;
910 enum mlx4_net_trans_promisc_mode promisc_mode
;
916 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
, u32 qpn
,
917 enum mlx4_net_trans_promisc_mode mode
);
918 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
919 enum mlx4_net_trans_promisc_mode mode
);
920 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
921 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
922 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
923 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
);
924 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
926 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
927 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
);
928 int mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
);
929 int mlx4_get_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *qpn
);
930 void mlx4_put_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int qpn
);
931 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
);
932 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
933 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
);
934 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
936 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
);
937 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
938 u8
*pg
, u16
*ratelimit
);
939 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
940 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
941 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
);
943 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
944 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
945 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
946 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
947 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
948 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
949 u32
*lkey
, u32
*rkey
);
950 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
951 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
952 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
953 int mlx4_assign_eq(struct mlx4_dev
*dev
, char *name
, struct cpu_rmap
*rmap
,
955 void mlx4_release_eq(struct mlx4_dev
*dev
, int vec
);
957 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
);
958 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
);
960 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
);
961 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
);
963 int mlx4_flow_attach(struct mlx4_dev
*dev
,
964 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
);
965 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
);
967 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
,
970 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
);
972 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
);
973 int mlx4_gen_pkey_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
974 int mlx4_gen_guid_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
);
975 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev
*dev
, u8 port
, int attr
);
976 int mlx4_gen_port_state_change_eqe(struct mlx4_dev
*dev
, int slave
, u8 port
, u8 port_subtype_change
);
977 enum slave_port_state
mlx4_get_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
);
978 int set_and_calc_slave_port_state(struct mlx4_dev
*dev
, int slave
, u8 port
, int event
, enum slave_port_gen_event
*gen_event
);
981 #endif /* MLX4_DEVICE_H */