2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <linux/if_ether.h>
39 #include <linux/mlx4/device.h>
41 #define MLX4_INVALID_LKEY 0x100
44 MLX4_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
45 MLX4_QP_OPTPAR_RRE
= 1 << 1,
46 MLX4_QP_OPTPAR_RAE
= 1 << 2,
47 MLX4_QP_OPTPAR_RWE
= 1 << 3,
48 MLX4_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
49 MLX4_QP_OPTPAR_Q_KEY
= 1 << 5,
50 MLX4_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
51 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
52 MLX4_QP_OPTPAR_SRA_MAX
= 1 << 8,
53 MLX4_QP_OPTPAR_RRA_MAX
= 1 << 9,
54 MLX4_QP_OPTPAR_PM_STATE
= 1 << 10,
55 MLX4_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
56 MLX4_QP_OPTPAR_RNR_RETRY
= 1 << 13,
57 MLX4_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
58 MLX4_QP_OPTPAR_SCHED_QUEUE
= 1 << 16,
59 MLX4_QP_OPTPAR_COUNTER_INDEX
= 1 << 20,
60 MLX4_QP_OPTPAR_VLAN_STRIPPING
= 1 << 21,
64 MLX4_QP_STATE_RST
= 0,
65 MLX4_QP_STATE_INIT
= 1,
66 MLX4_QP_STATE_RTR
= 2,
67 MLX4_QP_STATE_RTS
= 3,
68 MLX4_QP_STATE_SQER
= 4,
69 MLX4_QP_STATE_SQD
= 5,
70 MLX4_QP_STATE_ERR
= 6,
71 MLX4_QP_STATE_SQ_DRAINING
= 7,
85 MLX4_QP_PM_MIGRATED
= 0x3,
86 MLX4_QP_PM_ARMED
= 0x0,
87 MLX4_QP_PM_REARM
= 0x1
92 MLX4_QP_BIT_SRE
= 1 << 15,
93 MLX4_QP_BIT_SWE
= 1 << 14,
94 MLX4_QP_BIT_SAE
= 1 << 13,
96 MLX4_QP_BIT_RRE
= 1 << 15,
97 MLX4_QP_BIT_RWE
= 1 << 14,
98 MLX4_QP_BIT_RAE
= 1 << 13,
99 MLX4_QP_BIT_FPP
= 1 << 3,
100 MLX4_QP_BIT_RIC
= 1 << 4,
104 MLX4_RSS_HASH_XOR
= 0,
105 MLX4_RSS_HASH_TOP
= 1,
107 MLX4_RSS_UDP_IPV6
= 1 << 0,
108 MLX4_RSS_UDP_IPV4
= 1 << 1,
109 MLX4_RSS_TCP_IPV6
= 1 << 2,
110 MLX4_RSS_IPV6
= 1 << 3,
111 MLX4_RSS_TCP_IPV4
= 1 << 4,
112 MLX4_RSS_IPV4
= 1 << 5,
114 MLX4_RSS_BY_OUTER_HEADERS
= 0 << 6,
115 MLX4_RSS_BY_INNER_HEADERS
= 2 << 6,
116 MLX4_RSS_BY_INNER_HEADERS_IPONLY
= 3 << 6,
118 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
119 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH
= 0x24,
120 /* offset of being RSS indirection QP within mlx4_qp_context.flags */
121 MLX4_RSS_QPC_FLAG_OFFSET
= 13,
124 #define MLX4_EN_RSS_KEY_SIZE 40
126 struct mlx4_rss_context
{
132 __be32 rss_key
[MLX4_EN_RSS_KEY_SIZE
/ sizeof(__be32
)];
136 struct mlx4_qp_path
{
142 u8 disable_pkey_check
;
151 __be32 tclass_flowlabel
;
163 MLX4_FL_ETH_HIDE_CQE_VLAN
= 1 << 2,
164 MLX4_FL_ETH_SRC_CHECK_MC_LB
= 1 << 1,
165 MLX4_FL_ETH_SRC_CHECK_UC_LB
= 1 << 0,
169 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER
= 1 << 7,
172 enum { /* vlan_control */
173 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED
= 1 << 6,
174 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED
= 1 << 5, /* 802.1p priority tag */
175 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED
= 1 << 4,
176 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED
= 1 << 2,
177 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED
= 1 << 1, /* 802.1p priority tag */
178 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED
= 1 << 0
182 MLX4_FEUP_FORCE_ETH_UP
= 1 << 6, /* force Eth UP */
183 MLX4_FSM_FORCE_ETH_SRC_MAC
= 1 << 5, /* force Source MAC */
184 MLX4_FVL_FORCE_ETH_VLAN
= 1 << 3 /* force Eth vlan */
188 MLX4_FVL_RX_FORCE_ETH_VLAN
= 1 << 0 /* enforce Eth rx vlan */
191 struct mlx4_qp_context
{
201 struct mlx4_qp_path pri_path
;
202 struct mlx4_qp_path alt_path
;
205 __be32 next_send_psn
;
208 __be32 last_acked_psn
;
211 __be32 rnr_nextrecvpsn
;
218 __be16 rq_wqe_counter
;
219 __be16 sq_wqe_counter
;
221 __be16 rate_limit_params
;
225 __be32 nummmcpeers_basemkey
;
229 __be32 mtt_base_addr_l
;
233 struct mlx4_update_qp_context
{
235 __be64 primary_addr_path_mask
;
236 __be64 secondary_addr_path_mask
;
238 struct mlx4_qp_context qp_context
;
243 MLX4_UPD_QP_MASK_PM_STATE
= 32,
244 MLX4_UPD_QP_MASK_VSD
= 33,
245 MLX4_UPD_QP_MASK_QOS_VPP
= 34,
246 MLX4_UPD_QP_MASK_RATE_LIMIT
= 35,
250 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX
= 0 + 32,
251 MLX4_UPD_QP_PATH_MASK_FSM
= 1 + 32,
252 MLX4_UPD_QP_PATH_MASK_MAC_INDEX
= 2 + 32,
253 MLX4_UPD_QP_PATH_MASK_FVL
= 3 + 32,
254 MLX4_UPD_QP_PATH_MASK_CV
= 4 + 32,
255 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX
= 5 + 32,
256 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN
= 6 + 32,
257 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED
= 7 + 32,
258 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P
= 8 + 32,
259 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED
= 9 + 32,
260 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED
= 10 + 32,
261 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P
= 11 + 32,
262 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED
= 12 + 32,
263 MLX4_UPD_QP_PATH_MASK_FEUP
= 13 + 32,
264 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE
= 14 + 32,
265 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX
= 15 + 32,
266 MLX4_UPD_QP_PATH_MASK_FVL_RX
= 16 + 32,
267 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB
= 18 + 32,
268 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB
= 19 + 32,
272 MLX4_STRIP_VLAN
= 1 << 30
275 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
276 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
279 MLX4_WQE_CTRL_NEC
= 1 << 29,
280 MLX4_WQE_CTRL_IIP
= 1 << 28,
281 MLX4_WQE_CTRL_ILP
= 1 << 27,
282 MLX4_WQE_CTRL_FENCE
= 1 << 6,
283 MLX4_WQE_CTRL_CQ_UPDATE
= 3 << 2,
284 MLX4_WQE_CTRL_SOLICITED
= 1 << 1,
285 MLX4_WQE_CTRL_IP_CSUM
= 1 << 4,
286 MLX4_WQE_CTRL_TCP_UDP_CSUM
= 1 << 5,
287 MLX4_WQE_CTRL_INS_CVLAN
= 1 << 6,
288 MLX4_WQE_CTRL_INS_SVLAN
= 1 << 7,
289 MLX4_WQE_CTRL_STRONG_ORDER
= 1 << 7,
290 MLX4_WQE_CTRL_FORCE_LOOPBACK
= 1 << 0,
293 struct mlx4_wqe_ctrl_seg
{
304 * High 24 bits are SRC remote buffer; low 8 bits are flags:
305 * [7] SO (strong ordering)
306 * [5] TCP/UDP checksum
308 * [3:2] C (generate completion queue entry)
309 * [1] SE (solicited event)
310 * [0] FL (force loopback)
314 __be16 srcrb_flags16
[2];
317 * imm is immediate data for send/RDMA write w/ immediate;
318 * also invalidation key for send with invalidate; input
319 * modifier for WQEs on CCQs.
325 MLX4_WQE_MLX_VL15
= 1 << 17,
326 MLX4_WQE_MLX_SLR
= 1 << 16
329 struct mlx4_wqe_mlx_seg
{
339 * [15:12] static rate
343 * [0] FL (force loopback)
350 struct mlx4_wqe_datagram_seg
{
358 struct mlx4_wqe_lso_seg
{
363 enum mlx4_wqe_bind_seg_flags2
{
364 MLX4_WQE_BIND_ZERO_BASED
= (1 << 30),
365 MLX4_WQE_BIND_TYPE_2
= (1 << 31),
368 struct mlx4_wqe_bind_seg
{
378 MLX4_WQE_FMR_PERM_LOCAL_READ
= 1 << 27,
379 MLX4_WQE_FMR_PERM_LOCAL_WRITE
= 1 << 28,
380 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ
= 1 << 29,
381 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE
= 1 << 30,
382 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC
= 1 << 31
385 struct mlx4_wqe_fmr_seg
{
396 struct mlx4_wqe_fmr_ext_seg
{
402 __be32 wire_ref_tag_base
;
403 __be32 mem_ref_tag_base
;
406 struct mlx4_wqe_local_inval_seg
{
413 struct mlx4_wqe_raddr_seg
{
419 struct mlx4_wqe_atomic_seg
{
424 struct mlx4_wqe_masked_atomic_seg
{
427 __be64 swap_add_mask
;
431 struct mlx4_wqe_data_seg
{
438 MLX4_INLINE_ALIGN
= 64,
439 MLX4_INLINE_SEG
= 1 << 31,
442 struct mlx4_wqe_inline_seg
{
446 enum mlx4_update_qp_attr
{
447 MLX4_UPDATE_QP_SMAC
= 1 << 0,
448 MLX4_UPDATE_QP_VSD
= 1 << 1,
449 MLX4_UPDATE_QP_RATE_LIMIT
= 1 << 2,
450 MLX4_UPDATE_QP_QOS_VPORT
= 1 << 3,
451 MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB
= 1 << 4,
452 MLX4_UPDATE_QP_SUPPORTED_ATTRS
= (1 << 5) - 1
455 enum mlx4_update_qp_params_flags
{
456 MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB
= 1 << 0,
457 MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE
= 1 << 1,
460 struct mlx4_update_qp_params
{
468 int mlx4_update_qp(struct mlx4_dev
*dev
, u32 qpn
,
469 enum mlx4_update_qp_attr attr
,
470 struct mlx4_update_qp_params
*params
);
471 int mlx4_qp_modify(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
472 enum mlx4_qp_state cur_state
, enum mlx4_qp_state new_state
,
473 struct mlx4_qp_context
*context
, enum mlx4_qp_optpar optpar
,
474 int sqd_event
, struct mlx4_qp
*qp
);
476 int mlx4_qp_query(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
477 struct mlx4_qp_context
*context
);
479 int mlx4_qp_to_ready(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
480 struct mlx4_qp_context
*context
,
481 struct mlx4_qp
*qp
, enum mlx4_qp_state
*qp_state
);
483 static inline struct mlx4_qp
*__mlx4_qp_lookup(struct mlx4_dev
*dev
, u32 qpn
)
485 return radix_tree_lookup(&dev
->qp_table_tree
, qpn
& (dev
->caps
.num_qps
- 1));
488 void mlx4_qp_remove(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
490 #endif /* MLX4_QP_H */