2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #error Host endianness not defined
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
68 /* insert a value to a struct */
69 #define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87 __mlx5_mask(typ, fld))
89 #define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
95 #define MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
103 #define MLX5_GET64_PR(typ, p, fld) ({ \
104 u64 ___t = MLX5_GET64(typ, p, fld); \
105 pr_debug(#fld " = 0x%llx\n", ___t); \
109 /* Big endian getters */
110 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
111 __mlx5_64_off(typ, fld)))
113 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
115 switch (sizeof(tmp)) { \
117 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
120 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
123 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
126 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
133 MLX5_MAX_COMMANDS
= 32,
134 MLX5_CMD_DATA_BLOCK_SIZE
= 512,
135 MLX5_PCI_CMD_XPORT
= 7,
136 MLX5_MKEY_BSF_OCTO_SIZE
= 4,
141 MLX5_EXTENDED_UD_AV
= 0x80000000,
145 MLX5_CQ_STATE_ARMED
= 9,
146 MLX5_CQ_STATE_ALWAYS_ARMED
= 0xb,
147 MLX5_CQ_STATE_FIRED
= 0xa,
151 MLX5_STAT_RATE_OFFSET
= 5,
155 MLX5_INLINE_SEG
= 0x80000000,
159 MLX5_HW_START_PADDING
= MLX5_INLINE_SEG
,
163 MLX5_MIN_PKEY_TABLE_SIZE
= 128,
164 MLX5_MAX_LOG_PKEY_TABLE
= 5,
168 MLX5_MKEY_INBOX_PG_ACCESS
= 1 << 31
172 MLX5_PFAULT_SUBTYPE_WQE
= 0,
173 MLX5_PFAULT_SUBTYPE_RDMA
= 1,
177 MLX5_PERM_LOCAL_READ
= 1 << 2,
178 MLX5_PERM_LOCAL_WRITE
= 1 << 3,
179 MLX5_PERM_REMOTE_READ
= 1 << 4,
180 MLX5_PERM_REMOTE_WRITE
= 1 << 5,
181 MLX5_PERM_ATOMIC
= 1 << 6,
182 MLX5_PERM_UMR_EN
= 1 << 7,
186 MLX5_PCIE_CTRL_SMALL_FENCE
= 1 << 0,
187 MLX5_PCIE_CTRL_RELAXED_ORDERING
= 1 << 2,
188 MLX5_PCIE_CTRL_NO_SNOOP
= 1 << 3,
189 MLX5_PCIE_CTRL_TLP_PROCE_EN
= 1 << 6,
190 MLX5_PCIE_CTRL_TPH_MASK
= 3 << 4,
194 MLX5_ACCESS_MODE_PA
= 0,
195 MLX5_ACCESS_MODE_MTT
= 1,
196 MLX5_ACCESS_MODE_KLM
= 2
200 MLX5_MKEY_REMOTE_INVAL
= 1 << 24,
201 MLX5_MKEY_FLAG_SYNC_UMR
= 1 << 29,
202 MLX5_MKEY_BSF_EN
= 1 << 30,
203 MLX5_MKEY_LEN64
= 1 << 31,
212 MLX5_BF_REGS_PER_PAGE
= 4,
213 MLX5_MAX_UAR_PAGES
= 1 << 8,
214 MLX5_NON_FP_BF_REGS_PER_PAGE
= 2,
215 MLX5_MAX_UUARS
= MLX5_MAX_UAR_PAGES
* MLX5_NON_FP_BF_REGS_PER_PAGE
,
219 MLX5_MKEY_MASK_LEN
= 1ull << 0,
220 MLX5_MKEY_MASK_PAGE_SIZE
= 1ull << 1,
221 MLX5_MKEY_MASK_START_ADDR
= 1ull << 6,
222 MLX5_MKEY_MASK_PD
= 1ull << 7,
223 MLX5_MKEY_MASK_EN_RINVAL
= 1ull << 8,
224 MLX5_MKEY_MASK_EN_SIGERR
= 1ull << 9,
225 MLX5_MKEY_MASK_BSF_EN
= 1ull << 12,
226 MLX5_MKEY_MASK_KEY
= 1ull << 13,
227 MLX5_MKEY_MASK_QPN
= 1ull << 14,
228 MLX5_MKEY_MASK_LR
= 1ull << 17,
229 MLX5_MKEY_MASK_LW
= 1ull << 18,
230 MLX5_MKEY_MASK_RR
= 1ull << 19,
231 MLX5_MKEY_MASK_RW
= 1ull << 20,
232 MLX5_MKEY_MASK_A
= 1ull << 21,
233 MLX5_MKEY_MASK_SMALL_FENCE
= 1ull << 23,
234 MLX5_MKEY_MASK_FREE
= 1ull << 29,
238 MLX5_UMR_TRANSLATION_OFFSET_EN
= (1 << 4),
240 MLX5_UMR_CHECK_NOT_FREE
= (1 << 5),
241 MLX5_UMR_CHECK_FREE
= (2 << 5),
243 MLX5_UMR_INLINE
= (1 << 7),
246 #define MLX5_UMR_MTT_ALIGNMENT 0x40
247 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
248 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
250 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
253 MLX5_EVENT_QUEUE_TYPE_QP
= 0,
254 MLX5_EVENT_QUEUE_TYPE_RQ
= 1,
255 MLX5_EVENT_QUEUE_TYPE_SQ
= 2,
259 MLX5_EVENT_TYPE_COMP
= 0x0,
261 MLX5_EVENT_TYPE_PATH_MIG
= 0x01,
262 MLX5_EVENT_TYPE_COMM_EST
= 0x02,
263 MLX5_EVENT_TYPE_SQ_DRAINED
= 0x03,
264 MLX5_EVENT_TYPE_SRQ_LAST_WQE
= 0x13,
265 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT
= 0x14,
267 MLX5_EVENT_TYPE_CQ_ERROR
= 0x04,
268 MLX5_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
269 MLX5_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
270 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
271 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
272 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
274 MLX5_EVENT_TYPE_INTERNAL_ERROR
= 0x08,
275 MLX5_EVENT_TYPE_PORT_CHANGE
= 0x09,
276 MLX5_EVENT_TYPE_GPIO_EVENT
= 0x15,
277 MLX5_EVENT_TYPE_REMOTE_CONFIG
= 0x19,
279 MLX5_EVENT_TYPE_DB_BF_CONGESTION
= 0x1a,
280 MLX5_EVENT_TYPE_STALL_EVENT
= 0x1b,
282 MLX5_EVENT_TYPE_CMD
= 0x0a,
283 MLX5_EVENT_TYPE_PAGE_REQUEST
= 0xb,
285 MLX5_EVENT_TYPE_PAGE_FAULT
= 0xc,
286 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE
= 0xd,
290 MLX5_PORT_CHANGE_SUBTYPE_DOWN
= 1,
291 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE
= 4,
292 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED
= 5,
293 MLX5_PORT_CHANGE_SUBTYPE_LID
= 6,
294 MLX5_PORT_CHANGE_SUBTYPE_PKEY
= 7,
295 MLX5_PORT_CHANGE_SUBTYPE_GUID
= 8,
296 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG
= 9,
300 MLX5_DEV_CAP_FLAG_XRC
= 1LL << 3,
301 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
302 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
303 MLX5_DEV_CAP_FLAG_APM
= 1LL << 17,
304 MLX5_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
305 MLX5_DEV_CAP_FLAG_BLOCK_MCAST
= 1LL << 23,
306 MLX5_DEV_CAP_FLAG_ON_DMND_PG
= 1LL << 24,
307 MLX5_DEV_CAP_FLAG_CQ_MODER
= 1LL << 29,
308 MLX5_DEV_CAP_FLAG_RESIZE_CQ
= 1LL << 30,
309 MLX5_DEV_CAP_FLAG_DCT
= 1LL << 37,
310 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER
= 1LL << 40,
311 MLX5_DEV_CAP_FLAG_CMDIF_CSUM
= 3LL << 46,
315 MLX5_ROCE_VERSION_1
= 0,
316 MLX5_ROCE_VERSION_2
= 2,
320 MLX5_ROCE_VERSION_1_CAP
= 1 << MLX5_ROCE_VERSION_1
,
321 MLX5_ROCE_VERSION_2_CAP
= 1 << MLX5_ROCE_VERSION_2
,
325 MLX5_ROCE_L3_TYPE_IPV4
= 0,
326 MLX5_ROCE_L3_TYPE_IPV6
= 1,
330 MLX5_ROCE_L3_TYPE_IPV4_CAP
= 1 << 1,
331 MLX5_ROCE_L3_TYPE_IPV6_CAP
= 1 << 2,
335 MLX5_OPCODE_NOP
= 0x00,
336 MLX5_OPCODE_SEND_INVAL
= 0x01,
337 MLX5_OPCODE_RDMA_WRITE
= 0x08,
338 MLX5_OPCODE_RDMA_WRITE_IMM
= 0x09,
339 MLX5_OPCODE_SEND
= 0x0a,
340 MLX5_OPCODE_SEND_IMM
= 0x0b,
341 MLX5_OPCODE_LSO
= 0x0e,
342 MLX5_OPCODE_RDMA_READ
= 0x10,
343 MLX5_OPCODE_ATOMIC_CS
= 0x11,
344 MLX5_OPCODE_ATOMIC_FA
= 0x12,
345 MLX5_OPCODE_ATOMIC_MASKED_CS
= 0x14,
346 MLX5_OPCODE_ATOMIC_MASKED_FA
= 0x15,
347 MLX5_OPCODE_BIND_MW
= 0x18,
348 MLX5_OPCODE_CONFIG_CMD
= 0x1f,
350 MLX5_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
351 MLX5_RECV_OPCODE_SEND
= 0x01,
352 MLX5_RECV_OPCODE_SEND_IMM
= 0x02,
353 MLX5_RECV_OPCODE_SEND_INVAL
= 0x03,
355 MLX5_CQE_OPCODE_ERROR
= 0x1e,
356 MLX5_CQE_OPCODE_RESIZE
= 0x16,
358 MLX5_OPCODE_SET_PSV
= 0x20,
359 MLX5_OPCODE_GET_PSV
= 0x21,
360 MLX5_OPCODE_CHECK_PSV
= 0x22,
361 MLX5_OPCODE_RGET_PSV
= 0x26,
362 MLX5_OPCODE_RCHECK_PSV
= 0x27,
364 MLX5_OPCODE_UMR
= 0x25,
369 MLX5_SET_PORT_RESET_QKEY
= 0,
370 MLX5_SET_PORT_GUID0
= 16,
371 MLX5_SET_PORT_NODE_GUID
= 17,
372 MLX5_SET_PORT_SYS_GUID
= 18,
373 MLX5_SET_PORT_GID_TABLE
= 19,
374 MLX5_SET_PORT_PKEY_TABLE
= 20,
378 MLX5_BW_NO_LIMIT
= 0,
379 MLX5_100_MBPS_UNIT
= 3,
384 MLX5_MAX_PAGE_SHIFT
= 31
388 MLX5_ADAPTER_PAGE_SHIFT
= 12,
389 MLX5_ADAPTER_PAGE_SIZE
= 1 << MLX5_ADAPTER_PAGE_SHIFT
,
393 MLX5_CAP_OFF_CMDIF_CSUM
= 46,
398 * Max wqe size for rdma read is 512 bytes, so this
399 * limits our max_sge_rd as the wqe needs to fit:
400 * - ctrl segment (16 bytes)
401 * - rdma segment (16 bytes)
402 * - scatter elements (16 bytes each)
404 MLX5_MAX_SGE_RD
= (512 - 16 - 16) / 16
407 struct mlx5_inbox_hdr
{
413 struct mlx5_outbox_hdr
{
419 struct mlx5_cmd_query_adapter_mbox_in
{
420 struct mlx5_inbox_hdr hdr
;
424 struct mlx5_cmd_query_adapter_mbox_out
{
425 struct mlx5_outbox_hdr hdr
;
429 __be16 vsd_vendor_id
;
434 enum mlx5_odp_transport_cap_bits
{
435 MLX5_ODP_SUPPORT_SEND
= 1 << 31,
436 MLX5_ODP_SUPPORT_RECV
= 1 << 30,
437 MLX5_ODP_SUPPORT_WRITE
= 1 << 29,
438 MLX5_ODP_SUPPORT_READ
= 1 << 28,
441 struct mlx5_odp_caps
{
447 } per_transport_caps
;
448 char reserved2
[0xe4];
451 struct mlx5_cmd_init_hca_mbox_in
{
452 struct mlx5_inbox_hdr hdr
;
458 struct mlx5_cmd_init_hca_mbox_out
{
459 struct mlx5_outbox_hdr hdr
;
463 struct mlx5_cmd_teardown_hca_mbox_in
{
464 struct mlx5_inbox_hdr hdr
;
470 struct mlx5_cmd_teardown_hca_mbox_out
{
471 struct mlx5_outbox_hdr hdr
;
475 struct mlx5_cmd_layout
{
491 struct health_buffer
{
492 __be32 assert_var
[5];
494 __be32 assert_exit_ptr
;
495 __be32 assert_callra
;
505 struct mlx5_init_seg
{
507 __be32 cmdif_rev_fw_sub
;
510 __be32 cmdq_addr_l_sz
;
514 struct health_buffer health
;
516 __be32 internal_timer_h
;
517 __be32 internal_timer_l
;
519 __be32 health_counter
;
522 __be32 ieee1588_clk_type
;
526 struct mlx5_eqe_comp
{
531 struct mlx5_eqe_qp_srq
{
538 struct mlx5_eqe_cq_err
{
544 struct mlx5_eqe_port_state
{
549 struct mlx5_eqe_gpio
{
554 struct mlx5_eqe_congestion
{
560 struct mlx5_eqe_stall_vl
{
565 struct mlx5_eqe_cmd
{
570 struct mlx5_eqe_page_req
{
577 struct mlx5_eqe_page_fault
{
578 __be32 bytes_committed
;
584 __be16 packet_length
;
590 __be16 packet_length
;
598 struct mlx5_eqe_vport_change
{
606 struct mlx5_eqe_cmd cmd
;
607 struct mlx5_eqe_comp comp
;
608 struct mlx5_eqe_qp_srq qp_srq
;
609 struct mlx5_eqe_cq_err cq_err
;
610 struct mlx5_eqe_port_state port
;
611 struct mlx5_eqe_gpio gpio
;
612 struct mlx5_eqe_congestion cong
;
613 struct mlx5_eqe_stall_vl stall_vl
;
614 struct mlx5_eqe_page_req req_pages
;
615 struct mlx5_eqe_page_fault page_fault
;
616 struct mlx5_eqe_vport_change vport_change
;
631 struct mlx5_cmd_prot_block
{
632 u8 data
[MLX5_CMD_DATA_BLOCK_SIZE
];
643 MLX5_CQE_SYND_FLUSHED_IN_ERROR
= 5,
646 struct mlx5_err_cqe
{
652 __be32 s_wqe_opcode_qpn
;
659 u8 outer_l3_tunneled
;
662 u8 lro_tcppsh_abort_dupack
;
665 __be32 lro_ack_seq_num
;
666 __be32 rss_hash_result
;
676 __be32 srqn
; /* [31:24]: lro_num_seg, [23:0]: srqn */
677 __be32 imm_inval_pkey
;
688 struct mlx5_mini_cqe8
{
690 __be32 rx_hash_result
;
706 MLX5_INLINE_DATA32_SEG
,
707 MLX5_INLINE_DATA64_SEG
,
712 MLX5_CQE_FORMAT_CSUM
= 0x1,
715 #define MLX5_MINI_CQE_ARRAY_SIZE 8
717 static inline int mlx5_get_cqe_format(struct mlx5_cqe64
*cqe
)
719 return (cqe
->op_own
>> 2) & 0x3;
722 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64
*cqe
)
724 return (cqe
->lro_tcppsh_abort_dupack
>> 6) & 1;
727 static inline u8
get_cqe_l4_hdr_type(struct mlx5_cqe64
*cqe
)
729 return (cqe
->l4_l3_hdr_type
>> 4) & 0x7;
732 static inline u8
get_cqe_l3_hdr_type(struct mlx5_cqe64
*cqe
)
734 return (cqe
->l4_l3_hdr_type
>> 2) & 0x3;
737 static inline u8
cqe_is_tunneled(struct mlx5_cqe64
*cqe
)
739 return cqe
->outer_l3_tunneled
& 0x1;
742 static inline int cqe_has_vlan(struct mlx5_cqe64
*cqe
)
744 return !!(cqe
->l4_l3_hdr_type
& 0x1);
747 static inline u64
get_cqe_ts(struct mlx5_cqe64
*cqe
)
751 hi
= be32_to_cpu(cqe
->timestamp_h
);
752 lo
= be32_to_cpu(cqe
->timestamp_l
);
754 return (u64
)lo
| ((u64
)hi
<< 32);
757 struct mpwrq_cqe_bc
{
758 __be16 filler_consumed_strides
;
762 static inline u16
mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64
*cqe
)
764 struct mpwrq_cqe_bc
*bc
= (struct mpwrq_cqe_bc
*)&cqe
->byte_cnt
;
766 return be16_to_cpu(bc
->byte_cnt
);
769 static inline u16
mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc
*bc
)
771 return 0x7fff & be16_to_cpu(bc
->filler_consumed_strides
);
774 static inline u16
mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64
*cqe
)
776 struct mpwrq_cqe_bc
*bc
= (struct mpwrq_cqe_bc
*)&cqe
->byte_cnt
;
778 return mpwrq_get_cqe_bc_consumed_strides(bc
);
781 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64
*cqe
)
783 struct mpwrq_cqe_bc
*bc
= (struct mpwrq_cqe_bc
*)&cqe
->byte_cnt
;
785 return 0x8000 & be16_to_cpu(bc
->filler_consumed_strides
);
788 static inline u16
mpwrq_get_cqe_stride_index(struct mlx5_cqe64
*cqe
)
790 return be16_to_cpu(cqe
->wqe_counter
);
794 CQE_L4_HDR_TYPE_NONE
= 0x0,
795 CQE_L4_HDR_TYPE_TCP_NO_ACK
= 0x1,
796 CQE_L4_HDR_TYPE_UDP
= 0x2,
797 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA
= 0x3,
798 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA
= 0x4,
802 CQE_RSS_HTYPE_IP
= 0x3 << 6,
803 CQE_RSS_HTYPE_L4
= 0x3 << 2,
807 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH
= 0x0,
808 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6
= 0x1,
809 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4
= 0x2,
818 struct mlx5_sig_err_cqe
{
820 __be32 expected_trans_sig
;
821 __be32 actual_trans_sig
;
822 __be32 expected_reftag
;
823 __be32 actual_reftag
;
835 struct mlx5_wqe_srq_next_seg
{
837 __be16 next_wqe_index
;
848 union mlx5_ext_cqe inl_grh
;
849 struct mlx5_cqe64 cqe64
;
852 struct mlx5_srq_ctx
{
867 struct mlx5_create_srq_mbox_in
{
868 struct mlx5_inbox_hdr hdr
;
871 struct mlx5_srq_ctx ctx
;
876 struct mlx5_create_srq_mbox_out
{
877 struct mlx5_outbox_hdr hdr
;
882 struct mlx5_destroy_srq_mbox_in
{
883 struct mlx5_inbox_hdr hdr
;
888 struct mlx5_destroy_srq_mbox_out
{
889 struct mlx5_outbox_hdr hdr
;
893 struct mlx5_query_srq_mbox_in
{
894 struct mlx5_inbox_hdr hdr
;
899 struct mlx5_query_srq_mbox_out
{
900 struct mlx5_outbox_hdr hdr
;
902 struct mlx5_srq_ctx ctx
;
907 struct mlx5_arm_srq_mbox_in
{
908 struct mlx5_inbox_hdr hdr
;
914 struct mlx5_arm_srq_mbox_out
{
915 struct mlx5_outbox_hdr hdr
;
919 struct mlx5_cq_context
{
926 __be32 log_sz_usr_page
;
933 __be32 last_notified_index
;
934 __be32 solicit_producer_index
;
935 __be32 consumer_counter
;
936 __be32 producer_counter
;
938 __be64 db_record_addr
;
941 struct mlx5_create_cq_mbox_in
{
942 struct mlx5_inbox_hdr hdr
;
945 struct mlx5_cq_context ctx
;
950 struct mlx5_create_cq_mbox_out
{
951 struct mlx5_outbox_hdr hdr
;
956 struct mlx5_destroy_cq_mbox_in
{
957 struct mlx5_inbox_hdr hdr
;
962 struct mlx5_destroy_cq_mbox_out
{
963 struct mlx5_outbox_hdr hdr
;
967 struct mlx5_query_cq_mbox_in
{
968 struct mlx5_inbox_hdr hdr
;
973 struct mlx5_query_cq_mbox_out
{
974 struct mlx5_outbox_hdr hdr
;
976 struct mlx5_cq_context ctx
;
981 struct mlx5_modify_cq_mbox_in
{
982 struct mlx5_inbox_hdr hdr
;
985 struct mlx5_cq_context ctx
;
990 struct mlx5_modify_cq_mbox_out
{
991 struct mlx5_outbox_hdr hdr
;
995 struct mlx5_enable_hca_mbox_in
{
996 struct mlx5_inbox_hdr hdr
;
1000 struct mlx5_enable_hca_mbox_out
{
1001 struct mlx5_outbox_hdr hdr
;
1005 struct mlx5_disable_hca_mbox_in
{
1006 struct mlx5_inbox_hdr hdr
;
1010 struct mlx5_disable_hca_mbox_out
{
1011 struct mlx5_outbox_hdr hdr
;
1015 struct mlx5_eq_context
{
1021 __be32 log_sz_usr_page
;
1026 __be32 consumer_counter
;
1027 __be32 produser_counter
;
1031 struct mlx5_create_eq_mbox_in
{
1032 struct mlx5_inbox_hdr hdr
;
1036 struct mlx5_eq_context ctx
;
1043 struct mlx5_create_eq_mbox_out
{
1044 struct mlx5_outbox_hdr hdr
;
1050 struct mlx5_destroy_eq_mbox_in
{
1051 struct mlx5_inbox_hdr hdr
;
1057 struct mlx5_destroy_eq_mbox_out
{
1058 struct mlx5_outbox_hdr hdr
;
1062 struct mlx5_map_eq_mbox_in
{
1063 struct mlx5_inbox_hdr hdr
;
1071 struct mlx5_map_eq_mbox_out
{
1072 struct mlx5_outbox_hdr hdr
;
1076 struct mlx5_query_eq_mbox_in
{
1077 struct mlx5_inbox_hdr hdr
;
1083 struct mlx5_query_eq_mbox_out
{
1084 struct mlx5_outbox_hdr hdr
;
1086 struct mlx5_eq_context ctx
;
1090 MLX5_MKEY_STATUS_FREE
= 1 << 6,
1093 struct mlx5_mkey_seg
{
1094 /* This is a two bit field occupying bits 31-30.
1095 * bit 31 is always 0,
1096 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
1107 __be32 bsfs_octo_size
;
1109 __be32 xlt_oct_size
;
1115 struct mlx5_query_special_ctxs_mbox_in
{
1116 struct mlx5_inbox_hdr hdr
;
1120 struct mlx5_query_special_ctxs_mbox_out
{
1121 struct mlx5_outbox_hdr hdr
;
1122 __be32 dump_fill_mkey
;
1123 __be32 reserved_lkey
;
1126 struct mlx5_create_mkey_mbox_in
{
1127 struct mlx5_inbox_hdr hdr
;
1128 __be32 input_mkey_index
;
1130 struct mlx5_mkey_seg seg
;
1132 __be32 xlat_oct_act_size
;
1138 struct mlx5_create_mkey_mbox_out
{
1139 struct mlx5_outbox_hdr hdr
;
1144 struct mlx5_destroy_mkey_mbox_in
{
1145 struct mlx5_inbox_hdr hdr
;
1150 struct mlx5_destroy_mkey_mbox_out
{
1151 struct mlx5_outbox_hdr hdr
;
1155 struct mlx5_query_mkey_mbox_in
{
1156 struct mlx5_inbox_hdr hdr
;
1160 struct mlx5_query_mkey_mbox_out
{
1161 struct mlx5_outbox_hdr hdr
;
1165 struct mlx5_modify_mkey_mbox_in
{
1166 struct mlx5_inbox_hdr hdr
;
1171 struct mlx5_modify_mkey_mbox_out
{
1172 struct mlx5_outbox_hdr hdr
;
1176 struct mlx5_dump_mkey_mbox_in
{
1177 struct mlx5_inbox_hdr hdr
;
1180 struct mlx5_dump_mkey_mbox_out
{
1181 struct mlx5_outbox_hdr hdr
;
1185 struct mlx5_mad_ifc_mbox_in
{
1186 struct mlx5_inbox_hdr hdr
;
1194 struct mlx5_mad_ifc_mbox_out
{
1195 struct mlx5_outbox_hdr hdr
;
1200 struct mlx5_access_reg_mbox_in
{
1201 struct mlx5_inbox_hdr hdr
;
1208 struct mlx5_access_reg_mbox_out
{
1209 struct mlx5_outbox_hdr hdr
;
1214 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1217 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO
= 1 << 0
1220 struct mlx5_allocate_psv_in
{
1221 struct mlx5_inbox_hdr hdr
;
1226 struct mlx5_allocate_psv_out
{
1227 struct mlx5_outbox_hdr hdr
;
1232 struct mlx5_destroy_psv_in
{
1233 struct mlx5_inbox_hdr hdr
;
1238 struct mlx5_destroy_psv_out
{
1239 struct mlx5_outbox_hdr hdr
;
1243 #define MLX5_CMD_OP_MAX 0x920
1246 VPORT_STATE_DOWN
= 0x0,
1247 VPORT_STATE_UP
= 0x1,
1251 MLX5_ESW_VPORT_ADMIN_STATE_DOWN
= 0x0,
1252 MLX5_ESW_VPORT_ADMIN_STATE_UP
= 0x1,
1253 MLX5_ESW_VPORT_ADMIN_STATE_AUTO
= 0x2,
1257 MLX5_L3_PROT_TYPE_IPV4
= 0,
1258 MLX5_L3_PROT_TYPE_IPV6
= 1,
1262 MLX5_L4_PROT_TYPE_TCP
= 0,
1263 MLX5_L4_PROT_TYPE_UDP
= 1,
1267 MLX5_HASH_FIELD_SEL_SRC_IP
= 1 << 0,
1268 MLX5_HASH_FIELD_SEL_DST_IP
= 1 << 1,
1269 MLX5_HASH_FIELD_SEL_L4_SPORT
= 1 << 2,
1270 MLX5_HASH_FIELD_SEL_L4_DPORT
= 1 << 3,
1271 MLX5_HASH_FIELD_SEL_IPSEC_SPI
= 1 << 4,
1275 MLX5_MATCH_OUTER_HEADERS
= 1 << 0,
1276 MLX5_MATCH_MISC_PARAMETERS
= 1 << 1,
1277 MLX5_MATCH_INNER_HEADERS
= 1 << 2,
1282 MLX5_FLOW_TABLE_TYPE_NIC_RCV
= 0,
1283 MLX5_FLOW_TABLE_TYPE_ESWITCH
= 4,
1287 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT
= 0,
1288 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE
= 1,
1289 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR
= 2,
1292 enum mlx5_list_type
{
1293 MLX5_NVPRT_LIST_TYPE_UC
= 0x0,
1294 MLX5_NVPRT_LIST_TYPE_MC
= 0x1,
1295 MLX5_NVPRT_LIST_TYPE_VLAN
= 0x2,
1299 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
1300 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM
= 0x1,
1303 enum mlx5_wol_mode
{
1304 MLX5_WOL_DISABLE
= 0,
1305 MLX5_WOL_SECURED_MAGIC
= 1 << 1,
1306 MLX5_WOL_MAGIC
= 1 << 2,
1307 MLX5_WOL_ARP
= 1 << 3,
1308 MLX5_WOL_BROADCAST
= 1 << 4,
1309 MLX5_WOL_MULTICAST
= 1 << 5,
1310 MLX5_WOL_UNICAST
= 1 << 6,
1311 MLX5_WOL_PHY_ACTIVITY
= 1 << 7,
1317 enum mlx5_cap_mode
{
1318 HCA_CAP_OPMOD_GET_MAX
= 0,
1319 HCA_CAP_OPMOD_GET_CUR
= 1,
1322 enum mlx5_cap_type
{
1323 MLX5_CAP_GENERAL
= 0,
1324 MLX5_CAP_ETHERNET_OFFLOADS
,
1328 MLX5_CAP_IPOIB_OFFLOADS
,
1329 MLX5_CAP_EOIB_OFFLOADS
,
1330 MLX5_CAP_FLOW_TABLE
,
1331 MLX5_CAP_ESWITCH_FLOW_TABLE
,
1334 MLX5_CAP_VECTOR_CALC
,
1335 /* NUM OF CAP Types */
1339 /* GET Dev Caps macros */
1340 #define MLX5_CAP_GEN(mdev, cap) \
1341 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1343 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1344 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1346 #define MLX5_CAP_ETH(mdev, cap) \
1347 MLX5_GET(per_protocol_networking_offload_caps,\
1348 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1350 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1351 MLX5_GET(per_protocol_networking_offload_caps,\
1352 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1354 #define MLX5_CAP_ROCE(mdev, cap) \
1355 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1357 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1358 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1360 #define MLX5_CAP_ATOMIC(mdev, cap) \
1361 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1363 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1364 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1366 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1367 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1369 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1370 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1372 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1373 MLX5_GET(flow_table_eswitch_cap, \
1374 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1376 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1377 MLX5_GET(flow_table_eswitch_cap, \
1378 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1380 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1381 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1383 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1384 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1386 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1387 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1389 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1390 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1392 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1393 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1395 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1396 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1398 #define MLX5_CAP_ESW(mdev, cap) \
1399 MLX5_GET(e_switch_cap, \
1400 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1402 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1403 MLX5_GET(e_switch_cap, \
1404 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1406 #define MLX5_CAP_ODP(mdev, cap)\
1407 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1409 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1410 MLX5_GET(vector_calc_cap, \
1411 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1414 MLX5_CMD_STAT_OK
= 0x0,
1415 MLX5_CMD_STAT_INT_ERR
= 0x1,
1416 MLX5_CMD_STAT_BAD_OP_ERR
= 0x2,
1417 MLX5_CMD_STAT_BAD_PARAM_ERR
= 0x3,
1418 MLX5_CMD_STAT_BAD_SYS_STATE_ERR
= 0x4,
1419 MLX5_CMD_STAT_BAD_RES_ERR
= 0x5,
1420 MLX5_CMD_STAT_RES_BUSY
= 0x6,
1421 MLX5_CMD_STAT_LIM_ERR
= 0x8,
1422 MLX5_CMD_STAT_BAD_RES_STATE_ERR
= 0x9,
1423 MLX5_CMD_STAT_IX_ERR
= 0xa,
1424 MLX5_CMD_STAT_NO_RES_ERR
= 0xf,
1425 MLX5_CMD_STAT_BAD_INP_LEN_ERR
= 0x50,
1426 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR
= 0x51,
1427 MLX5_CMD_STAT_BAD_QP_STATE_ERR
= 0x10,
1428 MLX5_CMD_STAT_BAD_PKT_ERR
= 0x30,
1429 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR
= 0x40,
1433 MLX5_IEEE_802_3_COUNTERS_GROUP
= 0x0,
1434 MLX5_RFC_2863_COUNTERS_GROUP
= 0x1,
1435 MLX5_RFC_2819_COUNTERS_GROUP
= 0x2,
1436 MLX5_RFC_3635_COUNTERS_GROUP
= 0x3,
1437 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP
= 0x5,
1438 MLX5_PER_PRIORITY_COUNTERS_GROUP
= 0x10,
1439 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP
= 0x11,
1440 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
= 0x12,
1441 MLX5_INFINIBAND_PORT_COUNTERS_GROUP
= 0x20,
1444 static inline u16
mlx5_to_sw_pkey_sz(int pkey_sz
)
1446 if (pkey_sz
> MLX5_MAX_LOG_PKEY_TABLE
)
1448 return MLX5_MIN_PKEY_TABLE_SIZE
<< pkey_sz
;
1451 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1452 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1453 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1454 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1455 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1456 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1458 #endif /* MLX5_DEVICE_H */