include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38 #include <linux/mlx5/mlx5_ifc.h>
  39
  40 #if defined(__LITTLE_ENDIAN)
  41 #define MLX5_SET_HOST_ENDIANNESS        0
  42 #elif defined(__BIG_ENDIAN)
  43 #define MLX5_SET_HOST_ENDIANNESS        0x80
  44 #else
  45 #error Host endianness not defined
  46 #endif
  47
  48 /* helper macros */
  49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  58
  59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
  63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
  64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
  65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  67
  68 /* insert a value to a struct */
  69 #define MLX5_SET(typ, p, fld, v) do { \
  70         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  71         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  72         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  73                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  74                      << __mlx5_dw_bit_off(typ, fld))); \
  75 } while (0)
  76
  77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
  78         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  79         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  80         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  81                      (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
  82                      << __mlx5_dw_bit_off(typ, fld))); \
  83 } while (0)
  84
  85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  87 __mlx5_mask(typ, fld))
  88
  89 #define MLX5_GET_PR(typ, p, fld) ({ \
  90         u32 ___t = MLX5_GET(typ, p, fld); \
  91         pr_debug(#fld " = 0x%x\n", ___t); \
  92         ___t; \
  93 })
  94
  95 #define __MLX5_SET64(typ, p, fld, v) do { \
  96         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  97         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  98 } while (0)
  99
 100 #define MLX5_SET64(typ, p, fld, v) do { \
 101         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 102         __MLX5_SET64(typ, p, fld, v); \
 103 } while (0)
 104
 105 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
 106         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 107         __MLX5_SET64(typ, p, fld[idx], v); \
 108 } while (0)
 109
 110 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 111
 112 #define MLX5_GET64_PR(typ, p, fld) ({ \
 113         u64 ___t = MLX5_GET64(typ, p, fld); \
 114         pr_debug(#fld " = 0x%llx\n", ___t); \
 115         ___t; \
 116 })
 117
 118 /* Big endian getters */
 119 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
 120         __mlx5_64_off(typ, fld)))
 121
 122 #define MLX5_GET_BE(type_t, typ, p, fld) ({                               \
 123                 type_t tmp;                                               \
 124                 switch (sizeof(tmp)) {                                    \
 125                 case sizeof(u8):                                          \
 126                         tmp = (__force type_t)MLX5_GET(typ, p, fld);      \
 127                         break;                                            \
 128                 case sizeof(u16):                                         \
 129                         tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
 130                         break;                                            \
 131                 case sizeof(u32):                                         \
 132                         tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
 133                         break;                                            \
 134                 case sizeof(u64):                                         \
 135                         tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
 136                         break;                                            \
 137                         }                                                 \
 138                 tmp;                                                      \
 139                 })
 140
 141 enum mlx5_inline_modes {
 142         MLX5_INLINE_MODE_NONE,
 143         MLX5_INLINE_MODE_L2,
 144         MLX5_INLINE_MODE_IP,
 145         MLX5_INLINE_MODE_TCP_UDP,
 146 };
 147
 148 enum {
 149         MLX5_MAX_COMMANDS               = 32,
 150         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
 151         MLX5_PCI_CMD_XPORT              = 7,
 152         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
 153         MLX5_MAX_PSVS                   = 4,
 154 };
 155
 156 enum {
 157         MLX5_EXTENDED_UD_AV             = 0x80000000,
 158 };
 159
 160 enum {
 161         MLX5_CQ_STATE_ARMED             = 9,
 162         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 163         MLX5_CQ_STATE_FIRED             = 0xa,
 164 };
 165
 166 enum {
 167         MLX5_STAT_RATE_OFFSET   = 5,
 168 };
 169
 170 enum {
 171         MLX5_INLINE_SEG = 0x80000000,
 172 };
 173
 174 enum {
 175         MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
 176 };
 177
 178 enum {
 179         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 180         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 181 };
 182
 183 enum {
 184         MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
 185 };
 186
 187 enum {
 188         MLX5_PFAULT_SUBTYPE_WQE = 0,
 189         MLX5_PFAULT_SUBTYPE_RDMA = 1,
 190 };
 191
 192 enum {
 193         MLX5_PERM_LOCAL_READ    = 1 << 2,
 194         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 195         MLX5_PERM_REMOTE_READ   = 1 << 4,
 196         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 197         MLX5_PERM_ATOMIC        = 1 << 6,
 198         MLX5_PERM_UMR_EN        = 1 << 7,
 199 };
 200
 201 enum {
 202         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 203         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 204         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 205         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 206         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 207 };
 208
 209 enum {
 210         MLX5_EN_RD      = (u64)1,
 211         MLX5_EN_WR      = (u64)2
 212 };
 213
 214 enum {
 215         MLX5_BF_REGS_PER_PAGE           = 4,
 216         MLX5_MAX_UAR_PAGES              = 1 << 8,
 217         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 218         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 219 };
 220
 221 enum {
 222         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 223         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 224         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 225         MLX5_MKEY_MASK_PD               = 1ull << 7,
 226         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 227         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 228         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 229         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 230         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 231         MLX5_MKEY_MASK_LR               = 1ull << 17,
 232         MLX5_MKEY_MASK_LW               = 1ull << 18,
 233         MLX5_MKEY_MASK_RR               = 1ull << 19,
 234         MLX5_MKEY_MASK_RW               = 1ull << 20,
 235         MLX5_MKEY_MASK_A                = 1ull << 21,
 236         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 237         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 238 };
 239
 240 enum {
 241         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 242
 243         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 244         MLX5_UMR_CHECK_FREE             = (2 << 5),
 245
 246         MLX5_UMR_INLINE                 = (1 << 7),
 247 };
 248
 249 #define MLX5_UMR_MTT_ALIGNMENT 0x40
 250 #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
 251 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
 252
 253 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
 254
 255 enum {
 256         MLX5_EVENT_QUEUE_TYPE_QP = 0,
 257         MLX5_EVENT_QUEUE_TYPE_RQ = 1,
 258         MLX5_EVENT_QUEUE_TYPE_SQ = 2,
 259 };
 260
 261 enum mlx5_event {
 262         MLX5_EVENT_TYPE_COMP               = 0x0,
 263
 264         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 265         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 266         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 267         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 268         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 269
 270         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 271         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 272         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 273         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 274         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 275         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 276
 277         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 278         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 279         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 280         MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,
 281         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 282
 283         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 284         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 285
 286         MLX5_EVENT_TYPE_CMD                = 0x0a,
 287         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 288
 289         MLX5_EVENT_TYPE_PAGE_FAULT         = 0xc,
 290         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
 291 };
 292
 293 enum {
 294         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 295         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 296         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 297         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 298         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 299         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 300         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 301 };
 302
 303 enum {
 304         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 305         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 306         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 307         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 308         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 309         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 310         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 311         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 312         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 313         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 314         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 315         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 316 };
 317
 318 enum {
 319         MLX5_ROCE_VERSION_1             = 0,
 320         MLX5_ROCE_VERSION_2             = 2,
 321 };
 322
 323 enum {
 324         MLX5_ROCE_VERSION_1_CAP         = 1 << MLX5_ROCE_VERSION_1,
 325         MLX5_ROCE_VERSION_2_CAP         = 1 << MLX5_ROCE_VERSION_2,
 326 };
 327
 328 enum {
 329         MLX5_ROCE_L3_TYPE_IPV4          = 0,
 330         MLX5_ROCE_L3_TYPE_IPV6          = 1,
 331 };
 332
 333 enum {
 334         MLX5_ROCE_L3_TYPE_IPV4_CAP      = 1 << 1,
 335         MLX5_ROCE_L3_TYPE_IPV6_CAP      = 1 << 2,
 336 };
 337
 338 enum {
 339         MLX5_OPCODE_NOP                 = 0x00,
 340         MLX5_OPCODE_SEND_INVAL          = 0x01,
 341         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 342         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 343         MLX5_OPCODE_SEND                = 0x0a,
 344         MLX5_OPCODE_SEND_IMM            = 0x0b,
 345         MLX5_OPCODE_LSO                 = 0x0e,
 346         MLX5_OPCODE_RDMA_READ           = 0x10,
 347         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 348         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 349         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 350         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 351         MLX5_OPCODE_BIND_MW             = 0x18,
 352         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 353
 354         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 355         MLX5_RECV_OPCODE_SEND           = 0x01,
 356         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 357         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 358
 359         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 360         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 361
 362         MLX5_OPCODE_SET_PSV             = 0x20,
 363         MLX5_OPCODE_GET_PSV             = 0x21,
 364         MLX5_OPCODE_CHECK_PSV           = 0x22,
 365         MLX5_OPCODE_RGET_PSV            = 0x26,
 366         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 367
 368         MLX5_OPCODE_UMR                 = 0x25,
 369
 370 };
 371
 372 enum {
 373         MLX5_SET_PORT_RESET_QKEY        = 0,
 374         MLX5_SET_PORT_GUID0             = 16,
 375         MLX5_SET_PORT_NODE_GUID         = 17,
 376         MLX5_SET_PORT_SYS_GUID          = 18,
 377         MLX5_SET_PORT_GID_TABLE         = 19,
 378         MLX5_SET_PORT_PKEY_TABLE        = 20,
 379 };
 380
 381 enum {
 382         MLX5_BW_NO_LIMIT   = 0,
 383         MLX5_100_MBPS_UNIT = 3,
 384         MLX5_GBPS_UNIT     = 4,
 385 };
 386
 387 enum {
 388         MLX5_MAX_PAGE_SHIFT             = 31
 389 };
 390
 391 enum {
 392         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 393         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 394 };
 395
 396 enum {
 397         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 398 };
 399
 400 enum {
 401         /*
 402          * Max wqe size for rdma read is 512 bytes, so this
 403          * limits our max_sge_rd as the wqe needs to fit:
 404          * - ctrl segment (16 bytes)
 405          * - rdma segment (16 bytes)
 406          * - scatter elements (16 bytes each)
 407          */
 408         MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
 409 };
 410
 411 enum mlx5_odp_transport_cap_bits {
 412         MLX5_ODP_SUPPORT_SEND    = 1 << 31,
 413         MLX5_ODP_SUPPORT_RECV    = 1 << 30,
 414         MLX5_ODP_SUPPORT_WRITE   = 1 << 29,
 415         MLX5_ODP_SUPPORT_READ    = 1 << 28,
 416 };
 417
 418 struct mlx5_odp_caps {
 419         char reserved[0x10];
 420         struct {
 421                 __be32                  rc_odp_caps;
 422                 __be32                  uc_odp_caps;
 423                 __be32                  ud_odp_caps;
 424         } per_transport_caps;
 425         char reserved2[0xe4];
 426 };
 427
 428 struct mlx5_cmd_layout {
 429         u8              type;
 430         u8              rsvd0[3];
 431         __be32          inlen;
 432         __be64          in_ptr;
 433         __be32          in[4];
 434         __be32          out[4];
 435         __be64          out_ptr;
 436         __be32          outlen;
 437         u8              token;
 438         u8              sig;
 439         u8              rsvd1;
 440         u8              status_own;
 441 };
 442
 443 struct health_buffer {
 444         __be32          assert_var[5];
 445         __be32          rsvd0[3];
 446         __be32          assert_exit_ptr;
 447         __be32          assert_callra;
 448         __be32          rsvd1[2];
 449         __be32          fw_ver;
 450         __be32          hw_id;
 451         __be32          rsvd2;
 452         u8              irisc_index;
 453         u8              synd;
 454         __be16          ext_synd;
 455 };
 456
 457 struct mlx5_init_seg {
 458         __be32                  fw_rev;
 459         __be32                  cmdif_rev_fw_sub;
 460         __be32                  rsvd0[2];
 461         __be32                  cmdq_addr_h;
 462         __be32                  cmdq_addr_l_sz;
 463         __be32                  cmd_dbell;
 464         __be32                  rsvd1[120];
 465         __be32                  initializing;
 466         struct health_buffer    health;
 467         __be32                  rsvd2[880];
 468         __be32                  internal_timer_h;
 469         __be32                  internal_timer_l;
 470         __be32                  rsvd3[2];
 471         __be32                  health_counter;
 472         __be32                  rsvd4[1019];
 473         __be64                  ieee1588_clk;
 474         __be32                  ieee1588_clk_type;
 475         __be32                  clr_intx;
 476 };
 477
 478 struct mlx5_eqe_comp {
 479         __be32  reserved[6];
 480         __be32  cqn;
 481 };
 482
 483 struct mlx5_eqe_qp_srq {
 484         __be32  reserved1[5];
 485         u8      type;
 486         u8      reserved2[3];
 487         __be32  qp_srq_n;
 488 };
 489
 490 struct mlx5_eqe_cq_err {
 491         __be32  cqn;
 492         u8      reserved1[7];
 493         u8      syndrome;
 494 };
 495
 496 struct mlx5_eqe_port_state {
 497         u8      reserved0[8];
 498         u8      port;
 499 };
 500
 501 struct mlx5_eqe_gpio {
 502         __be32  reserved0[2];
 503         __be64  gpio_event;
 504 };
 505
 506 struct mlx5_eqe_congestion {
 507         u8      type;
 508         u8      rsvd0;
 509         u8      congestion_level;
 510 };
 511
 512 struct mlx5_eqe_stall_vl {
 513         u8      rsvd0[3];
 514         u8      port_vl;
 515 };
 516
 517 struct mlx5_eqe_cmd {
 518         __be32  vector;
 519         __be32  rsvd[6];
 520 };
 521
 522 struct mlx5_eqe_page_req {
 523         u8              rsvd0[2];
 524         __be16          func_id;
 525         __be32          num_pages;
 526         __be32          rsvd1[5];
 527 };
 528
 529 struct mlx5_eqe_page_fault {
 530         __be32 bytes_committed;
 531         union {
 532                 struct {
 533                         u16     reserved1;
 534                         __be16  wqe_index;
 535                         u16     reserved2;
 536                         __be16  packet_length;
 537                         u8      reserved3[12];
 538                 } __packed wqe;
 539                 struct {
 540                         __be32  r_key;
 541                         u16     reserved1;
 542                         __be16  packet_length;
 543                         __be32  rdma_op_len;
 544                         __be64  rdma_va;
 545                 } __packed rdma;
 546         } __packed;
 547         __be32 flags_qpn;
 548 } __packed;
 549
 550 struct mlx5_eqe_vport_change {
 551         u8              rsvd0[2];
 552         __be16          vport_num;
 553         __be32          rsvd1[6];
 554 } __packed;
 555
 556 struct mlx5_eqe_port_module {
 557         u8        reserved_at_0[1];
 558         u8        module;
 559         u8        reserved_at_2[1];
 560         u8        module_status;
 561         u8        reserved_at_4[2];
 562         u8        error_type;
 563 } __packed;
 564
 565 union ev_data {
 566         __be32                          raw[7];
 567         struct mlx5_eqe_cmd             cmd;
 568         struct mlx5_eqe_comp            comp;
 569         struct mlx5_eqe_qp_srq          qp_srq;
 570         struct mlx5_eqe_cq_err          cq_err;
 571         struct mlx5_eqe_port_state      port;
 572         struct mlx5_eqe_gpio            gpio;
 573         struct mlx5_eqe_congestion      cong;
 574         struct mlx5_eqe_stall_vl        stall_vl;
 575         struct mlx5_eqe_page_req        req_pages;
 576         struct mlx5_eqe_page_fault      page_fault;
 577         struct mlx5_eqe_vport_change    vport_change;
 578         struct mlx5_eqe_port_module     port_module;
 579 } __packed;
 580
 581 struct mlx5_eqe {
 582         u8              rsvd0;
 583         u8              type;
 584         u8              rsvd1;
 585         u8              sub_type;
 586         __be32          rsvd2[7];
 587         union ev_data   data;
 588         __be16          rsvd3;
 589         u8              signature;
 590         u8              owner;
 591 } __packed;
 592
 593 struct mlx5_cmd_prot_block {
 594         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 595         u8              rsvd0[48];
 596         __be64          next;
 597         __be32          block_num;
 598         u8              rsvd1;
 599         u8              token;
 600         u8              ctrl_sig;
 601         u8              sig;
 602 };
 603
 604 enum {
 605         MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
 606 };
 607
 608 struct mlx5_err_cqe {
 609         u8      rsvd0[32];
 610         __be32  srqn;
 611         u8      rsvd1[18];
 612         u8      vendor_err_synd;
 613         u8      syndrome;
 614         __be32  s_wqe_opcode_qpn;
 615         __be16  wqe_counter;
 616         u8      signature;
 617         u8      op_own;
 618 };
 619
 620 struct mlx5_cqe64 {
 621         u8              outer_l3_tunneled;
 622         u8              rsvd0;
 623         __be16          wqe_id;
 624         u8              lro_tcppsh_abort_dupack;
 625         u8              lro_min_ttl;
 626         __be16          lro_tcp_win;
 627         __be32          lro_ack_seq_num;
 628         __be32          rss_hash_result;
 629         u8              rss_hash_type;
 630         u8              ml_path;
 631         u8              rsvd20[2];
 632         __be16          check_sum;
 633         __be16          slid;
 634         __be32          flags_rqpn;
 635         u8              hds_ip_ext;
 636         u8              l4_l3_hdr_type;
 637         __be16          vlan_info;
 638         __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
 639         __be32          imm_inval_pkey;
 640         u8              rsvd40[4];
 641         __be32          byte_cnt;
 642         __be32          timestamp_h;
 643         __be32          timestamp_l;
 644         __be32          sop_drop_qpn;
 645         __be16          wqe_counter;
 646         u8              signature;
 647         u8              op_own;
 648 };
 649
 650 struct mlx5_mini_cqe8 {
 651         union {
 652                 __be32 rx_hash_result;
 653                 struct {
 654                         __be16 checksum;
 655                         __be16 rsvd;
 656                 };
 657                 struct {
 658                         __be16 wqe_counter;
 659                         u8  s_wqe_opcode;
 660                         u8  reserved;
 661                 } s_wqe_info;
 662         };
 663         __be32 byte_cnt;
 664 };
 665
 666 enum {
 667         MLX5_NO_INLINE_DATA,
 668         MLX5_INLINE_DATA32_SEG,
 669         MLX5_INLINE_DATA64_SEG,
 670         MLX5_COMPRESSED,
 671 };
 672
 673 enum {
 674         MLX5_CQE_FORMAT_CSUM = 0x1,
 675 };
 676
 677 #define MLX5_MINI_CQE_ARRAY_SIZE 8
 678
 679 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
 680 {
 681         return (cqe->op_own >> 2) & 0x3;
 682 }
 683
 684 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 685 {
 686         return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
 687 }
 688
 689 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
 690 {
 691         return (cqe->l4_l3_hdr_type >> 4) & 0x7;
 692 }
 693
 694 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
 695 {
 696         return (cqe->l4_l3_hdr_type >> 2) & 0x3;
 697 }
 698
 699 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
 700 {
 701         return cqe->outer_l3_tunneled & 0x1;
 702 }
 703
 704 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
 705 {
 706         return !!(cqe->l4_l3_hdr_type & 0x1);
 707 }
 708
 709 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
 710 {
 711         u32 hi, lo;
 712
 713         hi = be32_to_cpu(cqe->timestamp_h);
 714         lo = be32_to_cpu(cqe->timestamp_l);
 715
 716         return (u64)lo | ((u64)hi << 32);
 717 }
 718
 719 struct mpwrq_cqe_bc {
 720         __be16  filler_consumed_strides;
 721         __be16  byte_cnt;
 722 };
 723
 724 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
 725 {
 726         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 727
 728         return be16_to_cpu(bc->byte_cnt);
 729 }
 730
 731 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
 732 {
 733         return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
 734 }
 735
 736 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
 737 {
 738         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 739
 740         return mpwrq_get_cqe_bc_consumed_strides(bc);
 741 }
 742
 743 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
 744 {
 745         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 746
 747         return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
 748 }
 749
 750 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
 751 {
 752         return be16_to_cpu(cqe->wqe_counter);
 753 }
 754
 755 enum {
 756         CQE_L4_HDR_TYPE_NONE                    = 0x0,
 757         CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
 758         CQE_L4_HDR_TYPE_UDP                     = 0x2,
 759         CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
 760         CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
 761 };
 762
 763 enum {
 764         CQE_RSS_HTYPE_IP        = 0x3 << 6,
 765         CQE_RSS_HTYPE_L4        = 0x3 << 2,
 766 };
 767
 768 enum {
 769         MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH        = 0x0,
 770         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6       = 0x1,
 771         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4       = 0x2,
 772 };
 773
 774 enum {
 775         CQE_L2_OK       = 1 << 0,
 776         CQE_L3_OK       = 1 << 1,
 777         CQE_L4_OK       = 1 << 2,
 778 };
 779
 780 struct mlx5_sig_err_cqe {
 781         u8              rsvd0[16];
 782         __be32          expected_trans_sig;
 783         __be32          actual_trans_sig;
 784         __be32          expected_reftag;
 785         __be32          actual_reftag;
 786         __be16          syndrome;
 787         u8              rsvd22[2];
 788         __be32          mkey;
 789         __be64          err_offset;
 790         u8              rsvd30[8];
 791         __be32          qpn;
 792         u8              rsvd38[2];
 793         u8              signature;
 794         u8              op_own;
 795 };
 796
 797 struct mlx5_wqe_srq_next_seg {
 798         u8                      rsvd0[2];
 799         __be16                  next_wqe_index;
 800         u8                      signature;
 801         u8                      rsvd1[11];
 802 };
 803
 804 union mlx5_ext_cqe {
 805         struct ib_grh   grh;
 806         u8              inl[64];
 807 };
 808
 809 struct mlx5_cqe128 {
 810         union mlx5_ext_cqe      inl_grh;
 811         struct mlx5_cqe64       cqe64;
 812 };
 813
 814 enum {
 815         MLX5_MKEY_STATUS_FREE = 1 << 6,
 816 };
 817
 818 enum {
 819         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 820         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 821         MLX5_MKEY_BSF_EN        = 1 << 30,
 822         MLX5_MKEY_LEN64         = 1 << 31,
 823 };
 824
 825 struct mlx5_mkey_seg {
 826         /* This is a two bit field occupying bits 31-30.
 827          * bit 31 is always 0,
 828          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 829          */
 830         u8              status;
 831         u8              pcie_control;
 832         u8              flags;
 833         u8              version;
 834         __be32          qpn_mkey7_0;
 835         u8              rsvd1[4];
 836         __be32          flags_pd;
 837         __be64          start_addr;
 838         __be64          len;
 839         __be32          bsfs_octo_size;
 840         u8              rsvd2[16];
 841         __be32          xlt_oct_size;
 842         u8              rsvd3[3];
 843         u8              log2_page_size;
 844         u8              rsvd4[4];
 845 };
 846
 847 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 848
 849 enum {
 850         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 851 };
 852
 853 enum {
 854         VPORT_STATE_DOWN                = 0x0,
 855         VPORT_STATE_UP                  = 0x1,
 856 };
 857
 858 enum {
 859         MLX5_ESW_VPORT_ADMIN_STATE_DOWN  = 0x0,
 860         MLX5_ESW_VPORT_ADMIN_STATE_UP    = 0x1,
 861         MLX5_ESW_VPORT_ADMIN_STATE_AUTO  = 0x2,
 862 };
 863
 864 enum {
 865         MLX5_L3_PROT_TYPE_IPV4          = 0,
 866         MLX5_L3_PROT_TYPE_IPV6          = 1,
 867 };
 868
 869 enum {
 870         MLX5_L4_PROT_TYPE_TCP           = 0,
 871         MLX5_L4_PROT_TYPE_UDP           = 1,
 872 };
 873
 874 enum {
 875         MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
 876         MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
 877         MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
 878         MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
 879         MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
 880 };
 881
 882 enum {
 883         MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
 884         MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
 885         MLX5_MATCH_INNER_HEADERS        = 1 << 2,
 886
 887 };
 888
 889 enum {
 890         MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
 891         MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
 892 };
 893
 894 enum {
 895         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
 896         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
 897         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
 898 };
 899
 900 enum mlx5_list_type {
 901         MLX5_NVPRT_LIST_TYPE_UC   = 0x0,
 902         MLX5_NVPRT_LIST_TYPE_MC   = 0x1,
 903         MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
 904 };
 905
 906 enum {
 907         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
 908         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
 909 };
 910
 911 enum mlx5_wol_mode {
 912         MLX5_WOL_DISABLE        = 0,
 913         MLX5_WOL_SECURED_MAGIC  = 1 << 1,
 914         MLX5_WOL_MAGIC          = 1 << 2,
 915         MLX5_WOL_ARP            = 1 << 3,
 916         MLX5_WOL_BROADCAST      = 1 << 4,
 917         MLX5_WOL_MULTICAST      = 1 << 5,
 918         MLX5_WOL_UNICAST        = 1 << 6,
 919         MLX5_WOL_PHY_ACTIVITY   = 1 << 7,
 920 };
 921
 922 /* MLX5 DEV CAPs */
 923
 924 /* TODO: EAT.ME */
 925 enum mlx5_cap_mode {
 926         HCA_CAP_OPMOD_GET_MAX   = 0,
 927         HCA_CAP_OPMOD_GET_CUR   = 1,
 928 };
 929
 930 enum mlx5_cap_type {
 931         MLX5_CAP_GENERAL = 0,
 932         MLX5_CAP_ETHERNET_OFFLOADS,
 933         MLX5_CAP_ODP,
 934         MLX5_CAP_ATOMIC,
 935         MLX5_CAP_ROCE,
 936         MLX5_CAP_IPOIB_OFFLOADS,
 937         MLX5_CAP_EOIB_OFFLOADS,
 938         MLX5_CAP_FLOW_TABLE,
 939         MLX5_CAP_ESWITCH_FLOW_TABLE,
 940         MLX5_CAP_ESWITCH,
 941         MLX5_CAP_RESERVED,
 942         MLX5_CAP_VECTOR_CALC,
 943         MLX5_CAP_QOS,
 944         /* NUM OF CAP Types */
 945         MLX5_CAP_NUM
 946 };
 947
 948 /* GET Dev Caps macros */
 949 #define MLX5_CAP_GEN(mdev, cap) \
 950         MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
 951
 952 #define MLX5_CAP_GEN_MAX(mdev, cap) \
 953         MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
 954
 955 #define MLX5_CAP_ETH(mdev, cap) \
 956         MLX5_GET(per_protocol_networking_offload_caps,\
 957                  mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
 958
 959 #define MLX5_CAP_ETH_MAX(mdev, cap) \
 960         MLX5_GET(per_protocol_networking_offload_caps,\
 961                  mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
 962
 963 #define MLX5_CAP_ROCE(mdev, cap) \
 964         MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
 965
 966 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
 967         MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
 968
 969 #define MLX5_CAP_ATOMIC(mdev, cap) \
 970         MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
 971
 972 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
 973         MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
 974
 975 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
 976         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
 977
 978 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
 979         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
 980
 981 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
 982         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
 983
 984 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
 985         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
 986
 987 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
 988         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
 989
 990 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
 991         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
 992
 993 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
 994         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
 995
 996 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
 997         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
 998
 999 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1000         MLX5_GET(flow_table_eswitch_cap, \
1001                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1002
1003 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1004         MLX5_GET(flow_table_eswitch_cap, \
1005                  mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1006
1007 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1008         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1009
1010 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1011         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1012
1013 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1014         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1015
1016 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1017         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1018
1019 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1020         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1021
1022 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1023         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1024
1025 #define MLX5_CAP_ESW(mdev, cap) \
1026         MLX5_GET(e_switch_cap, \
1027                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1028
1029 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1030         MLX5_GET(e_switch_cap, \
1031                  mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1032
1033 #define MLX5_CAP_ODP(mdev, cap)\
1034         MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1035
1036 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1037         MLX5_GET(vector_calc_cap, \
1038                  mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1039
1040 #define MLX5_CAP_QOS(mdev, cap)\
1041         MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1042
1043 enum {
1044         MLX5_CMD_STAT_OK                        = 0x0,
1045         MLX5_CMD_STAT_INT_ERR                   = 0x1,
1046         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
1047         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
1048         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
1049         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
1050         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
1051         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
1052         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
1053         MLX5_CMD_STAT_IX_ERR                    = 0xa,
1054         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
1055         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
1056         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
1057         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
1058         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
1059         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
1060 };
1061
1062 enum {
1063         MLX5_IEEE_802_3_COUNTERS_GROUP        = 0x0,
1064         MLX5_RFC_2863_COUNTERS_GROUP          = 0x1,
1065         MLX5_RFC_2819_COUNTERS_GROUP          = 0x2,
1066         MLX5_RFC_3635_COUNTERS_GROUP          = 0x3,
1067         MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1068         MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1069         MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1070         MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
1071         MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
1072 };
1073
1074 enum {
1075         MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP       = 0x0,
1076         MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1077 };
1078
1079 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1080 {
1081         if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1082                 return 0;
1083         return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1084 }
1085
1086 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1087 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1088 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1089 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1090                                 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1091                                 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1092
1093 #endif /* MLX5_DEVICE_H */