2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #error Host endianness not defined
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
68 /* insert a value to a struct */
69 #define MLX5_SET(typ, p, fld, v) do { \
71 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
72 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
73 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
74 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
75 << __mlx5_dw_bit_off(typ, fld))); \
78 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
79 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
80 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
81 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
82 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
83 << __mlx5_dw_bit_off(typ, fld))); \
86 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
87 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
88 __mlx5_mask(typ, fld))
90 #define MLX5_GET_PR(typ, p, fld) ({ \
91 u32 ___t = MLX5_GET(typ, p, fld); \
92 pr_debug(#fld " = 0x%x\n", ___t); \
96 #define __MLX5_SET64(typ, p, fld, v) do { \
97 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
101 #define MLX5_SET64(typ, p, fld, v) do { \
102 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
103 __MLX5_SET64(typ, p, fld, v); \
106 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108 __MLX5_SET64(typ, p, fld[idx], v); \
111 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
113 #define MLX5_GET64_PR(typ, p, fld) ({ \
114 u64 ___t = MLX5_GET64(typ, p, fld); \
115 pr_debug(#fld " = 0x%llx\n", ___t); \
119 /* Big endian getters */
120 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
121 __mlx5_64_off(typ, fld)))
123 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
125 switch (sizeof(tmp)) { \
127 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
130 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
133 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
136 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
142 enum mlx5_inline_modes
{
143 MLX5_INLINE_MODE_NONE
,
146 MLX5_INLINE_MODE_TCP_UDP
,
150 MLX5_MAX_COMMANDS
= 32,
151 MLX5_CMD_DATA_BLOCK_SIZE
= 512,
152 MLX5_PCI_CMD_XPORT
= 7,
153 MLX5_MKEY_BSF_OCTO_SIZE
= 4,
158 MLX5_EXTENDED_UD_AV
= 0x80000000,
162 MLX5_CQ_STATE_ARMED
= 9,
163 MLX5_CQ_STATE_ALWAYS_ARMED
= 0xb,
164 MLX5_CQ_STATE_FIRED
= 0xa,
168 MLX5_STAT_RATE_OFFSET
= 5,
172 MLX5_INLINE_SEG
= 0x80000000,
176 MLX5_HW_START_PADDING
= MLX5_INLINE_SEG
,
180 MLX5_MIN_PKEY_TABLE_SIZE
= 128,
181 MLX5_MAX_LOG_PKEY_TABLE
= 5,
185 MLX5_MKEY_INBOX_PG_ACCESS
= 1 << 31
189 MLX5_PFAULT_SUBTYPE_WQE
= 0,
190 MLX5_PFAULT_SUBTYPE_RDMA
= 1,
194 MLX5_PERM_LOCAL_READ
= 1 << 2,
195 MLX5_PERM_LOCAL_WRITE
= 1 << 3,
196 MLX5_PERM_REMOTE_READ
= 1 << 4,
197 MLX5_PERM_REMOTE_WRITE
= 1 << 5,
198 MLX5_PERM_ATOMIC
= 1 << 6,
199 MLX5_PERM_UMR_EN
= 1 << 7,
203 MLX5_PCIE_CTRL_SMALL_FENCE
= 1 << 0,
204 MLX5_PCIE_CTRL_RELAXED_ORDERING
= 1 << 2,
205 MLX5_PCIE_CTRL_NO_SNOOP
= 1 << 3,
206 MLX5_PCIE_CTRL_TLP_PROCE_EN
= 1 << 6,
207 MLX5_PCIE_CTRL_TPH_MASK
= 3 << 4,
216 MLX5_ADAPTER_PAGE_SHIFT
= 12,
217 MLX5_ADAPTER_PAGE_SIZE
= 1 << MLX5_ADAPTER_PAGE_SHIFT
,
221 MLX5_BFREGS_PER_UAR
= 4,
222 MLX5_MAX_UARS
= 1 << 8,
223 MLX5_NON_FP_BFREGS_PER_UAR
= 2,
224 MLX5_FP_BFREGS_PER_UAR
= MLX5_BFREGS_PER_UAR
-
225 MLX5_NON_FP_BFREGS_PER_UAR
,
226 MLX5_MAX_BFREGS
= MLX5_MAX_UARS
*
227 MLX5_NON_FP_BFREGS_PER_UAR
,
228 MLX5_UARS_IN_PAGE
= PAGE_SIZE
/ MLX5_ADAPTER_PAGE_SIZE
,
229 MLX5_NON_FP_BFREGS_IN_PAGE
= MLX5_NON_FP_BFREGS_PER_UAR
* MLX5_UARS_IN_PAGE
,
233 MLX5_MKEY_MASK_LEN
= 1ull << 0,
234 MLX5_MKEY_MASK_PAGE_SIZE
= 1ull << 1,
235 MLX5_MKEY_MASK_START_ADDR
= 1ull << 6,
236 MLX5_MKEY_MASK_PD
= 1ull << 7,
237 MLX5_MKEY_MASK_EN_RINVAL
= 1ull << 8,
238 MLX5_MKEY_MASK_EN_SIGERR
= 1ull << 9,
239 MLX5_MKEY_MASK_BSF_EN
= 1ull << 12,
240 MLX5_MKEY_MASK_KEY
= 1ull << 13,
241 MLX5_MKEY_MASK_QPN
= 1ull << 14,
242 MLX5_MKEY_MASK_LR
= 1ull << 17,
243 MLX5_MKEY_MASK_LW
= 1ull << 18,
244 MLX5_MKEY_MASK_RR
= 1ull << 19,
245 MLX5_MKEY_MASK_RW
= 1ull << 20,
246 MLX5_MKEY_MASK_A
= 1ull << 21,
247 MLX5_MKEY_MASK_SMALL_FENCE
= 1ull << 23,
248 MLX5_MKEY_MASK_FREE
= 1ull << 29,
252 MLX5_UMR_TRANSLATION_OFFSET_EN
= (1 << 4),
254 MLX5_UMR_CHECK_NOT_FREE
= (1 << 5),
255 MLX5_UMR_CHECK_FREE
= (2 << 5),
257 MLX5_UMR_INLINE
= (1 << 7),
260 #define MLX5_UMR_MTT_ALIGNMENT 0x40
261 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
262 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
264 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
267 MLX5_EVENT_QUEUE_TYPE_QP
= 0,
268 MLX5_EVENT_QUEUE_TYPE_RQ
= 1,
269 MLX5_EVENT_QUEUE_TYPE_SQ
= 2,
273 MLX5_EVENT_TYPE_COMP
= 0x0,
275 MLX5_EVENT_TYPE_PATH_MIG
= 0x01,
276 MLX5_EVENT_TYPE_COMM_EST
= 0x02,
277 MLX5_EVENT_TYPE_SQ_DRAINED
= 0x03,
278 MLX5_EVENT_TYPE_SRQ_LAST_WQE
= 0x13,
279 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT
= 0x14,
281 MLX5_EVENT_TYPE_CQ_ERROR
= 0x04,
282 MLX5_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
283 MLX5_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
284 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
285 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
286 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
288 MLX5_EVENT_TYPE_INTERNAL_ERROR
= 0x08,
289 MLX5_EVENT_TYPE_PORT_CHANGE
= 0x09,
290 MLX5_EVENT_TYPE_GPIO_EVENT
= 0x15,
291 MLX5_EVENT_TYPE_PORT_MODULE_EVENT
= 0x16,
292 MLX5_EVENT_TYPE_REMOTE_CONFIG
= 0x19,
293 MLX5_EVENT_TYPE_PPS_EVENT
= 0x25,
295 MLX5_EVENT_TYPE_DB_BF_CONGESTION
= 0x1a,
296 MLX5_EVENT_TYPE_STALL_EVENT
= 0x1b,
298 MLX5_EVENT_TYPE_CMD
= 0x0a,
299 MLX5_EVENT_TYPE_PAGE_REQUEST
= 0xb,
301 MLX5_EVENT_TYPE_PAGE_FAULT
= 0xc,
302 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE
= 0xd,
306 MLX5_PORT_CHANGE_SUBTYPE_DOWN
= 1,
307 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE
= 4,
308 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED
= 5,
309 MLX5_PORT_CHANGE_SUBTYPE_LID
= 6,
310 MLX5_PORT_CHANGE_SUBTYPE_PKEY
= 7,
311 MLX5_PORT_CHANGE_SUBTYPE_GUID
= 8,
312 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG
= 9,
316 MLX5_DEV_CAP_FLAG_XRC
= 1LL << 3,
317 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
318 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
319 MLX5_DEV_CAP_FLAG_APM
= 1LL << 17,
320 MLX5_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
321 MLX5_DEV_CAP_FLAG_BLOCK_MCAST
= 1LL << 23,
322 MLX5_DEV_CAP_FLAG_ON_DMND_PG
= 1LL << 24,
323 MLX5_DEV_CAP_FLAG_CQ_MODER
= 1LL << 29,
324 MLX5_DEV_CAP_FLAG_RESIZE_CQ
= 1LL << 30,
325 MLX5_DEV_CAP_FLAG_DCT
= 1LL << 37,
326 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER
= 1LL << 40,
327 MLX5_DEV_CAP_FLAG_CMDIF_CSUM
= 3LL << 46,
331 MLX5_ROCE_VERSION_1
= 0,
332 MLX5_ROCE_VERSION_2
= 2,
336 MLX5_ROCE_VERSION_1_CAP
= 1 << MLX5_ROCE_VERSION_1
,
337 MLX5_ROCE_VERSION_2_CAP
= 1 << MLX5_ROCE_VERSION_2
,
341 MLX5_ROCE_L3_TYPE_IPV4
= 0,
342 MLX5_ROCE_L3_TYPE_IPV6
= 1,
346 MLX5_ROCE_L3_TYPE_IPV4_CAP
= 1 << 1,
347 MLX5_ROCE_L3_TYPE_IPV6_CAP
= 1 << 2,
351 MLX5_OPCODE_NOP
= 0x00,
352 MLX5_OPCODE_SEND_INVAL
= 0x01,
353 MLX5_OPCODE_RDMA_WRITE
= 0x08,
354 MLX5_OPCODE_RDMA_WRITE_IMM
= 0x09,
355 MLX5_OPCODE_SEND
= 0x0a,
356 MLX5_OPCODE_SEND_IMM
= 0x0b,
357 MLX5_OPCODE_LSO
= 0x0e,
358 MLX5_OPCODE_RDMA_READ
= 0x10,
359 MLX5_OPCODE_ATOMIC_CS
= 0x11,
360 MLX5_OPCODE_ATOMIC_FA
= 0x12,
361 MLX5_OPCODE_ATOMIC_MASKED_CS
= 0x14,
362 MLX5_OPCODE_ATOMIC_MASKED_FA
= 0x15,
363 MLX5_OPCODE_BIND_MW
= 0x18,
364 MLX5_OPCODE_CONFIG_CMD
= 0x1f,
366 MLX5_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
367 MLX5_RECV_OPCODE_SEND
= 0x01,
368 MLX5_RECV_OPCODE_SEND_IMM
= 0x02,
369 MLX5_RECV_OPCODE_SEND_INVAL
= 0x03,
371 MLX5_CQE_OPCODE_ERROR
= 0x1e,
372 MLX5_CQE_OPCODE_RESIZE
= 0x16,
374 MLX5_OPCODE_SET_PSV
= 0x20,
375 MLX5_OPCODE_GET_PSV
= 0x21,
376 MLX5_OPCODE_CHECK_PSV
= 0x22,
377 MLX5_OPCODE_RGET_PSV
= 0x26,
378 MLX5_OPCODE_RCHECK_PSV
= 0x27,
380 MLX5_OPCODE_UMR
= 0x25,
385 MLX5_SET_PORT_RESET_QKEY
= 0,
386 MLX5_SET_PORT_GUID0
= 16,
387 MLX5_SET_PORT_NODE_GUID
= 17,
388 MLX5_SET_PORT_SYS_GUID
= 18,
389 MLX5_SET_PORT_GID_TABLE
= 19,
390 MLX5_SET_PORT_PKEY_TABLE
= 20,
394 MLX5_BW_NO_LIMIT
= 0,
395 MLX5_100_MBPS_UNIT
= 3,
400 MLX5_MAX_PAGE_SHIFT
= 31
404 MLX5_CAP_OFF_CMDIF_CSUM
= 46,
409 * Max wqe size for rdma read is 512 bytes, so this
410 * limits our max_sge_rd as the wqe needs to fit:
411 * - ctrl segment (16 bytes)
412 * - rdma segment (16 bytes)
413 * - scatter elements (16 bytes each)
415 MLX5_MAX_SGE_RD
= (512 - 16 - 16) / 16
418 enum mlx5_odp_transport_cap_bits
{
419 MLX5_ODP_SUPPORT_SEND
= 1 << 31,
420 MLX5_ODP_SUPPORT_RECV
= 1 << 30,
421 MLX5_ODP_SUPPORT_WRITE
= 1 << 29,
422 MLX5_ODP_SUPPORT_READ
= 1 << 28,
425 struct mlx5_odp_caps
{
431 } per_transport_caps
;
432 char reserved2
[0xe4];
435 struct mlx5_cmd_layout
{
450 struct health_buffer
{
451 __be32 assert_var
[5];
453 __be32 assert_exit_ptr
;
454 __be32 assert_callra
;
464 struct mlx5_init_seg
{
466 __be32 cmdif_rev_fw_sub
;
469 __be32 cmdq_addr_l_sz
;
473 struct health_buffer health
;
475 __be32 internal_timer_h
;
476 __be32 internal_timer_l
;
478 __be32 health_counter
;
481 __be32 ieee1588_clk_type
;
485 struct mlx5_eqe_comp
{
490 struct mlx5_eqe_qp_srq
{
497 struct mlx5_eqe_cq_err
{
503 struct mlx5_eqe_port_state
{
508 struct mlx5_eqe_gpio
{
513 struct mlx5_eqe_congestion
{
519 struct mlx5_eqe_stall_vl
{
524 struct mlx5_eqe_cmd
{
529 struct mlx5_eqe_page_req
{
536 struct mlx5_eqe_page_fault
{
537 __be32 bytes_committed
;
543 __be16 packet_length
;
551 __be16 packet_length
;
559 struct mlx5_eqe_vport_change
{
565 struct mlx5_eqe_port_module
{
574 struct mlx5_eqe_pps
{
592 struct mlx5_eqe_cmd cmd
;
593 struct mlx5_eqe_comp comp
;
594 struct mlx5_eqe_qp_srq qp_srq
;
595 struct mlx5_eqe_cq_err cq_err
;
596 struct mlx5_eqe_port_state port
;
597 struct mlx5_eqe_gpio gpio
;
598 struct mlx5_eqe_congestion cong
;
599 struct mlx5_eqe_stall_vl stall_vl
;
600 struct mlx5_eqe_page_req req_pages
;
601 struct mlx5_eqe_page_fault page_fault
;
602 struct mlx5_eqe_vport_change vport_change
;
603 struct mlx5_eqe_port_module port_module
;
604 struct mlx5_eqe_pps pps
;
619 struct mlx5_cmd_prot_block
{
620 u8 data
[MLX5_CMD_DATA_BLOCK_SIZE
];
631 MLX5_CQE_SYND_FLUSHED_IN_ERROR
= 5,
634 struct mlx5_err_cqe
{
640 __be32 s_wqe_opcode_qpn
;
647 u8 outer_l3_tunneled
;
650 u8 lro_tcppsh_abort_dupack
;
653 __be32 lro_ack_seq_num
;
654 __be32 rss_hash_result
;
664 __be32 srqn
; /* [31:24]: lro_num_seg, [23:0]: srqn */
665 __be32 imm_inval_pkey
;
676 struct mlx5_mini_cqe8
{
678 __be32 rx_hash_result
;
694 MLX5_INLINE_DATA32_SEG
,
695 MLX5_INLINE_DATA64_SEG
,
700 MLX5_CQE_FORMAT_CSUM
= 0x1,
703 #define MLX5_MINI_CQE_ARRAY_SIZE 8
705 static inline int mlx5_get_cqe_format(struct mlx5_cqe64
*cqe
)
707 return (cqe
->op_own
>> 2) & 0x3;
710 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64
*cqe
)
712 return (cqe
->lro_tcppsh_abort_dupack
>> 6) & 1;
715 static inline u8
get_cqe_l4_hdr_type(struct mlx5_cqe64
*cqe
)
717 return (cqe
->l4_l3_hdr_type
>> 4) & 0x7;
720 static inline u8
get_cqe_l3_hdr_type(struct mlx5_cqe64
*cqe
)
722 return (cqe
->l4_l3_hdr_type
>> 2) & 0x3;
725 static inline u8
cqe_is_tunneled(struct mlx5_cqe64
*cqe
)
727 return cqe
->outer_l3_tunneled
& 0x1;
730 static inline int cqe_has_vlan(struct mlx5_cqe64
*cqe
)
732 return !!(cqe
->l4_l3_hdr_type
& 0x1);
735 static inline u64
get_cqe_ts(struct mlx5_cqe64
*cqe
)
739 hi
= be32_to_cpu(cqe
->timestamp_h
);
740 lo
= be32_to_cpu(cqe
->timestamp_l
);
742 return (u64
)lo
| ((u64
)hi
<< 32);
745 struct mpwrq_cqe_bc
{
746 __be16 filler_consumed_strides
;
750 static inline u16
mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64
*cqe
)
752 struct mpwrq_cqe_bc
*bc
= (struct mpwrq_cqe_bc
*)&cqe
->byte_cnt
;
754 return be16_to_cpu(bc
->byte_cnt
);
757 static inline u16
mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc
*bc
)
759 return 0x7fff & be16_to_cpu(bc
->filler_consumed_strides
);
762 static inline u16
mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64
*cqe
)
764 struct mpwrq_cqe_bc
*bc
= (struct mpwrq_cqe_bc
*)&cqe
->byte_cnt
;
766 return mpwrq_get_cqe_bc_consumed_strides(bc
);
769 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64
*cqe
)
771 struct mpwrq_cqe_bc
*bc
= (struct mpwrq_cqe_bc
*)&cqe
->byte_cnt
;
773 return 0x8000 & be16_to_cpu(bc
->filler_consumed_strides
);
776 static inline u16
mpwrq_get_cqe_stride_index(struct mlx5_cqe64
*cqe
)
778 return be16_to_cpu(cqe
->wqe_counter
);
782 CQE_L4_HDR_TYPE_NONE
= 0x0,
783 CQE_L4_HDR_TYPE_TCP_NO_ACK
= 0x1,
784 CQE_L4_HDR_TYPE_UDP
= 0x2,
785 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA
= 0x3,
786 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA
= 0x4,
790 CQE_RSS_HTYPE_IP
= 0x3 << 2,
791 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
792 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
794 CQE_RSS_HTYPE_L4
= 0x3 << 6,
795 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
796 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
801 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH
= 0x0,
802 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6
= 0x1,
803 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4
= 0x2,
812 struct mlx5_sig_err_cqe
{
814 __be32 expected_trans_sig
;
815 __be32 actual_trans_sig
;
816 __be32 expected_reftag
;
817 __be32 actual_reftag
;
829 struct mlx5_wqe_srq_next_seg
{
831 __be16 next_wqe_index
;
842 union mlx5_ext_cqe inl_grh
;
843 struct mlx5_cqe64 cqe64
;
847 MLX5_MKEY_STATUS_FREE
= 1 << 6,
851 MLX5_MKEY_REMOTE_INVAL
= 1 << 24,
852 MLX5_MKEY_FLAG_SYNC_UMR
= 1 << 29,
853 MLX5_MKEY_BSF_EN
= 1 << 30,
854 MLX5_MKEY_LEN64
= 1 << 31,
857 struct mlx5_mkey_seg
{
858 /* This is a two bit field occupying bits 31-30.
859 * bit 31 is always 0,
860 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
871 __be32 bsfs_octo_size
;
879 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
882 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO
= 1 << 0
886 VPORT_STATE_DOWN
= 0x0,
887 VPORT_STATE_UP
= 0x1,
891 MLX5_ESW_VPORT_ADMIN_STATE_DOWN
= 0x0,
892 MLX5_ESW_VPORT_ADMIN_STATE_UP
= 0x1,
893 MLX5_ESW_VPORT_ADMIN_STATE_AUTO
= 0x2,
897 MLX5_L3_PROT_TYPE_IPV4
= 0,
898 MLX5_L3_PROT_TYPE_IPV6
= 1,
902 MLX5_L4_PROT_TYPE_TCP
= 0,
903 MLX5_L4_PROT_TYPE_UDP
= 1,
907 MLX5_HASH_FIELD_SEL_SRC_IP
= 1 << 0,
908 MLX5_HASH_FIELD_SEL_DST_IP
= 1 << 1,
909 MLX5_HASH_FIELD_SEL_L4_SPORT
= 1 << 2,
910 MLX5_HASH_FIELD_SEL_L4_DPORT
= 1 << 3,
911 MLX5_HASH_FIELD_SEL_IPSEC_SPI
= 1 << 4,
915 MLX5_MATCH_OUTER_HEADERS
= 1 << 0,
916 MLX5_MATCH_MISC_PARAMETERS
= 1 << 1,
917 MLX5_MATCH_INNER_HEADERS
= 1 << 2,
922 MLX5_FLOW_TABLE_TYPE_NIC_RCV
= 0,
923 MLX5_FLOW_TABLE_TYPE_ESWITCH
= 4,
927 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT
= 0,
928 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE
= 1,
929 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR
= 2,
932 enum mlx5_list_type
{
933 MLX5_NVPRT_LIST_TYPE_UC
= 0x0,
934 MLX5_NVPRT_LIST_TYPE_MC
= 0x1,
935 MLX5_NVPRT_LIST_TYPE_VLAN
= 0x2,
939 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
940 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM
= 0x1,
944 MLX5_WOL_DISABLE
= 0,
945 MLX5_WOL_SECURED_MAGIC
= 1 << 1,
946 MLX5_WOL_MAGIC
= 1 << 2,
947 MLX5_WOL_ARP
= 1 << 3,
948 MLX5_WOL_BROADCAST
= 1 << 4,
949 MLX5_WOL_MULTICAST
= 1 << 5,
950 MLX5_WOL_UNICAST
= 1 << 6,
951 MLX5_WOL_PHY_ACTIVITY
= 1 << 7,
958 HCA_CAP_OPMOD_GET_MAX
= 0,
959 HCA_CAP_OPMOD_GET_CUR
= 1,
963 MLX5_CAP_GENERAL
= 0,
964 MLX5_CAP_ETHERNET_OFFLOADS
,
968 MLX5_CAP_IPOIB_OFFLOADS
,
969 MLX5_CAP_EOIB_OFFLOADS
,
971 MLX5_CAP_ESWITCH_FLOW_TABLE
,
974 MLX5_CAP_VECTOR_CALC
,
976 /* NUM OF CAP Types */
980 enum mlx5_pcam_reg_groups
{
981 MLX5_PCAM_REGS_5000_TO_507F
= 0x0,
984 enum mlx5_pcam_feature_groups
{
985 MLX5_PCAM_FEATURE_ENHANCED_FEATURES
= 0x0,
988 enum mlx5_mcam_reg_groups
{
989 MLX5_MCAM_REGS_FIRST_128
= 0x0,
992 enum mlx5_mcam_feature_groups
{
993 MLX5_MCAM_FEATURE_ENHANCED_FEATURES
= 0x0,
996 /* GET Dev Caps macros */
997 #define MLX5_CAP_GEN(mdev, cap) \
998 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1000 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1001 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1003 #define MLX5_CAP_ETH(mdev, cap) \
1004 MLX5_GET(per_protocol_networking_offload_caps,\
1005 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1007 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1008 MLX5_GET(per_protocol_networking_offload_caps,\
1009 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1011 #define MLX5_CAP_ROCE(mdev, cap) \
1012 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1014 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1015 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1017 #define MLX5_CAP_ATOMIC(mdev, cap) \
1018 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1020 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1021 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1023 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1024 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1026 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1027 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1029 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1030 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1032 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1033 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1035 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1036 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1038 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1039 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1041 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1042 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1044 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1045 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1047 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1048 MLX5_GET(flow_table_eswitch_cap, \
1049 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1051 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1052 MLX5_GET(flow_table_eswitch_cap, \
1053 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1055 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1056 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1058 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1059 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1061 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1062 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1064 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1065 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1067 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1068 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1070 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1071 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1073 #define MLX5_CAP_ESW(mdev, cap) \
1074 MLX5_GET(e_switch_cap, \
1075 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1077 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1078 MLX5_GET(e_switch_cap, \
1079 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1081 #define MLX5_CAP_ODP(mdev, cap)\
1082 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1084 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1085 MLX5_GET(vector_calc_cap, \
1086 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1088 #define MLX5_CAP_QOS(mdev, cap)\
1089 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1091 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1092 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1094 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1095 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1098 MLX5_CMD_STAT_OK
= 0x0,
1099 MLX5_CMD_STAT_INT_ERR
= 0x1,
1100 MLX5_CMD_STAT_BAD_OP_ERR
= 0x2,
1101 MLX5_CMD_STAT_BAD_PARAM_ERR
= 0x3,
1102 MLX5_CMD_STAT_BAD_SYS_STATE_ERR
= 0x4,
1103 MLX5_CMD_STAT_BAD_RES_ERR
= 0x5,
1104 MLX5_CMD_STAT_RES_BUSY
= 0x6,
1105 MLX5_CMD_STAT_LIM_ERR
= 0x8,
1106 MLX5_CMD_STAT_BAD_RES_STATE_ERR
= 0x9,
1107 MLX5_CMD_STAT_IX_ERR
= 0xa,
1108 MLX5_CMD_STAT_NO_RES_ERR
= 0xf,
1109 MLX5_CMD_STAT_BAD_INP_LEN_ERR
= 0x50,
1110 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR
= 0x51,
1111 MLX5_CMD_STAT_BAD_QP_STATE_ERR
= 0x10,
1112 MLX5_CMD_STAT_BAD_PKT_ERR
= 0x30,
1113 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR
= 0x40,
1117 MLX5_IEEE_802_3_COUNTERS_GROUP
= 0x0,
1118 MLX5_RFC_2863_COUNTERS_GROUP
= 0x1,
1119 MLX5_RFC_2819_COUNTERS_GROUP
= 0x2,
1120 MLX5_RFC_3635_COUNTERS_GROUP
= 0x3,
1121 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP
= 0x5,
1122 MLX5_PER_PRIORITY_COUNTERS_GROUP
= 0x10,
1123 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP
= 0x11,
1124 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
= 0x12,
1125 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP
= 0x16,
1126 MLX5_INFINIBAND_PORT_COUNTERS_GROUP
= 0x20,
1130 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP
= 0x0,
1133 static inline u16
mlx5_to_sw_pkey_sz(int pkey_sz
)
1135 if (pkey_sz
> MLX5_MAX_LOG_PKEY_TABLE
)
1137 return MLX5_MIN_PKEY_TABLE_SIZE
<< pkey_sz
;
1140 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1141 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1142 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1143 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1144 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1145 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1147 #endif /* MLX5_DEVICE_H */