include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38 #include <linux/mlx5/mlx5_ifc.h>
  39
  40 #if defined(__LITTLE_ENDIAN)
  41 #define MLX5_SET_HOST_ENDIANNESS        0
  42 #elif defined(__BIG_ENDIAN)
  43 #define MLX5_SET_HOST_ENDIANNESS        0x80
  44 #else
  45 #error Host endianness not defined
  46 #endif
  47
  48 /* helper macros */
  49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  58
  59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
  63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
  64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
  65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  67
  68 /* insert a value to a struct */
  69 #define MLX5_SET(typ, p, fld, v) do { \
  70         u32 _v = v; \
  71         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  72         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  73         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  74                      (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
  75                      << __mlx5_dw_bit_off(typ, fld))); \
  76 } while (0)
  77
  78 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
  79         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  80         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  81         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  82                      (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
  83                      << __mlx5_dw_bit_off(typ, fld))); \
  84 } while (0)
  85
  86 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  87 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  88 __mlx5_mask(typ, fld))
  89
  90 #define MLX5_GET_PR(typ, p, fld) ({ \
  91         u32 ___t = MLX5_GET(typ, p, fld); \
  92         pr_debug(#fld " = 0x%x\n", ___t); \
  93         ___t; \
  94 })
  95
  96 #define __MLX5_SET64(typ, p, fld, v) do { \
  97         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  98         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  99 } while (0)
 100
 101 #define MLX5_SET64(typ, p, fld, v) do { \
 102         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 103         __MLX5_SET64(typ, p, fld, v); \
 104 } while (0)
 105
 106 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
 107         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 108         __MLX5_SET64(typ, p, fld[idx], v); \
 109 } while (0)
 110
 111 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 112
 113 #define MLX5_GET64_PR(typ, p, fld) ({ \
 114         u64 ___t = MLX5_GET64(typ, p, fld); \
 115         pr_debug(#fld " = 0x%llx\n", ___t); \
 116         ___t; \
 117 })
 118
 119 /* Big endian getters */
 120 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
 121         __mlx5_64_off(typ, fld)))
 122
 123 #define MLX5_GET_BE(type_t, typ, p, fld) ({                               \
 124                 type_t tmp;                                               \
 125                 switch (sizeof(tmp)) {                                    \
 126                 case sizeof(u8):                                          \
 127                         tmp = (__force type_t)MLX5_GET(typ, p, fld);      \
 128                         break;                                            \
 129                 case sizeof(u16):                                         \
 130                         tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
 131                         break;                                            \
 132                 case sizeof(u32):                                         \
 133                         tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
 134                         break;                                            \
 135                 case sizeof(u64):                                         \
 136                         tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
 137                         break;                                            \
 138                         }                                                 \
 139                 tmp;                                                      \
 140                 })
 141
 142 enum mlx5_inline_modes {
 143         MLX5_INLINE_MODE_NONE,
 144         MLX5_INLINE_MODE_L2,
 145         MLX5_INLINE_MODE_IP,
 146         MLX5_INLINE_MODE_TCP_UDP,
 147 };
 148
 149 enum {
 150         MLX5_MAX_COMMANDS               = 32,
 151         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
 152         MLX5_PCI_CMD_XPORT              = 7,
 153         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
 154         MLX5_MAX_PSVS                   = 4,
 155 };
 156
 157 enum {
 158         MLX5_EXTENDED_UD_AV             = 0x80000000,
 159 };
 160
 161 enum {
 162         MLX5_CQ_STATE_ARMED             = 9,
 163         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 164         MLX5_CQ_STATE_FIRED             = 0xa,
 165 };
 166
 167 enum {
 168         MLX5_STAT_RATE_OFFSET   = 5,
 169 };
 170
 171 enum {
 172         MLX5_INLINE_SEG = 0x80000000,
 173 };
 174
 175 enum {
 176         MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
 177 };
 178
 179 enum {
 180         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 181         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 182 };
 183
 184 enum {
 185         MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
 186 };
 187
 188 enum {
 189         MLX5_PFAULT_SUBTYPE_WQE = 0,
 190         MLX5_PFAULT_SUBTYPE_RDMA = 1,
 191 };
 192
 193 enum {
 194         MLX5_PERM_LOCAL_READ    = 1 << 2,
 195         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 196         MLX5_PERM_REMOTE_READ   = 1 << 4,
 197         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 198         MLX5_PERM_ATOMIC        = 1 << 6,
 199         MLX5_PERM_UMR_EN        = 1 << 7,
 200 };
 201
 202 enum {
 203         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 204         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 205         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 206         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 207         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 208 };
 209
 210 enum {
 211         MLX5_EN_RD      = (u64)1,
 212         MLX5_EN_WR      = (u64)2
 213 };
 214
 215 enum {
 216         MLX5_BF_REGS_PER_PAGE           = 4,
 217         MLX5_MAX_UAR_PAGES              = 1 << 8,
 218         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 219         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 220 };
 221
 222 enum {
 223         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 224         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 225         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 226         MLX5_MKEY_MASK_PD               = 1ull << 7,
 227         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 228         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 229         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 230         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 231         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 232         MLX5_MKEY_MASK_LR               = 1ull << 17,
 233         MLX5_MKEY_MASK_LW               = 1ull << 18,
 234         MLX5_MKEY_MASK_RR               = 1ull << 19,
 235         MLX5_MKEY_MASK_RW               = 1ull << 20,
 236         MLX5_MKEY_MASK_A                = 1ull << 21,
 237         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 238         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 239 };
 240
 241 enum {
 242         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 243
 244         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 245         MLX5_UMR_CHECK_FREE             = (2 << 5),
 246
 247         MLX5_UMR_INLINE                 = (1 << 7),
 248 };
 249
 250 #define MLX5_UMR_MTT_ALIGNMENT 0x40
 251 #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
 252 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
 253
 254 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
 255
 256 enum {
 257         MLX5_EVENT_QUEUE_TYPE_QP = 0,
 258         MLX5_EVENT_QUEUE_TYPE_RQ = 1,
 259         MLX5_EVENT_QUEUE_TYPE_SQ = 2,
 260 };
 261
 262 enum mlx5_event {
 263         MLX5_EVENT_TYPE_COMP               = 0x0,
 264
 265         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 266         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 267         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 268         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 269         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 270
 271         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 272         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 273         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 274         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 275         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 276         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 277
 278         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 279         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 280         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 281         MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,
 282         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 283
 284         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 285         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 286
 287         MLX5_EVENT_TYPE_CMD                = 0x0a,
 288         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 289
 290         MLX5_EVENT_TYPE_PAGE_FAULT         = 0xc,
 291         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
 292 };
 293
 294 enum {
 295         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 296         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 297         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 298         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 299         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 300         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 301         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 302 };
 303
 304 enum {
 305         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 306         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 307         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 308         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 309         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 310         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 311         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 312         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 313         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 314         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 315         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 316         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 317 };
 318
 319 enum {
 320         MLX5_ROCE_VERSION_1             = 0,
 321         MLX5_ROCE_VERSION_2             = 2,
 322 };
 323
 324 enum {
 325         MLX5_ROCE_VERSION_1_CAP         = 1 << MLX5_ROCE_VERSION_1,
 326         MLX5_ROCE_VERSION_2_CAP         = 1 << MLX5_ROCE_VERSION_2,
 327 };
 328
 329 enum {
 330         MLX5_ROCE_L3_TYPE_IPV4          = 0,
 331         MLX5_ROCE_L3_TYPE_IPV6          = 1,
 332 };
 333
 334 enum {
 335         MLX5_ROCE_L3_TYPE_IPV4_CAP      = 1 << 1,
 336         MLX5_ROCE_L3_TYPE_IPV6_CAP      = 1 << 2,
 337 };
 338
 339 enum {
 340         MLX5_OPCODE_NOP                 = 0x00,
 341         MLX5_OPCODE_SEND_INVAL          = 0x01,
 342         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 343         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 344         MLX5_OPCODE_SEND                = 0x0a,
 345         MLX5_OPCODE_SEND_IMM            = 0x0b,
 346         MLX5_OPCODE_LSO                 = 0x0e,
 347         MLX5_OPCODE_RDMA_READ           = 0x10,
 348         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 349         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 350         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 351         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 352         MLX5_OPCODE_BIND_MW             = 0x18,
 353         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 354
 355         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 356         MLX5_RECV_OPCODE_SEND           = 0x01,
 357         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 358         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 359
 360         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 361         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 362
 363         MLX5_OPCODE_SET_PSV             = 0x20,
 364         MLX5_OPCODE_GET_PSV             = 0x21,
 365         MLX5_OPCODE_CHECK_PSV           = 0x22,
 366         MLX5_OPCODE_RGET_PSV            = 0x26,
 367         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 368
 369         MLX5_OPCODE_UMR                 = 0x25,
 370
 371 };
 372
 373 enum {
 374         MLX5_SET_PORT_RESET_QKEY        = 0,
 375         MLX5_SET_PORT_GUID0             = 16,
 376         MLX5_SET_PORT_NODE_GUID         = 17,
 377         MLX5_SET_PORT_SYS_GUID          = 18,
 378         MLX5_SET_PORT_GID_TABLE         = 19,
 379         MLX5_SET_PORT_PKEY_TABLE        = 20,
 380 };
 381
 382 enum {
 383         MLX5_BW_NO_LIMIT   = 0,
 384         MLX5_100_MBPS_UNIT = 3,
 385         MLX5_GBPS_UNIT     = 4,
 386 };
 387
 388 enum {
 389         MLX5_MAX_PAGE_SHIFT             = 31
 390 };
 391
 392 enum {
 393         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 394         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 395 };
 396
 397 enum {
 398         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 399 };
 400
 401 enum {
 402         /*
 403          * Max wqe size for rdma read is 512 bytes, so this
 404          * limits our max_sge_rd as the wqe needs to fit:
 405          * - ctrl segment (16 bytes)
 406          * - rdma segment (16 bytes)
 407          * - scatter elements (16 bytes each)
 408          */
 409         MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
 410 };
 411
 412 enum mlx5_odp_transport_cap_bits {
 413         MLX5_ODP_SUPPORT_SEND    = 1 << 31,
 414         MLX5_ODP_SUPPORT_RECV    = 1 << 30,
 415         MLX5_ODP_SUPPORT_WRITE   = 1 << 29,
 416         MLX5_ODP_SUPPORT_READ    = 1 << 28,
 417 };
 418
 419 struct mlx5_odp_caps {
 420         char reserved[0x10];
 421         struct {
 422                 __be32                  rc_odp_caps;
 423                 __be32                  uc_odp_caps;
 424                 __be32                  ud_odp_caps;
 425         } per_transport_caps;
 426         char reserved2[0xe4];
 427 };
 428
 429 struct mlx5_cmd_layout {
 430         u8              type;
 431         u8              rsvd0[3];
 432         __be32          inlen;
 433         __be64          in_ptr;
 434         __be32          in[4];
 435         __be32          out[4];
 436         __be64          out_ptr;
 437         __be32          outlen;
 438         u8              token;
 439         u8              sig;
 440         u8              rsvd1;
 441         u8              status_own;
 442 };
 443
 444 struct health_buffer {
 445         __be32          assert_var[5];
 446         __be32          rsvd0[3];
 447         __be32          assert_exit_ptr;
 448         __be32          assert_callra;
 449         __be32          rsvd1[2];
 450         __be32          fw_ver;
 451         __be32          hw_id;
 452         __be32          rsvd2;
 453         u8              irisc_index;
 454         u8              synd;
 455         __be16          ext_synd;
 456 };
 457
 458 struct mlx5_init_seg {
 459         __be32                  fw_rev;
 460         __be32                  cmdif_rev_fw_sub;
 461         __be32                  rsvd0[2];
 462         __be32                  cmdq_addr_h;
 463         __be32                  cmdq_addr_l_sz;
 464         __be32                  cmd_dbell;
 465         __be32                  rsvd1[120];
 466         __be32                  initializing;
 467         struct health_buffer    health;
 468         __be32                  rsvd2[880];
 469         __be32                  internal_timer_h;
 470         __be32                  internal_timer_l;
 471         __be32                  rsvd3[2];
 472         __be32                  health_counter;
 473         __be32                  rsvd4[1019];
 474         __be64                  ieee1588_clk;
 475         __be32                  ieee1588_clk_type;
 476         __be32                  clr_intx;
 477 };
 478
 479 struct mlx5_eqe_comp {
 480         __be32  reserved[6];
 481         __be32  cqn;
 482 };
 483
 484 struct mlx5_eqe_qp_srq {
 485         __be32  reserved1[5];
 486         u8      type;
 487         u8      reserved2[3];
 488         __be32  qp_srq_n;
 489 };
 490
 491 struct mlx5_eqe_cq_err {
 492         __be32  cqn;
 493         u8      reserved1[7];
 494         u8      syndrome;
 495 };
 496
 497 struct mlx5_eqe_port_state {
 498         u8      reserved0[8];
 499         u8      port;
 500 };
 501
 502 struct mlx5_eqe_gpio {
 503         __be32  reserved0[2];
 504         __be64  gpio_event;
 505 };
 506
 507 struct mlx5_eqe_congestion {
 508         u8      type;
 509         u8      rsvd0;
 510         u8      congestion_level;
 511 };
 512
 513 struct mlx5_eqe_stall_vl {
 514         u8      rsvd0[3];
 515         u8      port_vl;
 516 };
 517
 518 struct mlx5_eqe_cmd {
 519         __be32  vector;
 520         __be32  rsvd[6];
 521 };
 522
 523 struct mlx5_eqe_page_req {
 524         u8              rsvd0[2];
 525         __be16          func_id;
 526         __be32          num_pages;
 527         __be32          rsvd1[5];
 528 };
 529
 530 struct mlx5_eqe_page_fault {
 531         __be32 bytes_committed;
 532         union {
 533                 struct {
 534                         u16     reserved1;
 535                         __be16  wqe_index;
 536                         u16     reserved2;
 537                         __be16  packet_length;
 538                         u8      reserved3[12];
 539                 } __packed wqe;
 540                 struct {
 541                         __be32  r_key;
 542                         u16     reserved1;
 543                         __be16  packet_length;
 544                         __be32  rdma_op_len;
 545                         __be64  rdma_va;
 546                 } __packed rdma;
 547         } __packed;
 548         __be32 flags_qpn;
 549 } __packed;
 550
 551 struct mlx5_eqe_vport_change {
 552         u8              rsvd0[2];
 553         __be16          vport_num;
 554         __be32          rsvd1[6];
 555 } __packed;
 556
 557 struct mlx5_eqe_port_module {
 558         u8        reserved_at_0[1];
 559         u8        module;
 560         u8        reserved_at_2[1];
 561         u8        module_status;
 562         u8        reserved_at_4[2];
 563         u8        error_type;
 564 } __packed;
 565
 566 union ev_data {
 567         __be32                          raw[7];
 568         struct mlx5_eqe_cmd             cmd;
 569         struct mlx5_eqe_comp            comp;
 570         struct mlx5_eqe_qp_srq          qp_srq;
 571         struct mlx5_eqe_cq_err          cq_err;
 572         struct mlx5_eqe_port_state      port;
 573         struct mlx5_eqe_gpio            gpio;
 574         struct mlx5_eqe_congestion      cong;
 575         struct mlx5_eqe_stall_vl        stall_vl;
 576         struct mlx5_eqe_page_req        req_pages;
 577         struct mlx5_eqe_page_fault      page_fault;
 578         struct mlx5_eqe_vport_change    vport_change;
 579         struct mlx5_eqe_port_module     port_module;
 580 } __packed;
 581
 582 struct mlx5_eqe {
 583         u8              rsvd0;
 584         u8              type;
 585         u8              rsvd1;
 586         u8              sub_type;
 587         __be32          rsvd2[7];
 588         union ev_data   data;
 589         __be16          rsvd3;
 590         u8              signature;
 591         u8              owner;
 592 } __packed;
 593
 594 struct mlx5_cmd_prot_block {
 595         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 596         u8              rsvd0[48];
 597         __be64          next;
 598         __be32          block_num;
 599         u8              rsvd1;
 600         u8              token;
 601         u8              ctrl_sig;
 602         u8              sig;
 603 };
 604
 605 enum {
 606         MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
 607 };
 608
 609 struct mlx5_err_cqe {
 610         u8      rsvd0[32];
 611         __be32  srqn;
 612         u8      rsvd1[18];
 613         u8      vendor_err_synd;
 614         u8      syndrome;
 615         __be32  s_wqe_opcode_qpn;
 616         __be16  wqe_counter;
 617         u8      signature;
 618         u8      op_own;
 619 };
 620
 621 struct mlx5_cqe64 {
 622         u8              outer_l3_tunneled;
 623         u8              rsvd0;
 624         __be16          wqe_id;
 625         u8              lro_tcppsh_abort_dupack;
 626         u8              lro_min_ttl;
 627         __be16          lro_tcp_win;
 628         __be32          lro_ack_seq_num;
 629         __be32          rss_hash_result;
 630         u8              rss_hash_type;
 631         u8              ml_path;
 632         u8              rsvd20[2];
 633         __be16          check_sum;
 634         __be16          slid;
 635         __be32          flags_rqpn;
 636         u8              hds_ip_ext;
 637         u8              l4_l3_hdr_type;
 638         __be16          vlan_info;
 639         __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
 640         __be32          imm_inval_pkey;
 641         u8              rsvd40[4];
 642         __be32          byte_cnt;
 643         __be32          timestamp_h;
 644         __be32          timestamp_l;
 645         __be32          sop_drop_qpn;
 646         __be16          wqe_counter;
 647         u8              signature;
 648         u8              op_own;
 649 };
 650
 651 struct mlx5_mini_cqe8 {
 652         union {
 653                 __be32 rx_hash_result;
 654                 struct {
 655                         __be16 checksum;
 656                         __be16 rsvd;
 657                 };
 658                 struct {
 659                         __be16 wqe_counter;
 660                         u8  s_wqe_opcode;
 661                         u8  reserved;
 662                 } s_wqe_info;
 663         };
 664         __be32 byte_cnt;
 665 };
 666
 667 enum {
 668         MLX5_NO_INLINE_DATA,
 669         MLX5_INLINE_DATA32_SEG,
 670         MLX5_INLINE_DATA64_SEG,
 671         MLX5_COMPRESSED,
 672 };
 673
 674 enum {
 675         MLX5_CQE_FORMAT_CSUM = 0x1,
 676 };
 677
 678 #define MLX5_MINI_CQE_ARRAY_SIZE 8
 679
 680 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
 681 {
 682         return (cqe->op_own >> 2) & 0x3;
 683 }
 684
 685 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 686 {
 687         return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
 688 }
 689
 690 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
 691 {
 692         return (cqe->l4_l3_hdr_type >> 4) & 0x7;
 693 }
 694
 695 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
 696 {
 697         return (cqe->l4_l3_hdr_type >> 2) & 0x3;
 698 }
 699
 700 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
 701 {
 702         return cqe->outer_l3_tunneled & 0x1;
 703 }
 704
 705 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
 706 {
 707         return !!(cqe->l4_l3_hdr_type & 0x1);
 708 }
 709
 710 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
 711 {
 712         u32 hi, lo;
 713
 714         hi = be32_to_cpu(cqe->timestamp_h);
 715         lo = be32_to_cpu(cqe->timestamp_l);
 716
 717         return (u64)lo | ((u64)hi << 32);
 718 }
 719
 720 struct mpwrq_cqe_bc {
 721         __be16  filler_consumed_strides;
 722         __be16  byte_cnt;
 723 };
 724
 725 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
 726 {
 727         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 728
 729         return be16_to_cpu(bc->byte_cnt);
 730 }
 731
 732 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
 733 {
 734         return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
 735 }
 736
 737 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
 738 {
 739         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 740
 741         return mpwrq_get_cqe_bc_consumed_strides(bc);
 742 }
 743
 744 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
 745 {
 746         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 747
 748         return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
 749 }
 750
 751 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
 752 {
 753         return be16_to_cpu(cqe->wqe_counter);
 754 }
 755
 756 enum {
 757         CQE_L4_HDR_TYPE_NONE                    = 0x0,
 758         CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
 759         CQE_L4_HDR_TYPE_UDP                     = 0x2,
 760         CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
 761         CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
 762 };
 763
 764 enum {
 765         CQE_RSS_HTYPE_IP        = 0x3 << 6,
 766         CQE_RSS_HTYPE_L4        = 0x3 << 2,
 767 };
 768
 769 enum {
 770         MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH        = 0x0,
 771         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6       = 0x1,
 772         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4       = 0x2,
 773 };
 774
 775 enum {
 776         CQE_L2_OK       = 1 << 0,
 777         CQE_L3_OK       = 1 << 1,
 778         CQE_L4_OK       = 1 << 2,
 779 };
 780
 781 struct mlx5_sig_err_cqe {
 782         u8              rsvd0[16];
 783         __be32          expected_trans_sig;
 784         __be32          actual_trans_sig;
 785         __be32          expected_reftag;
 786         __be32          actual_reftag;
 787         __be16          syndrome;
 788         u8              rsvd22[2];
 789         __be32          mkey;
 790         __be64          err_offset;
 791         u8              rsvd30[8];
 792         __be32          qpn;
 793         u8              rsvd38[2];
 794         u8              signature;
 795         u8              op_own;
 796 };
 797
 798 struct mlx5_wqe_srq_next_seg {
 799         u8                      rsvd0[2];
 800         __be16                  next_wqe_index;
 801         u8                      signature;
 802         u8                      rsvd1[11];
 803 };
 804
 805 union mlx5_ext_cqe {
 806         struct ib_grh   grh;
 807         u8              inl[64];
 808 };
 809
 810 struct mlx5_cqe128 {
 811         union mlx5_ext_cqe      inl_grh;
 812         struct mlx5_cqe64       cqe64;
 813 };
 814
 815 enum {
 816         MLX5_MKEY_STATUS_FREE = 1 << 6,
 817 };
 818
 819 enum {
 820         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 821         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 822         MLX5_MKEY_BSF_EN        = 1 << 30,
 823         MLX5_MKEY_LEN64         = 1 << 31,
 824 };
 825
 826 struct mlx5_mkey_seg {
 827         /* This is a two bit field occupying bits 31-30.
 828          * bit 31 is always 0,
 829          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 830          */
 831         u8              status;
 832         u8              pcie_control;
 833         u8              flags;
 834         u8              version;
 835         __be32          qpn_mkey7_0;
 836         u8              rsvd1[4];
 837         __be32          flags_pd;
 838         __be64          start_addr;
 839         __be64          len;
 840         __be32          bsfs_octo_size;
 841         u8              rsvd2[16];
 842         __be32          xlt_oct_size;
 843         u8              rsvd3[3];
 844         u8              log2_page_size;
 845         u8              rsvd4[4];
 846 };
 847
 848 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 849
 850 enum {
 851         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 852 };
 853
 854 enum {
 855         VPORT_STATE_DOWN                = 0x0,
 856         VPORT_STATE_UP                  = 0x1,
 857 };
 858
 859 enum {
 860         MLX5_ESW_VPORT_ADMIN_STATE_DOWN  = 0x0,
 861         MLX5_ESW_VPORT_ADMIN_STATE_UP    = 0x1,
 862         MLX5_ESW_VPORT_ADMIN_STATE_AUTO  = 0x2,
 863 };
 864
 865 enum {
 866         MLX5_L3_PROT_TYPE_IPV4          = 0,
 867         MLX5_L3_PROT_TYPE_IPV6          = 1,
 868 };
 869
 870 enum {
 871         MLX5_L4_PROT_TYPE_TCP           = 0,
 872         MLX5_L4_PROT_TYPE_UDP           = 1,
 873 };
 874
 875 enum {
 876         MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
 877         MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
 878         MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
 879         MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
 880         MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
 881 };
 882
 883 enum {
 884         MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
 885         MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
 886         MLX5_MATCH_INNER_HEADERS        = 1 << 2,
 887
 888 };
 889
 890 enum {
 891         MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
 892         MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
 893 };
 894
 895 enum {
 896         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
 897         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
 898         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
 899 };
 900
 901 enum mlx5_list_type {
 902         MLX5_NVPRT_LIST_TYPE_UC   = 0x0,
 903         MLX5_NVPRT_LIST_TYPE_MC   = 0x1,
 904         MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
 905 };
 906
 907 enum {
 908         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
 909         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
 910 };
 911
 912 enum mlx5_wol_mode {
 913         MLX5_WOL_DISABLE        = 0,
 914         MLX5_WOL_SECURED_MAGIC  = 1 << 1,
 915         MLX5_WOL_MAGIC          = 1 << 2,
 916         MLX5_WOL_ARP            = 1 << 3,
 917         MLX5_WOL_BROADCAST      = 1 << 4,
 918         MLX5_WOL_MULTICAST      = 1 << 5,
 919         MLX5_WOL_UNICAST        = 1 << 6,
 920         MLX5_WOL_PHY_ACTIVITY   = 1 << 7,
 921 };
 922
 923 /* MLX5 DEV CAPs */
 924
 925 /* TODO: EAT.ME */
 926 enum mlx5_cap_mode {
 927         HCA_CAP_OPMOD_GET_MAX   = 0,
 928         HCA_CAP_OPMOD_GET_CUR   = 1,
 929 };
 930
 931 enum mlx5_cap_type {
 932         MLX5_CAP_GENERAL = 0,
 933         MLX5_CAP_ETHERNET_OFFLOADS,
 934         MLX5_CAP_ODP,
 935         MLX5_CAP_ATOMIC,
 936         MLX5_CAP_ROCE,
 937         MLX5_CAP_IPOIB_OFFLOADS,
 938         MLX5_CAP_EOIB_OFFLOADS,
 939         MLX5_CAP_FLOW_TABLE,
 940         MLX5_CAP_ESWITCH_FLOW_TABLE,
 941         MLX5_CAP_ESWITCH,
 942         MLX5_CAP_RESERVED,
 943         MLX5_CAP_VECTOR_CALC,
 944         MLX5_CAP_QOS,
 945         /* NUM OF CAP Types */
 946         MLX5_CAP_NUM
 947 };
 948
 949 /* GET Dev Caps macros */
 950 #define MLX5_CAP_GEN(mdev, cap) \
 951         MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
 952
 953 #define MLX5_CAP_GEN_MAX(mdev, cap) \
 954         MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
 955
 956 #define MLX5_CAP_ETH(mdev, cap) \
 957         MLX5_GET(per_protocol_networking_offload_caps,\
 958                  mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
 959
 960 #define MLX5_CAP_ETH_MAX(mdev, cap) \
 961         MLX5_GET(per_protocol_networking_offload_caps,\
 962                  mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
 963
 964 #define MLX5_CAP_ROCE(mdev, cap) \
 965         MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
 966
 967 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
 968         MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
 969
 970 #define MLX5_CAP_ATOMIC(mdev, cap) \
 971         MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
 972
 973 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
 974         MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
 975
 976 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
 977         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
 978
 979 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
 980         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
 981
 982 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
 983         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
 984
 985 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
 986         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
 987
 988 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
 989         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
 990
 991 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
 992         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
 993
 994 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
 995         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
 996
 997 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
 998         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
 999
1000 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1001         MLX5_GET(flow_table_eswitch_cap, \
1002                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1003
1004 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1005         MLX5_GET(flow_table_eswitch_cap, \
1006                  mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1007
1008 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1009         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1010
1011 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1012         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1013
1014 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1015         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1016
1017 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1018         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1019
1020 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1021         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1022
1023 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1024         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1025
1026 #define MLX5_CAP_ESW(mdev, cap) \
1027         MLX5_GET(e_switch_cap, \
1028                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1029
1030 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1031         MLX5_GET(e_switch_cap, \
1032                  mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1033
1034 #define MLX5_CAP_ODP(mdev, cap)\
1035         MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1036
1037 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1038         MLX5_GET(vector_calc_cap, \
1039                  mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1040
1041 #define MLX5_CAP_QOS(mdev, cap)\
1042         MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1043
1044 enum {
1045         MLX5_CMD_STAT_OK                        = 0x0,
1046         MLX5_CMD_STAT_INT_ERR                   = 0x1,
1047         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
1048         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
1049         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
1050         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
1051         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
1052         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
1053         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
1054         MLX5_CMD_STAT_IX_ERR                    = 0xa,
1055         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
1056         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
1057         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
1058         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
1059         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
1060         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
1061 };
1062
1063 enum {
1064         MLX5_IEEE_802_3_COUNTERS_GROUP        = 0x0,
1065         MLX5_RFC_2863_COUNTERS_GROUP          = 0x1,
1066         MLX5_RFC_2819_COUNTERS_GROUP          = 0x2,
1067         MLX5_RFC_3635_COUNTERS_GROUP          = 0x3,
1068         MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1069         MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1070         MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1071         MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
1072         MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
1073 };
1074
1075 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1076 {
1077         if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1078                 return 0;
1079         return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1080 }
1081
1082 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1083 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1084 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1085 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1086                                 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1087                                 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1088
1089 #endif /* MLX5_DEVICE_H */