include/linux/mlx5/driver.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DRIVER_H
  34 #define MLX5_DRIVER_H
  35
  36 #include <linux/kernel.h>
  37 #include <linux/completion.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock_types.h>
  40 #include <linux/semaphore.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/radix-tree.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/mempool.h>
  46 #include <linux/interrupt.h>
  47
  48 #include <linux/mlx5/device.h>
  49 #include <linux/mlx5/doorbell.h>
  50 #include <linux/mlx5/srq.h>
  51
  52 enum {
  53         MLX5_BOARD_ID_LEN = 64,
  54         MLX5_MAX_NAME_LEN = 16,
  55 };
  56
  57 enum {
  58         /* one minute for the sake of bringup. Generally, commands must always
  59          * complete and we may need to increase this timeout value
  60          */
  61         MLX5_CMD_TIMEOUT_MSEC   = 60 * 1000,
  62         MLX5_CMD_WQ_MAX_NAME    = 32,
  63 };
  64
  65 enum {
  66         CMD_OWNER_SW            = 0x0,
  67         CMD_OWNER_HW            = 0x1,
  68         CMD_STATUS_SUCCESS      = 0,
  69 };
  70
  71 enum mlx5_sqp_t {
  72         MLX5_SQP_SMI            = 0,
  73         MLX5_SQP_GSI            = 1,
  74         MLX5_SQP_IEEE_1588      = 2,
  75         MLX5_SQP_SNIFFER        = 3,
  76         MLX5_SQP_SYNC_UMR       = 4,
  77 };
  78
  79 enum {
  80         MLX5_MAX_PORTS  = 2,
  81 };
  82
  83 enum {
  84         MLX5_EQ_VEC_PAGES        = 0,
  85         MLX5_EQ_VEC_CMD          = 1,
  86         MLX5_EQ_VEC_ASYNC        = 2,
  87         MLX5_EQ_VEC_PFAULT       = 3,
  88         MLX5_EQ_VEC_COMP_BASE,
  89 };
  90
  91 enum {
  92         MLX5_MAX_IRQ_NAME       = 32
  93 };
  94
  95 enum {
  96         MLX5_ATOMIC_MODE_IB_COMP        = 1 << 16,
  97         MLX5_ATOMIC_MODE_CX             = 2 << 16,
  98         MLX5_ATOMIC_MODE_8B             = 3 << 16,
  99         MLX5_ATOMIC_MODE_16B            = 4 << 16,
 100         MLX5_ATOMIC_MODE_32B            = 5 << 16,
 101         MLX5_ATOMIC_MODE_64B            = 6 << 16,
 102         MLX5_ATOMIC_MODE_128B           = 7 << 16,
 103         MLX5_ATOMIC_MODE_256B           = 8 << 16,
 104 };
 105
 106 enum {
 107         MLX5_REG_QETCR           = 0x4005,
 108         MLX5_REG_QTCT            = 0x400a,
 109         MLX5_REG_DCBX_PARAM      = 0x4020,
 110         MLX5_REG_DCBX_APP        = 0x4021,
 111         MLX5_REG_PCAP            = 0x5001,
 112         MLX5_REG_PMTU            = 0x5003,
 113         MLX5_REG_PTYS            = 0x5004,
 114         MLX5_REG_PAOS            = 0x5006,
 115         MLX5_REG_PFCC            = 0x5007,
 116         MLX5_REG_PPCNT           = 0x5008,
 117         MLX5_REG_PMAOS           = 0x5012,
 118         MLX5_REG_PUDE            = 0x5009,
 119         MLX5_REG_PMPE            = 0x5010,
 120         MLX5_REG_PELC            = 0x500e,
 121         MLX5_REG_PVLC            = 0x500f,
 122         MLX5_REG_PCMR            = 0x5041,
 123         MLX5_REG_PMLP            = 0x5002,
 124         MLX5_REG_PCAM            = 0x507f,
 125         MLX5_REG_NODE_DESC       = 0x6001,
 126         MLX5_REG_HOST_ENDIANNESS = 0x7004,
 127         MLX5_REG_MCIA            = 0x9014,
 128         MLX5_REG_MLCR            = 0x902b,
 129         MLX5_REG_MPCNT           = 0x9051,
 130         MLX5_REG_MTPPS           = 0x9053,
 131         MLX5_REG_MTPPSE          = 0x9054,
 132         MLX5_REG_MCAM            = 0x907f,
 133 };
 134
 135 enum mlx5_dcbx_oper_mode {
 136         MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
 137         MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
 138 };
 139
 140 enum {
 141         MLX5_ATOMIC_OPS_CMP_SWAP        = 1 << 0,
 142         MLX5_ATOMIC_OPS_FETCH_ADD       = 1 << 1,
 143 };
 144
 145 enum mlx5_page_fault_resume_flags {
 146         MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
 147         MLX5_PAGE_FAULT_RESUME_WRITE     = 1 << 1,
 148         MLX5_PAGE_FAULT_RESUME_RDMA      = 1 << 2,
 149         MLX5_PAGE_FAULT_RESUME_ERROR     = 1 << 7,
 150 };
 151
 152 enum dbg_rsc_type {
 153         MLX5_DBG_RSC_QP,
 154         MLX5_DBG_RSC_EQ,
 155         MLX5_DBG_RSC_CQ,
 156 };
 157
 158 struct mlx5_field_desc {
 159         struct dentry          *dent;
 160         int                     i;
 161 };
 162
 163 struct mlx5_rsc_debug {
 164         struct mlx5_core_dev   *dev;
 165         void                   *object;
 166         enum dbg_rsc_type       type;
 167         struct dentry          *root;
 168         struct mlx5_field_desc  fields[0];
 169 };
 170
 171 enum mlx5_dev_event {
 172         MLX5_DEV_EVENT_SYS_ERROR,
 173         MLX5_DEV_EVENT_PORT_UP,
 174         MLX5_DEV_EVENT_PORT_DOWN,
 175         MLX5_DEV_EVENT_PORT_INITIALIZED,
 176         MLX5_DEV_EVENT_LID_CHANGE,
 177         MLX5_DEV_EVENT_PKEY_CHANGE,
 178         MLX5_DEV_EVENT_GUID_CHANGE,
 179         MLX5_DEV_EVENT_CLIENT_REREG,
 180         MLX5_DEV_EVENT_PPS,
 181 };
 182
 183 enum mlx5_port_status {
 184         MLX5_PORT_UP        = 1,
 185         MLX5_PORT_DOWN      = 2,
 186 };
 187
 188 enum mlx5_eq_type {
 189         MLX5_EQ_TYPE_COMP,
 190         MLX5_EQ_TYPE_ASYNC,
 191 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 192         MLX5_EQ_TYPE_PF,
 193 #endif
 194 };
 195
 196 struct mlx5_bfreg_info {
 197         u32                    *sys_pages;
 198         int                     num_low_latency_bfregs;
 199         unsigned int           *count;
 200
 201         /*
 202          * protect bfreg allocation data structs
 203          */
 204         struct mutex            lock;
 205         u32                     ver;
 206         bool                    lib_uar_4k;
 207         u32                     num_sys_pages;
 208 };
 209
 210 struct mlx5_cmd_first {
 211         __be32          data[4];
 212 };
 213
 214 struct mlx5_cmd_msg {
 215         struct list_head                list;
 216         struct cmd_msg_cache           *parent;
 217         u32                             len;
 218         struct mlx5_cmd_first           first;
 219         struct mlx5_cmd_mailbox        *next;
 220 };
 221
 222 struct mlx5_cmd_debug {
 223         struct dentry          *dbg_root;
 224         struct dentry          *dbg_in;
 225         struct dentry          *dbg_out;
 226         struct dentry          *dbg_outlen;
 227         struct dentry          *dbg_status;
 228         struct dentry          *dbg_run;
 229         void                   *in_msg;
 230         void                   *out_msg;
 231         u8                      status;
 232         u16                     inlen;
 233         u16                     outlen;
 234 };
 235
 236 struct cmd_msg_cache {
 237         /* protect block chain allocations
 238          */
 239         spinlock_t              lock;
 240         struct list_head        head;
 241         unsigned int            max_inbox_size;
 242         unsigned int            num_ent;
 243 };
 244
 245 enum {
 246         MLX5_NUM_COMMAND_CACHES = 5,
 247 };
 248
 249 struct mlx5_cmd_stats {
 250         u64             sum;
 251         u64             n;
 252         struct dentry  *root;
 253         struct dentry  *avg;
 254         struct dentry  *count;
 255         /* protect command average calculations */
 256         spinlock_t      lock;
 257 };
 258
 259 struct mlx5_cmd {
 260         void           *cmd_alloc_buf;
 261         dma_addr_t      alloc_dma;
 262         int             alloc_size;
 263         void           *cmd_buf;
 264         dma_addr_t      dma;
 265         u16             cmdif_rev;
 266         u8              log_sz;
 267         u8              log_stride;
 268         int             max_reg_cmds;
 269         int             events;
 270         u32 __iomem    *vector;
 271
 272         /* protect command queue allocations
 273          */
 274         spinlock_t      alloc_lock;
 275
 276         /* protect token allocations
 277          */
 278         spinlock_t      token_lock;
 279         u8              token;
 280         unsigned long   bitmask;
 281         char            wq_name[MLX5_CMD_WQ_MAX_NAME];
 282         struct workqueue_struct *wq;
 283         struct semaphore sem;
 284         struct semaphore pages_sem;
 285         int     mode;
 286         struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
 287         struct pci_pool *pool;
 288         struct mlx5_cmd_debug dbg;
 289         struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
 290         int checksum_disabled;
 291         struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
 292 };
 293
 294 struct mlx5_port_caps {
 295         int     gid_table_len;
 296         int     pkey_table_len;
 297         u8      ext_port_cap;
 298         bool    has_smi;
 299 };
 300
 301 struct mlx5_cmd_mailbox {
 302         void           *buf;
 303         dma_addr_t      dma;
 304         struct mlx5_cmd_mailbox *next;
 305 };
 306
 307 struct mlx5_buf_list {
 308         void                   *buf;
 309         dma_addr_t              map;
 310 };
 311
 312 struct mlx5_buf {
 313         struct mlx5_buf_list    direct;
 314         int                     npages;
 315         int                     size;
 316         u8                      page_shift;
 317 };
 318
 319 struct mlx5_frag_buf {
 320         struct mlx5_buf_list    *frags;
 321         int                     npages;
 322         int                     size;
 323         u8                      page_shift;
 324 };
 325
 326 struct mlx5_eq_tasklet {
 327         struct list_head list;
 328         struct list_head process_list;
 329         struct tasklet_struct task;
 330         /* lock on completion tasklet list */
 331         spinlock_t lock;
 332 };
 333
 334 struct mlx5_eq_pagefault {
 335         struct work_struct       work;
 336         /* Pagefaults lock */
 337         spinlock_t               lock;
 338         struct workqueue_struct *wq;
 339         mempool_t               *pool;
 340 };
 341
 342 struct mlx5_eq {
 343         struct mlx5_core_dev   *dev;
 344         __be32 __iomem         *doorbell;
 345         u32                     cons_index;
 346         struct mlx5_buf         buf;
 347         int                     size;
 348         unsigned int            irqn;
 349         u8                      eqn;
 350         int                     nent;
 351         u64                     mask;
 352         struct list_head        list;
 353         int                     index;
 354         struct mlx5_rsc_debug   *dbg;
 355         enum mlx5_eq_type       type;
 356         union {
 357                 struct mlx5_eq_tasklet   tasklet_ctx;
 358 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 359                 struct mlx5_eq_pagefault pf_ctx;
 360 #endif
 361         };
 362 };
 363
 364 struct mlx5_core_psv {
 365         u32     psv_idx;
 366         struct psv_layout {
 367                 u32     pd;
 368                 u16     syndrome;
 369                 u16     reserved;
 370                 u16     bg;
 371                 u16     app_tag;
 372                 u32     ref_tag;
 373         } psv;
 374 };
 375
 376 struct mlx5_core_sig_ctx {
 377         struct mlx5_core_psv    psv_memory;
 378         struct mlx5_core_psv    psv_wire;
 379         struct ib_sig_err       err_item;
 380         bool                    sig_status_checked;
 381         bool                    sig_err_exists;
 382         u32                     sigerr_count;
 383 };
 384
 385 enum {
 386         MLX5_MKEY_MR = 1,
 387         MLX5_MKEY_MW,
 388 };
 389
 390 struct mlx5_core_mkey {
 391         u64                     iova;
 392         u64                     size;
 393         u32                     key;
 394         u32                     pd;
 395         u32                     type;
 396 };
 397
 398 #define MLX5_24BIT_MASK         ((1 << 24) - 1)
 399
 400 enum mlx5_res_type {
 401         MLX5_RES_QP     = MLX5_EVENT_QUEUE_TYPE_QP,
 402         MLX5_RES_RQ     = MLX5_EVENT_QUEUE_TYPE_RQ,
 403         MLX5_RES_SQ     = MLX5_EVENT_QUEUE_TYPE_SQ,
 404         MLX5_RES_SRQ    = 3,
 405         MLX5_RES_XSRQ   = 4,
 406 };
 407
 408 struct mlx5_core_rsc_common {
 409         enum mlx5_res_type      res;
 410         atomic_t                refcount;
 411         struct completion       free;
 412 };
 413
 414 struct mlx5_core_srq {
 415         struct mlx5_core_rsc_common     common; /* must be first */
 416         u32             srqn;
 417         int             max;
 418         int             max_gs;
 419         int             max_avail_gather;
 420         int             wqe_shift;
 421         void (*event)   (struct mlx5_core_srq *, enum mlx5_event);
 422
 423         atomic_t                refcount;
 424         struct completion       free;
 425 };
 426
 427 struct mlx5_eq_table {
 428         void __iomem           *update_ci;
 429         void __iomem           *update_arm_ci;
 430         struct list_head        comp_eqs_list;
 431         struct mlx5_eq          pages_eq;
 432         struct mlx5_eq          async_eq;
 433         struct mlx5_eq          cmd_eq;
 434 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 435         struct mlx5_eq          pfault_eq;
 436 #endif
 437         int                     num_comp_vectors;
 438         /* protect EQs list
 439          */
 440         spinlock_t              lock;
 441 };
 442
 443 struct mlx5_uars_page {
 444         void __iomem           *map;
 445         bool                    wc;
 446         u32                     index;
 447         struct list_head        list;
 448         unsigned int            bfregs;
 449         unsigned long          *reg_bitmap; /* for non fast path bf regs */
 450         unsigned long          *fp_bitmap;
 451         unsigned int            reg_avail;
 452         unsigned int            fp_avail;
 453         struct kref             ref_count;
 454         struct mlx5_core_dev   *mdev;
 455 };
 456
 457 struct mlx5_bfreg_head {
 458         /* protect blue flame registers allocations */
 459         struct mutex            lock;
 460         struct list_head        list;
 461 };
 462
 463 struct mlx5_bfreg_data {
 464         struct mlx5_bfreg_head  reg_head;
 465         struct mlx5_bfreg_head  wc_head;
 466 };
 467
 468 struct mlx5_sq_bfreg {
 469         void __iomem           *map;
 470         struct mlx5_uars_page  *up;
 471         bool                    wc;
 472         u32                     index;
 473         unsigned int            offset;
 474 };
 475
 476 struct mlx5_core_health {
 477         struct health_buffer __iomem   *health;
 478         __be32 __iomem                 *health_counter;
 479         struct timer_list               timer;
 480         u32                             prev;
 481         int                             miss_counter;
 482         bool                            sick;
 483         /* wq spinlock to synchronize draining */
 484         spinlock_t                      wq_lock;
 485         struct workqueue_struct        *wq;
 486         unsigned long                   flags;
 487         struct work_struct              work;
 488         struct delayed_work             recover_work;
 489 };
 490
 491 struct mlx5_cq_table {
 492         /* protect radix tree
 493          */
 494         spinlock_t              lock;
 495         struct radix_tree_root  tree;
 496 };
 497
 498 struct mlx5_qp_table {
 499         /* protect radix tree
 500          */
 501         spinlock_t              lock;
 502         struct radix_tree_root  tree;
 503 };
 504
 505 struct mlx5_srq_table {
 506         /* protect radix tree
 507          */
 508         spinlock_t              lock;
 509         struct radix_tree_root  tree;
 510 };
 511
 512 struct mlx5_mkey_table {
 513         /* protect radix tree
 514          */
 515         rwlock_t                lock;
 516         struct radix_tree_root  tree;
 517 };
 518
 519 struct mlx5_vf_context {
 520         int     enabled;
 521 };
 522
 523 struct mlx5_core_sriov {
 524         struct mlx5_vf_context  *vfs_ctx;
 525         int                     num_vfs;
 526         int                     enabled_vfs;
 527 };
 528
 529 struct mlx5_irq_info {
 530         cpumask_var_t mask;
 531         char name[MLX5_MAX_IRQ_NAME];
 532 };
 533
 534 struct mlx5_fc_stats {
 535         struct rb_root counters;
 536         struct list_head addlist;
 537         /* protect addlist add/splice operations */
 538         spinlock_t addlist_lock;
 539
 540         struct workqueue_struct *wq;
 541         struct delayed_work work;
 542         unsigned long next_query;
 543 };
 544
 545 struct mlx5_eswitch;
 546 struct mlx5_lag;
 547 struct mlx5_pagefault;
 548
 549 struct mlx5_rl_entry {
 550         u32                     rate;
 551         u16                     index;
 552         u16                     refcount;
 553 };
 554
 555 struct mlx5_rl_table {
 556         /* protect rate limit table */
 557         struct mutex            rl_lock;
 558         u16                     max_size;
 559         u32                     max_rate;
 560         u32                     min_rate;
 561         struct mlx5_rl_entry   *rl_entry;
 562 };
 563
 564 enum port_module_event_status_type {
 565         MLX5_MODULE_STATUS_PLUGGED   = 0x1,
 566         MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
 567         MLX5_MODULE_STATUS_ERROR     = 0x3,
 568         MLX5_MODULE_STATUS_NUM       = 0x3,
 569 };
 570
 571 enum  port_module_event_error_type {
 572         MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
 573         MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
 574         MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
 575         MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
 576         MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
 577         MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
 578         MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
 579         MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
 580         MLX5_MODULE_EVENT_ERROR_UNKNOWN,
 581         MLX5_MODULE_EVENT_ERROR_NUM,
 582 };
 583
 584 struct mlx5_port_module_event_stats {
 585         u64 status_counters[MLX5_MODULE_STATUS_NUM];
 586         u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
 587 };
 588
 589 struct mlx5_priv {
 590         char                    name[MLX5_MAX_NAME_LEN];
 591         struct mlx5_eq_table    eq_table;
 592         struct msix_entry       *msix_arr;
 593         struct mlx5_irq_info    *irq_info;
 594
 595         /* pages stuff */
 596         struct workqueue_struct *pg_wq;
 597         struct rb_root          page_root;
 598         int                     fw_pages;
 599         atomic_t                reg_pages;
 600         struct list_head        free_list;
 601         int                     vfs_pages;
 602
 603         struct mlx5_core_health health;
 604
 605         struct mlx5_srq_table   srq_table;
 606
 607         /* start: qp staff */
 608         struct mlx5_qp_table    qp_table;
 609         struct dentry          *qp_debugfs;
 610         struct dentry          *eq_debugfs;
 611         struct dentry          *cq_debugfs;
 612         struct dentry          *cmdif_debugfs;
 613         /* end: qp staff */
 614
 615         /* start: cq staff */
 616         struct mlx5_cq_table    cq_table;
 617         /* end: cq staff */
 618
 619         /* start: mkey staff */
 620         struct mlx5_mkey_table  mkey_table;
 621         /* end: mkey staff */
 622
 623         /* start: alloc staff */
 624         /* protect buffer alocation according to numa node */
 625         struct mutex            alloc_mutex;
 626         int                     numa_node;
 627
 628         struct mutex            pgdir_mutex;
 629         struct list_head        pgdir_list;
 630         /* end: alloc staff */
 631         struct dentry          *dbg_root;
 632
 633         /* protect mkey key part */
 634         spinlock_t              mkey_lock;
 635         u8                      mkey_key;
 636
 637         struct list_head        dev_list;
 638         struct list_head        ctx_list;
 639         spinlock_t              ctx_lock;
 640
 641         struct mlx5_flow_steering *steering;
 642         struct mlx5_eswitch     *eswitch;
 643         struct mlx5_core_sriov  sriov;
 644         struct mlx5_lag         *lag;
 645         unsigned long           pci_dev_data;
 646         struct mlx5_fc_stats            fc_stats;
 647         struct mlx5_rl_table            rl_table;
 648
 649         struct mlx5_port_module_event_stats  pme_stats;
 650
 651 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 652         void                  (*pfault)(struct mlx5_core_dev *dev,
 653                                         void *context,
 654                                         struct mlx5_pagefault *pfault);
 655         void                   *pfault_ctx;
 656         struct srcu_struct      pfault_srcu;
 657 #endif
 658         struct mlx5_bfreg_data          bfregs;
 659         struct mlx5_uars_page          *uar;
 660 };
 661
 662 enum mlx5_device_state {
 663         MLX5_DEVICE_STATE_UP,
 664         MLX5_DEVICE_STATE_INTERNAL_ERROR,
 665 };
 666
 667 enum mlx5_interface_state {
 668         MLX5_INTERFACE_STATE_DOWN = BIT(0),
 669         MLX5_INTERFACE_STATE_UP = BIT(1),
 670         MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
 671 };
 672
 673 enum mlx5_pci_status {
 674         MLX5_PCI_STATUS_DISABLED,
 675         MLX5_PCI_STATUS_ENABLED,
 676 };
 677
 678 enum mlx5_pagefault_type_flags {
 679         MLX5_PFAULT_REQUESTOR = 1 << 0,
 680         MLX5_PFAULT_WRITE     = 1 << 1,
 681         MLX5_PFAULT_RDMA      = 1 << 2,
 682 };
 683
 684 /* Contains the details of a pagefault. */
 685 struct mlx5_pagefault {
 686         u32                     bytes_committed;
 687         u32                     token;
 688         u8                      event_subtype;
 689         u8                      type;
 690         union {
 691                 /* Initiator or send message responder pagefault details. */
 692                 struct {
 693                         /* Received packet size, only valid for responders. */
 694                         u32     packet_size;
 695                         /*
 696                          * Number of resource holding WQE, depends on type.
 697                          */
 698                         u32     wq_num;
 699                         /*
 700                          * WQE index. Refers to either the send queue or
 701                          * receive queue, according to event_subtype.
 702                          */
 703                         u16     wqe_index;
 704                 } wqe;
 705                 /* RDMA responder pagefault details */
 706                 struct {
 707                         u32     r_key;
 708                         /*
 709                          * Received packet size, minimal size page fault
 710                          * resolution required for forward progress.
 711                          */
 712                         u32     packet_size;
 713                         u32     rdma_op_len;
 714                         u64     rdma_va;
 715                 } rdma;
 716         };
 717
 718         struct mlx5_eq         *eq;
 719         struct work_struct      work;
 720 };
 721
 722 struct mlx5_td {
 723         struct list_head tirs_list;
 724         u32              tdn;
 725 };
 726
 727 struct mlx5e_resources {
 728         u32                        pdn;
 729         struct mlx5_td             td;
 730         struct mlx5_core_mkey      mkey;
 731 };
 732
 733 struct mlx5_core_dev {
 734         struct pci_dev         *pdev;
 735         /* sync pci state */
 736         struct mutex            pci_status_mutex;
 737         enum mlx5_pci_status    pci_status;
 738         u8                      rev_id;
 739         char                    board_id[MLX5_BOARD_ID_LEN];
 740         struct mlx5_cmd         cmd;
 741         struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
 742         struct {
 743                 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 744                 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 745                 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
 746                 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
 747         } caps;
 748         phys_addr_t             iseg_base;
 749         struct mlx5_init_seg __iomem *iseg;
 750         enum mlx5_device_state  state;
 751         /* sync interface state */
 752         struct mutex            intf_state_mutex;
 753         unsigned long           intf_state;
 754         void                    (*event) (struct mlx5_core_dev *dev,
 755                                           enum mlx5_dev_event event,
 756                                           unsigned long param);
 757         struct mlx5_priv        priv;
 758         struct mlx5_profile     *profile;
 759         atomic_t                num_qps;
 760         u32                     issi;
 761         struct mlx5e_resources  mlx5e_res;
 762 #ifdef CONFIG_RFS_ACCEL
 763         struct cpu_rmap         *rmap;
 764 #endif
 765 };
 766
 767 struct mlx5_db {
 768         __be32                  *db;
 769         union {
 770                 struct mlx5_db_pgdir            *pgdir;
 771                 struct mlx5_ib_user_db_page     *user_page;
 772         }                       u;
 773         dma_addr_t              dma;
 774         int                     index;
 775 };
 776
 777 enum {
 778         MLX5_COMP_EQ_SIZE = 1024,
 779 };
 780
 781 enum {
 782         MLX5_PTYS_IB = 1 << 0,
 783         MLX5_PTYS_EN = 1 << 2,
 784 };
 785
 786 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
 787
 788 struct mlx5_cmd_work_ent {
 789         struct mlx5_cmd_msg    *in;
 790         struct mlx5_cmd_msg    *out;
 791         void                   *uout;
 792         int                     uout_size;
 793         mlx5_cmd_cbk_t          callback;
 794         struct delayed_work     cb_timeout_work;
 795         void                   *context;
 796         int                     idx;
 797         struct completion       done;
 798         struct mlx5_cmd        *cmd;
 799         struct work_struct      work;
 800         struct mlx5_cmd_layout *lay;
 801         int                     ret;
 802         int                     page_queue;
 803         u8                      status;
 804         u8                      token;
 805         u64                     ts1;
 806         u64                     ts2;
 807         u16                     op;
 808 };
 809
 810 struct mlx5_pas {
 811         u64     pa;
 812         u8      log_sz;
 813 };
 814
 815 enum port_state_policy {
 816         MLX5_POLICY_DOWN        = 0,
 817         MLX5_POLICY_UP          = 1,
 818         MLX5_POLICY_FOLLOW      = 2,
 819         MLX5_POLICY_INVALID     = 0xffffffff
 820 };
 821
 822 enum phy_port_state {
 823         MLX5_AAA_111
 824 };
 825
 826 struct mlx5_hca_vport_context {
 827         u32                     field_select;
 828         bool                    sm_virt_aware;
 829         bool                    has_smi;
 830         bool                    has_raw;
 831         enum port_state_policy  policy;
 832         enum phy_port_state     phys_state;
 833         enum ib_port_state      vport_state;
 834         u8                      port_physical_state;
 835         u64                     sys_image_guid;
 836         u64                     port_guid;
 837         u64                     node_guid;
 838         u32                     cap_mask1;
 839         u32                     cap_mask1_perm;
 840         u32                     cap_mask2;
 841         u32                     cap_mask2_perm;
 842         u16                     lid;
 843         u8                      init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
 844         u8                      lmc;
 845         u8                      subnet_timeout;
 846         u16                     sm_lid;
 847         u8                      sm_sl;
 848         u16                     qkey_violation_counter;
 849         u16                     pkey_violation_counter;
 850         bool                    grh_required;
 851 };
 852
 853 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 854 {
 855                 return buf->direct.buf + offset;
 856 }
 857
 858 extern struct workqueue_struct *mlx5_core_wq;
 859
 860 #define STRUCT_FIELD(header, field) \
 861         .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
 862         .struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
 863
 864 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
 865 {
 866         return pci_get_drvdata(pdev);
 867 }
 868
 869 extern struct dentry *mlx5_debugfs_root;
 870
 871 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
 872 {
 873         return ioread32be(&dev->iseg->fw_rev) & 0xffff;
 874 }
 875
 876 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
 877 {
 878         return ioread32be(&dev->iseg->fw_rev) >> 16;
 879 }
 880
 881 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
 882 {
 883         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
 884 }
 885
 886 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
 887 {
 888         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 889 }
 890
 891 static inline void *mlx5_vzalloc(unsigned long size)
 892 {
 893         void *rtn;
 894
 895         rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
 896         if (!rtn)
 897                 rtn = vzalloc(size);
 898         return rtn;
 899 }
 900
 901 static inline u32 mlx5_base_mkey(const u32 key)
 902 {
 903         return key & 0xffffff00u;
 904 }
 905
 906 int mlx5_cmd_init(struct mlx5_core_dev *dev);
 907 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 908 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 909 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 910
 911 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 912                   int out_size);
 913 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
 914                      void *out, int out_size, mlx5_cmd_cbk_t callback,
 915                      void *context);
 916 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
 917
 918 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 919 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 920 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 921 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
 922 int mlx5_health_init(struct mlx5_core_dev *dev);
 923 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 924 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
 925 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
 926 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 927                         struct mlx5_buf *buf, int node);
 928 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
 929 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 930 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 931                              struct mlx5_frag_buf *buf, int node);
 932 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
 933 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 934                                                       gfp_t flags, int npages);
 935 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 936                                  struct mlx5_cmd_mailbox *head);
 937 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 938                          struct mlx5_srq_attr *in);
 939 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
 940 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 941                         struct mlx5_srq_attr *out);
 942 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 943                       u16 lwm, int is_srq);
 944 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
 945 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
 946 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
 947                              struct mlx5_core_mkey *mkey,
 948                              u32 *in, int inlen,
 949                              u32 *out, int outlen,
 950                              mlx5_cmd_cbk_t callback, void *context);
 951 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
 952                           struct mlx5_core_mkey *mkey,
 953                           u32 *in, int inlen);
 954 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
 955                            struct mlx5_core_mkey *mkey);
 956 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
 957                          u32 *out, int outlen);
 958 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
 959                              u32 *mkey);
 960 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
 961 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
 962 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
 963                       u16 opmod, u8 port);
 964 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
 965 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
 966 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
 967 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
 968 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
 969                                  s32 npages);
 970 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
 971 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
 972 void mlx5_register_debugfs(void);
 973 void mlx5_unregister_debugfs(void);
 974 int mlx5_eq_init(struct mlx5_core_dev *dev);
 975 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
 976 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
 977 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
 978 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
 979 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
 980 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
 981 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
 982 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
 983 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
 984 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 985                        int nent, u64 mask, const char *name,
 986                        enum mlx5_eq_type type);
 987 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 988 int mlx5_start_eqs(struct mlx5_core_dev *dev);
 989 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
 990 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
 991                     unsigned int *irqn);
 992 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 993 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 994
 995 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
 996 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
 997 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
 998                          int size_in, void *data_out, int size_out,
 999                          u16 reg_num, int arg, int write);
1000
1001 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1002 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1003 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1004                        u32 *out, int outlen);
1005 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1006 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1007 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1008 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1009 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1010 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1011                        int node);
1012 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1013
1014 const char *mlx5_command_str(int command);
1015 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1016 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1017 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1018                          int npsvs, u32 *sig_index);
1019 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1020 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1021 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1022                         struct mlx5_odp_caps *odp_caps);
1023 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1024                              u8 port_num, void *out, size_t sz);
1025 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1026 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1027                                 u32 wq_num, u8 type, int error);
1028 #endif
1029
1030 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1031 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1032 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1033 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1034 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1035 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1036                      bool map_wc, bool fast_path);
1037 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1038
1039 static inline int fw_initializing(struct mlx5_core_dev *dev)
1040 {
1041         return ioread32be(&dev->iseg->initializing) >> 31;
1042 }
1043
1044 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1045 {
1046         return mkey >> 8;
1047 }
1048
1049 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1050 {
1051         return mkey_idx << 8;
1052 }
1053
1054 static inline u8 mlx5_mkey_variant(u32 mkey)
1055 {
1056         return mkey & 0xff;
1057 }
1058
1059 enum {
1060         MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
1061         MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
1062 };
1063
1064 enum {
1065         MAX_UMR_CACHE_ENTRY = 20,
1066         MLX5_IMR_MTT_CACHE_ENTRY,
1067         MLX5_IMR_KSM_CACHE_ENTRY,
1068         MAX_MR_CACHE_ENTRIES
1069 };
1070
1071 enum {
1072         MLX5_INTERFACE_PROTOCOL_IB  = 0,
1073         MLX5_INTERFACE_PROTOCOL_ETH = 1,
1074 };
1075
1076 struct mlx5_interface {
1077         void *                  (*add)(struct mlx5_core_dev *dev);
1078         void                    (*remove)(struct mlx5_core_dev *dev, void *context);
1079         int                     (*attach)(struct mlx5_core_dev *dev, void *context);
1080         void                    (*detach)(struct mlx5_core_dev *dev, void *context);
1081         void                    (*event)(struct mlx5_core_dev *dev, void *context,
1082                                          enum mlx5_dev_event event, unsigned long param);
1083         void                    (*pfault)(struct mlx5_core_dev *dev,
1084                                           void *context,
1085                                           struct mlx5_pagefault *pfault);
1086         void *                  (*get_dev)(void *context);
1087         int                     protocol;
1088         struct list_head        list;
1089 };
1090
1091 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1092 int mlx5_register_interface(struct mlx5_interface *intf);
1093 void mlx5_unregister_interface(struct mlx5_interface *intf);
1094 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1095
1096 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1097 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1098 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1099 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1100 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1101 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1102
1103 struct mlx5_profile {
1104         u64     mask;
1105         u8      log_max_qp;
1106         struct {
1107                 int     size;
1108                 int     limit;
1109         } mr_cache[MAX_MR_CACHE_ENTRIES];
1110 };
1111
1112 enum {
1113         MLX5_PCI_DEV_IS_VF              = 1 << 0,
1114 };
1115
1116 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1117 {
1118         return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1119 }
1120
1121 static inline int mlx5_get_gid_table_len(u16 param)
1122 {
1123         if (param > 4) {
1124                 pr_warn("gid table length is zero\n");
1125                 return 0;
1126         }
1127
1128         return 8 * (1 << param);
1129 }
1130
1131 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1132 {
1133         return !!(dev->priv.rl_table.max_size);
1134 }
1135
1136 enum {
1137         MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1138 };
1139
1140 #endif /* MLX5_DRIVER_H */