2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
57 MLX5_BOARD_ID_LEN
= 64,
58 MLX5_MAX_NAME_LEN
= 16,
62 /* one minute for the sake of bringup. Generally, commands must always
63 * complete and we may need to increase this timeout value
65 MLX5_CMD_TIMEOUT_MSEC
= 60 * 1000,
66 MLX5_CMD_WQ_MAX_NAME
= 32,
72 CMD_STATUS_SUCCESS
= 0,
78 MLX5_SQP_IEEE_1588
= 2,
80 MLX5_SQP_SYNC_UMR
= 4,
88 MLX5_EQ_VEC_PAGES
= 0,
90 MLX5_EQ_VEC_ASYNC
= 2,
91 MLX5_EQ_VEC_PFAULT
= 3,
92 MLX5_EQ_VEC_COMP_BASE
,
96 MLX5_MAX_IRQ_NAME
= 32
100 MLX5_ATOMIC_MODE_IB_COMP
= 1 << 16,
101 MLX5_ATOMIC_MODE_CX
= 2 << 16,
102 MLX5_ATOMIC_MODE_8B
= 3 << 16,
103 MLX5_ATOMIC_MODE_16B
= 4 << 16,
104 MLX5_ATOMIC_MODE_32B
= 5 << 16,
105 MLX5_ATOMIC_MODE_64B
= 6 << 16,
106 MLX5_ATOMIC_MODE_128B
= 7 << 16,
107 MLX5_ATOMIC_MODE_256B
= 8 << 16,
111 MLX5_REG_QPTS
= 0x4002,
112 MLX5_REG_QETCR
= 0x4005,
113 MLX5_REG_QTCT
= 0x400a,
114 MLX5_REG_QPDPM
= 0x4013,
115 MLX5_REG_QCAM
= 0x4019,
116 MLX5_REG_DCBX_PARAM
= 0x4020,
117 MLX5_REG_DCBX_APP
= 0x4021,
118 MLX5_REG_FPGA_CAP
= 0x4022,
119 MLX5_REG_FPGA_CTRL
= 0x4023,
120 MLX5_REG_FPGA_ACCESS_REG
= 0x4024,
121 MLX5_REG_PCAP
= 0x5001,
122 MLX5_REG_PMTU
= 0x5003,
123 MLX5_REG_PTYS
= 0x5004,
124 MLX5_REG_PAOS
= 0x5006,
125 MLX5_REG_PFCC
= 0x5007,
126 MLX5_REG_PPCNT
= 0x5008,
127 MLX5_REG_PMAOS
= 0x5012,
128 MLX5_REG_PUDE
= 0x5009,
129 MLX5_REG_PMPE
= 0x5010,
130 MLX5_REG_PELC
= 0x500e,
131 MLX5_REG_PVLC
= 0x500f,
132 MLX5_REG_PCMR
= 0x5041,
133 MLX5_REG_PMLP
= 0x5002,
134 MLX5_REG_PCAM
= 0x507f,
135 MLX5_REG_NODE_DESC
= 0x6001,
136 MLX5_REG_HOST_ENDIANNESS
= 0x7004,
137 MLX5_REG_MCIA
= 0x9014,
138 MLX5_REG_MLCR
= 0x902b,
139 MLX5_REG_MPCNT
= 0x9051,
140 MLX5_REG_MTPPS
= 0x9053,
141 MLX5_REG_MTPPSE
= 0x9054,
142 MLX5_REG_MCQI
= 0x9061,
143 MLX5_REG_MCC
= 0x9062,
144 MLX5_REG_MCDA
= 0x9063,
145 MLX5_REG_MCAM
= 0x907f,
148 enum mlx5_qpts_trust_state
{
149 MLX5_QPTS_TRUST_PCP
= 1,
150 MLX5_QPTS_TRUST_DSCP
= 2,
153 enum mlx5_dcbx_oper_mode
{
154 MLX5E_DCBX_PARAM_VER_OPER_HOST
= 0x0,
155 MLX5E_DCBX_PARAM_VER_OPER_AUTO
= 0x3,
158 enum mlx5_dct_atomic_mode
{
159 MLX5_ATOMIC_MODE_DCT_OFF
= 20,
160 MLX5_ATOMIC_MODE_DCT_NONE
= 0 << MLX5_ATOMIC_MODE_DCT_OFF
,
161 MLX5_ATOMIC_MODE_DCT_IB_COMP
= 1 << MLX5_ATOMIC_MODE_DCT_OFF
,
162 MLX5_ATOMIC_MODE_DCT_CX
= 2 << MLX5_ATOMIC_MODE_DCT_OFF
,
166 MLX5_ATOMIC_OPS_CMP_SWAP
= 1 << 0,
167 MLX5_ATOMIC_OPS_FETCH_ADD
= 1 << 1,
170 enum mlx5_page_fault_resume_flags
{
171 MLX5_PAGE_FAULT_RESUME_REQUESTOR
= 1 << 0,
172 MLX5_PAGE_FAULT_RESUME_WRITE
= 1 << 1,
173 MLX5_PAGE_FAULT_RESUME_RDMA
= 1 << 2,
174 MLX5_PAGE_FAULT_RESUME_ERROR
= 1 << 7,
183 enum port_state_policy
{
184 MLX5_POLICY_DOWN
= 0,
186 MLX5_POLICY_FOLLOW
= 2,
187 MLX5_POLICY_INVALID
= 0xffffffff
190 struct mlx5_field_desc
{
195 struct mlx5_rsc_debug
{
196 struct mlx5_core_dev
*dev
;
198 enum dbg_rsc_type type
;
200 struct mlx5_field_desc fields
[0];
203 enum mlx5_dev_event
{
204 MLX5_DEV_EVENT_SYS_ERROR
,
205 MLX5_DEV_EVENT_PORT_UP
,
206 MLX5_DEV_EVENT_PORT_DOWN
,
207 MLX5_DEV_EVENT_PORT_INITIALIZED
,
208 MLX5_DEV_EVENT_LID_CHANGE
,
209 MLX5_DEV_EVENT_PKEY_CHANGE
,
210 MLX5_DEV_EVENT_GUID_CHANGE
,
211 MLX5_DEV_EVENT_CLIENT_REREG
,
213 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT
,
216 enum mlx5_port_status
{
224 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
229 struct mlx5_bfreg_info
{
231 int num_low_latency_bfregs
;
235 * protect bfreg allocation data structs
241 u32 num_static_sys_pages
;
242 u32 total_num_bfregs
;
246 struct mlx5_cmd_first
{
250 struct mlx5_cmd_msg
{
251 struct list_head list
;
252 struct cmd_msg_cache
*parent
;
254 struct mlx5_cmd_first first
;
255 struct mlx5_cmd_mailbox
*next
;
258 struct mlx5_cmd_debug
{
259 struct dentry
*dbg_root
;
260 struct dentry
*dbg_in
;
261 struct dentry
*dbg_out
;
262 struct dentry
*dbg_outlen
;
263 struct dentry
*dbg_status
;
264 struct dentry
*dbg_run
;
272 struct cmd_msg_cache
{
273 /* protect block chain allocations
276 struct list_head head
;
277 unsigned int max_inbox_size
;
278 unsigned int num_ent
;
282 MLX5_NUM_COMMAND_CACHES
= 5,
285 struct mlx5_cmd_stats
{
290 struct dentry
*count
;
291 /* protect command average calculations */
297 dma_addr_t alloc_dma
;
308 /* protect command queue allocations
310 spinlock_t alloc_lock
;
312 /* protect token allocations
314 spinlock_t token_lock
;
316 unsigned long bitmask
;
317 char wq_name
[MLX5_CMD_WQ_MAX_NAME
];
318 struct workqueue_struct
*wq
;
319 struct semaphore sem
;
320 struct semaphore pages_sem
;
322 struct mlx5_cmd_work_ent
*ent_arr
[MLX5_MAX_COMMANDS
];
323 struct dma_pool
*pool
;
324 struct mlx5_cmd_debug dbg
;
325 struct cmd_msg_cache cache
[MLX5_NUM_COMMAND_CACHES
];
326 int checksum_disabled
;
327 struct mlx5_cmd_stats stats
[MLX5_CMD_OP_MAX
];
330 struct mlx5_port_caps
{
337 struct mlx5_cmd_mailbox
{
340 struct mlx5_cmd_mailbox
*next
;
343 struct mlx5_buf_list
{
348 struct mlx5_frag_buf
{
349 struct mlx5_buf_list
*frags
;
355 struct mlx5_frag_buf_ctrl
{
356 struct mlx5_frag_buf frag_buf
;
364 struct mlx5_eq_tasklet
{
365 struct list_head list
;
366 struct list_head process_list
;
367 struct tasklet_struct task
;
368 /* lock on completion tasklet list */
372 struct mlx5_eq_pagefault
{
373 struct work_struct work
;
374 /* Pagefaults lock */
376 struct workqueue_struct
*wq
;
380 struct mlx5_cq_table
{
381 /* protect radix tree */
383 struct radix_tree_root tree
;
387 struct mlx5_core_dev
*dev
;
388 struct mlx5_cq_table cq_table
;
389 __be32 __iomem
*doorbell
;
391 struct mlx5_frag_buf buf
;
397 struct list_head list
;
399 struct mlx5_rsc_debug
*dbg
;
400 enum mlx5_eq_type type
;
402 struct mlx5_eq_tasklet tasklet_ctx
;
403 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
404 struct mlx5_eq_pagefault pf_ctx
;
409 struct mlx5_core_psv
{
421 struct mlx5_core_sig_ctx
{
422 struct mlx5_core_psv psv_memory
;
423 struct mlx5_core_psv psv_wire
;
424 struct ib_sig_err err_item
;
425 bool sig_status_checked
;
435 struct mlx5_core_mkey
{
443 #define MLX5_24BIT_MASK ((1 << 24) - 1)
446 MLX5_RES_QP
= MLX5_EVENT_QUEUE_TYPE_QP
,
447 MLX5_RES_RQ
= MLX5_EVENT_QUEUE_TYPE_RQ
,
448 MLX5_RES_SQ
= MLX5_EVENT_QUEUE_TYPE_SQ
,
452 MLX5_RES_DCT
= MLX5_EVENT_QUEUE_TYPE_DCT
,
455 struct mlx5_core_rsc_common
{
456 enum mlx5_res_type res
;
458 struct completion free
;
461 struct mlx5_core_srq
{
462 struct mlx5_core_rsc_common common
; /* must be first */
466 size_t max_avail_gather
;
468 void (*event
) (struct mlx5_core_srq
*, enum mlx5_event
);
471 struct completion free
;
474 struct mlx5_eq_table
{
475 void __iomem
*update_ci
;
476 void __iomem
*update_arm_ci
;
477 struct list_head comp_eqs_list
;
478 struct mlx5_eq pages_eq
;
479 struct mlx5_eq async_eq
;
480 struct mlx5_eq cmd_eq
;
481 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
482 struct mlx5_eq pfault_eq
;
484 int num_comp_vectors
;
490 struct mlx5_uars_page
{
494 struct list_head list
;
496 unsigned long *reg_bitmap
; /* for non fast path bf regs */
497 unsigned long *fp_bitmap
;
498 unsigned int reg_avail
;
499 unsigned int fp_avail
;
500 struct kref ref_count
;
501 struct mlx5_core_dev
*mdev
;
504 struct mlx5_bfreg_head
{
505 /* protect blue flame registers allocations */
507 struct list_head list
;
510 struct mlx5_bfreg_data
{
511 struct mlx5_bfreg_head reg_head
;
512 struct mlx5_bfreg_head wc_head
;
515 struct mlx5_sq_bfreg
{
517 struct mlx5_uars_page
*up
;
523 struct mlx5_core_health
{
524 struct health_buffer __iomem
*health
;
525 __be32 __iomem
*health_counter
;
526 struct timer_list timer
;
530 /* wq spinlock to synchronize draining */
532 struct workqueue_struct
*wq
;
534 struct work_struct work
;
535 struct delayed_work recover_work
;
538 struct mlx5_qp_table
{
539 /* protect radix tree
542 struct radix_tree_root tree
;
545 struct mlx5_srq_table
{
546 /* protect radix tree
549 struct radix_tree_root tree
;
552 struct mlx5_mkey_table
{
553 /* protect radix tree
556 struct radix_tree_root tree
;
559 struct mlx5_vf_context
{
563 enum port_state_policy policy
;
566 struct mlx5_core_sriov
{
567 struct mlx5_vf_context
*vfs_ctx
;
572 struct mlx5_irq_info
{
574 char name
[MLX5_MAX_IRQ_NAME
];
577 struct mlx5_fc_stats
{
578 struct rb_root counters
;
579 struct list_head addlist
;
580 /* protect addlist add/splice operations */
581 spinlock_t addlist_lock
;
583 struct workqueue_struct
*wq
;
584 struct delayed_work work
;
585 unsigned long next_query
;
586 unsigned long sampling_interval
; /* jiffies */
592 struct mlx5_pagefault
;
594 struct mlx5_rate_limit
{
600 struct mlx5_rl_entry
{
601 struct mlx5_rate_limit rl
;
606 struct mlx5_rl_table
{
607 /* protect rate limit table */
608 struct mutex rl_lock
;
612 struct mlx5_rl_entry
*rl_entry
;
615 enum port_module_event_status_type
{
616 MLX5_MODULE_STATUS_PLUGGED
= 0x1,
617 MLX5_MODULE_STATUS_UNPLUGGED
= 0x2,
618 MLX5_MODULE_STATUS_ERROR
= 0x3,
619 MLX5_MODULE_STATUS_NUM
= 0x3,
622 enum port_module_event_error_type
{
623 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED
,
624 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE
,
625 MLX5_MODULE_EVENT_ERROR_BUS_STUCK
,
626 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT
,
627 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST
,
628 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER
,
629 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE
,
630 MLX5_MODULE_EVENT_ERROR_BAD_CABLE
,
631 MLX5_MODULE_EVENT_ERROR_UNKNOWN
,
632 MLX5_MODULE_EVENT_ERROR_NUM
,
635 struct mlx5_port_module_event_stats
{
636 u64 status_counters
[MLX5_MODULE_STATUS_NUM
];
637 u64 error_counters
[MLX5_MODULE_EVENT_ERROR_NUM
];
641 char name
[MLX5_MAX_NAME_LEN
];
642 struct mlx5_eq_table eq_table
;
643 struct mlx5_irq_info
*irq_info
;
646 struct workqueue_struct
*pg_wq
;
647 struct rb_root page_root
;
650 struct list_head free_list
;
653 struct mlx5_core_health health
;
655 struct mlx5_srq_table srq_table
;
657 /* start: qp staff */
658 struct mlx5_qp_table qp_table
;
659 struct dentry
*qp_debugfs
;
660 struct dentry
*eq_debugfs
;
661 struct dentry
*cq_debugfs
;
662 struct dentry
*cmdif_debugfs
;
665 /* start: mkey staff */
666 struct mlx5_mkey_table mkey_table
;
667 /* end: mkey staff */
669 /* start: alloc staff */
670 /* protect buffer alocation according to numa node */
671 struct mutex alloc_mutex
;
674 struct mutex pgdir_mutex
;
675 struct list_head pgdir_list
;
676 /* end: alloc staff */
677 struct dentry
*dbg_root
;
679 /* protect mkey key part */
680 spinlock_t mkey_lock
;
683 struct list_head dev_list
;
684 struct list_head ctx_list
;
687 struct list_head waiting_events_list
;
688 bool is_accum_events
;
690 struct mlx5_flow_steering
*steering
;
691 struct mlx5_mpfs
*mpfs
;
692 struct mlx5_eswitch
*eswitch
;
693 struct mlx5_core_sriov sriov
;
694 struct mlx5_lag
*lag
;
695 unsigned long pci_dev_data
;
696 struct mlx5_fc_stats fc_stats
;
697 struct mlx5_rl_table rl_table
;
699 struct mlx5_port_module_event_stats pme_stats
;
701 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
702 void (*pfault
)(struct mlx5_core_dev
*dev
,
704 struct mlx5_pagefault
*pfault
);
706 struct srcu_struct pfault_srcu
;
708 struct mlx5_bfreg_data bfregs
;
709 struct mlx5_uars_page
*uar
;
712 enum mlx5_device_state
{
713 MLX5_DEVICE_STATE_UP
,
714 MLX5_DEVICE_STATE_INTERNAL_ERROR
,
717 enum mlx5_interface_state
{
718 MLX5_INTERFACE_STATE_UP
= BIT(0),
721 enum mlx5_pci_status
{
722 MLX5_PCI_STATUS_DISABLED
,
723 MLX5_PCI_STATUS_ENABLED
,
726 enum mlx5_pagefault_type_flags
{
727 MLX5_PFAULT_REQUESTOR
= 1 << 0,
728 MLX5_PFAULT_WRITE
= 1 << 1,
729 MLX5_PFAULT_RDMA
= 1 << 2,
732 /* Contains the details of a pagefault. */
733 struct mlx5_pagefault
{
739 /* Initiator or send message responder pagefault details. */
741 /* Received packet size, only valid for responders. */
744 * Number of resource holding WQE, depends on type.
748 * WQE index. Refers to either the send queue or
749 * receive queue, according to event_subtype.
753 /* RDMA responder pagefault details */
757 * Received packet size, minimal size page fault
758 * resolution required for forward progress.
767 struct work_struct work
;
771 struct list_head tirs_list
;
775 struct mlx5e_resources
{
778 struct mlx5_core_mkey mkey
;
779 struct mlx5_sq_bfreg bfreg
;
782 #define MLX5_MAX_RESERVED_GIDS 8
784 struct mlx5_rsvd_gids
{
790 #define MAX_PIN_NUM 8
792 u8 pin_caps
[MAX_PIN_NUM
];
793 struct work_struct out_work
;
794 u64 start
[MAX_PIN_NUM
];
800 struct cyclecounter cycles
;
801 struct timecounter tc
;
802 struct hwtstamp_config hwtstamp_config
;
804 unsigned long overflow_period
;
805 struct delayed_work overflow_work
;
806 struct mlx5_core_dev
*mdev
;
807 struct ptp_clock
*ptp
;
808 struct ptp_clock_info ptp_info
;
809 struct mlx5_pps pps_info
;
812 struct mlx5_core_dev
{
813 struct pci_dev
*pdev
;
815 struct mutex pci_status_mutex
;
816 enum mlx5_pci_status pci_status
;
818 char board_id
[MLX5_BOARD_ID_LEN
];
820 struct mlx5_port_caps port_caps
[MLX5_MAX_PORTS
];
822 u32 hca_cur
[MLX5_CAP_NUM
][MLX5_UN_SZ_DW(hca_cap_union
)];
823 u32 hca_max
[MLX5_CAP_NUM
][MLX5_UN_SZ_DW(hca_cap_union
)];
824 u32 pcam
[MLX5_ST_SZ_DW(pcam_reg
)];
825 u32 mcam
[MLX5_ST_SZ_DW(mcam_reg
)];
826 u32 fpga
[MLX5_ST_SZ_DW(fpga_cap
)];
827 u32 qcam
[MLX5_ST_SZ_DW(qcam_reg
)];
829 phys_addr_t iseg_base
;
830 struct mlx5_init_seg __iomem
*iseg
;
831 enum mlx5_device_state state
;
832 /* sync interface state */
833 struct mutex intf_state_mutex
;
834 unsigned long intf_state
;
835 void (*event
) (struct mlx5_core_dev
*dev
,
836 enum mlx5_dev_event event
,
837 unsigned long param
);
838 struct mlx5_priv priv
;
839 struct mlx5_profile
*profile
;
842 struct mlx5e_resources mlx5e_res
;
844 struct mlx5_rsvd_gids reserved_gids
;
847 #ifdef CONFIG_MLX5_FPGA
848 struct mlx5_fpga_device
*fpga
;
850 #ifdef CONFIG_RFS_ACCEL
851 struct cpu_rmap
*rmap
;
853 struct mlx5_clock clock
;
854 struct mlx5_ib_clock_info
*clock_info
;
855 struct page
*clock_info_page
;
861 struct mlx5_db_pgdir
*pgdir
;
862 struct mlx5_ib_user_db_page
*user_page
;
869 MLX5_COMP_EQ_SIZE
= 1024,
873 MLX5_PTYS_IB
= 1 << 0,
874 MLX5_PTYS_EN
= 1 << 2,
877 typedef void (*mlx5_cmd_cbk_t
)(int status
, void *context
);
880 MLX5_CMD_ENT_STATE_PENDING_COMP
,
883 struct mlx5_cmd_work_ent
{
885 struct mlx5_cmd_msg
*in
;
886 struct mlx5_cmd_msg
*out
;
889 mlx5_cmd_cbk_t callback
;
890 struct delayed_work cb_timeout_work
;
893 struct completion done
;
894 struct mlx5_cmd
*cmd
;
895 struct work_struct work
;
896 struct mlx5_cmd_layout
*lay
;
912 enum phy_port_state
{
916 struct mlx5_hca_vport_context
{
921 enum port_state_policy policy
;
922 enum phy_port_state phys_state
;
923 enum ib_port_state vport_state
;
924 u8 port_physical_state
;
933 u8 init_type_reply
; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
938 u16 qkey_violation_counter
;
939 u16 pkey_violation_counter
;
943 static inline void *mlx5_buf_offset(struct mlx5_frag_buf
*buf
, int offset
)
945 return buf
->frags
->buf
+ offset
;
948 #define STRUCT_FIELD(header, field) \
949 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
950 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
952 static inline struct mlx5_core_dev
*pci2mlx5_core_dev(struct pci_dev
*pdev
)
954 return pci_get_drvdata(pdev
);
957 extern struct dentry
*mlx5_debugfs_root
;
959 static inline u16
fw_rev_maj(struct mlx5_core_dev
*dev
)
961 return ioread32be(&dev
->iseg
->fw_rev
) & 0xffff;
964 static inline u16
fw_rev_min(struct mlx5_core_dev
*dev
)
966 return ioread32be(&dev
->iseg
->fw_rev
) >> 16;
969 static inline u16
fw_rev_sub(struct mlx5_core_dev
*dev
)
971 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) & 0xffff;
974 static inline u16
cmdif_rev(struct mlx5_core_dev
*dev
)
976 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) >> 16;
979 static inline u32
mlx5_base_mkey(const u32 key
)
981 return key
& 0xffffff00u
;
984 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl
*fbc
,
987 fbc
->log_stride
= 6 + MLX5_GET(cqc
, cqc
, cqe_sz
);
988 fbc
->log_sz
= MLX5_GET(cqc
, cqc
, log_cq_size
);
989 fbc
->sz_m1
= (1 << fbc
->log_sz
) - 1;
990 fbc
->log_frag_strides
= PAGE_SHIFT
- fbc
->log_stride
;
991 fbc
->frag_sz_m1
= (1 << fbc
->log_frag_strides
) - 1;
994 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl
*fbc
,
997 unsigned int frag
= (ix
>> fbc
->log_frag_strides
);
999 return fbc
->frag_buf
.frags
[frag
].buf
+
1000 ((fbc
->frag_sz_m1
& ix
) << fbc
->log_stride
);
1003 int mlx5_cmd_init(struct mlx5_core_dev
*dev
);
1004 void mlx5_cmd_cleanup(struct mlx5_core_dev
*dev
);
1005 void mlx5_cmd_use_events(struct mlx5_core_dev
*dev
);
1006 void mlx5_cmd_use_polling(struct mlx5_core_dev
*dev
);
1008 int mlx5_cmd_exec(struct mlx5_core_dev
*dev
, void *in
, int in_size
, void *out
,
1010 int mlx5_cmd_exec_cb(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
1011 void *out
, int out_size
, mlx5_cmd_cbk_t callback
,
1013 int mlx5_cmd_exec_polling(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
1014 void *out
, int out_size
);
1015 void mlx5_cmd_mbox_status(void *out
, u8
*status
, u32
*syndrome
);
1017 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
);
1018 int mlx5_cmd_alloc_uar(struct mlx5_core_dev
*dev
, u32
*uarn
);
1019 int mlx5_cmd_free_uar(struct mlx5_core_dev
*dev
, u32 uarn
);
1020 void mlx5_health_cleanup(struct mlx5_core_dev
*dev
);
1021 int mlx5_health_init(struct mlx5_core_dev
*dev
);
1022 void mlx5_start_health_poll(struct mlx5_core_dev
*dev
);
1023 void mlx5_stop_health_poll(struct mlx5_core_dev
*dev
);
1024 void mlx5_drain_health_wq(struct mlx5_core_dev
*dev
);
1025 void mlx5_trigger_health_work(struct mlx5_core_dev
*dev
);
1026 void mlx5_drain_health_recovery(struct mlx5_core_dev
*dev
);
1027 int mlx5_buf_alloc_node(struct mlx5_core_dev
*dev
, int size
,
1028 struct mlx5_frag_buf
*buf
, int node
);
1029 int mlx5_buf_alloc(struct mlx5_core_dev
*dev
,
1030 int size
, struct mlx5_frag_buf
*buf
);
1031 void mlx5_buf_free(struct mlx5_core_dev
*dev
, struct mlx5_frag_buf
*buf
);
1032 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev
*dev
, int size
,
1033 struct mlx5_frag_buf
*buf
, int node
);
1034 void mlx5_frag_buf_free(struct mlx5_core_dev
*dev
, struct mlx5_frag_buf
*buf
);
1035 struct mlx5_cmd_mailbox
*mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
1036 gfp_t flags
, int npages
);
1037 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
1038 struct mlx5_cmd_mailbox
*head
);
1039 int mlx5_core_create_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
1040 struct mlx5_srq_attr
*in
);
1041 int mlx5_core_destroy_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
);
1042 int mlx5_core_query_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
1043 struct mlx5_srq_attr
*out
);
1044 int mlx5_core_arm_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
1045 u16 lwm
, int is_srq
);
1046 void mlx5_init_mkey_table(struct mlx5_core_dev
*dev
);
1047 void mlx5_cleanup_mkey_table(struct mlx5_core_dev
*dev
);
1048 int mlx5_core_create_mkey_cb(struct mlx5_core_dev
*dev
,
1049 struct mlx5_core_mkey
*mkey
,
1051 u32
*out
, int outlen
,
1052 mlx5_cmd_cbk_t callback
, void *context
);
1053 int mlx5_core_create_mkey(struct mlx5_core_dev
*dev
,
1054 struct mlx5_core_mkey
*mkey
,
1055 u32
*in
, int inlen
);
1056 int mlx5_core_destroy_mkey(struct mlx5_core_dev
*dev
,
1057 struct mlx5_core_mkey
*mkey
);
1058 int mlx5_core_query_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mkey
*mkey
,
1059 u32
*out
, int outlen
);
1060 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mkey
*_mkey
,
1062 int mlx5_core_alloc_pd(struct mlx5_core_dev
*dev
, u32
*pdn
);
1063 int mlx5_core_dealloc_pd(struct mlx5_core_dev
*dev
, u32 pdn
);
1064 int mlx5_core_mad_ifc(struct mlx5_core_dev
*dev
, const void *inb
, void *outb
,
1065 u16 opmod
, u8 port
);
1066 void mlx5_pagealloc_init(struct mlx5_core_dev
*dev
);
1067 void mlx5_pagealloc_cleanup(struct mlx5_core_dev
*dev
);
1068 int mlx5_pagealloc_start(struct mlx5_core_dev
*dev
);
1069 void mlx5_pagealloc_stop(struct mlx5_core_dev
*dev
);
1070 void mlx5_core_req_pages_handler(struct mlx5_core_dev
*dev
, u16 func_id
,
1072 int mlx5_satisfy_startup_pages(struct mlx5_core_dev
*dev
, int boot
);
1073 int mlx5_reclaim_startup_pages(struct mlx5_core_dev
*dev
);
1074 void mlx5_register_debugfs(void);
1075 void mlx5_unregister_debugfs(void);
1077 void mlx5_fill_page_array(struct mlx5_frag_buf
*buf
, __be64
*pas
);
1078 void mlx5_fill_page_frag_array(struct mlx5_frag_buf
*frag_buf
, __be64
*pas
);
1079 void mlx5_rsc_event(struct mlx5_core_dev
*dev
, u32 rsn
, int event_type
);
1080 void mlx5_srq_event(struct mlx5_core_dev
*dev
, u32 srqn
, int event_type
);
1081 struct mlx5_core_srq
*mlx5_core_get_srq(struct mlx5_core_dev
*dev
, u32 srqn
);
1082 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
1083 unsigned int *irqn
);
1084 int mlx5_core_attach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
1085 int mlx5_core_detach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
1087 int mlx5_qp_debugfs_init(struct mlx5_core_dev
*dev
);
1088 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev
*dev
);
1089 int mlx5_core_access_reg(struct mlx5_core_dev
*dev
, void *data_in
,
1090 int size_in
, void *data_out
, int size_out
,
1091 u16 reg_num
, int arg
, int write
);
1093 int mlx5_db_alloc(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
1094 int mlx5_db_alloc_node(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
,
1096 void mlx5_db_free(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
1098 const char *mlx5_command_str(int command
);
1099 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev
*dev
);
1100 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev
*dev
);
1101 int mlx5_core_create_psv(struct mlx5_core_dev
*dev
, u32 pdn
,
1102 int npsvs
, u32
*sig_index
);
1103 int mlx5_core_destroy_psv(struct mlx5_core_dev
*dev
, int psv_num
);
1104 void mlx5_core_put_rsc(struct mlx5_core_rsc_common
*common
);
1105 int mlx5_query_odp_caps(struct mlx5_core_dev
*dev
,
1106 struct mlx5_odp_caps
*odp_caps
);
1107 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev
*dev
,
1108 u8 port_num
, void *out
, size_t sz
);
1109 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1110 int mlx5_core_page_fault_resume(struct mlx5_core_dev
*dev
, u32 token
,
1111 u32 wq_num
, u8 type
, int error
);
1114 int mlx5_init_rl_table(struct mlx5_core_dev
*dev
);
1115 void mlx5_cleanup_rl_table(struct mlx5_core_dev
*dev
);
1116 int mlx5_rl_add_rate(struct mlx5_core_dev
*dev
, u16
*index
,
1117 struct mlx5_rate_limit
*rl
);
1118 void mlx5_rl_remove_rate(struct mlx5_core_dev
*dev
, struct mlx5_rate_limit
*rl
);
1119 bool mlx5_rl_is_in_range(struct mlx5_core_dev
*dev
, u32 rate
);
1120 bool mlx5_rl_are_equal(struct mlx5_rate_limit
*rl_0
,
1121 struct mlx5_rate_limit
*rl_1
);
1122 int mlx5_alloc_bfreg(struct mlx5_core_dev
*mdev
, struct mlx5_sq_bfreg
*bfreg
,
1123 bool map_wc
, bool fast_path
);
1124 void mlx5_free_bfreg(struct mlx5_core_dev
*mdev
, struct mlx5_sq_bfreg
*bfreg
);
1126 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev
*dev
);
1127 int mlx5_core_roce_gid_set(struct mlx5_core_dev
*dev
, unsigned int index
,
1128 u8 roce_version
, u8 roce_l3_type
, const u8
*gid
,
1129 const u8
*mac
, bool vlan
, u16 vlan_id
, u8 port_num
);
1131 static inline int fw_initializing(struct mlx5_core_dev
*dev
)
1133 return ioread32be(&dev
->iseg
->initializing
) >> 31;
1136 static inline u32
mlx5_mkey_to_idx(u32 mkey
)
1141 static inline u32
mlx5_idx_to_mkey(u32 mkey_idx
)
1143 return mkey_idx
<< 8;
1146 static inline u8
mlx5_mkey_variant(u32 mkey
)
1152 MLX5_PROF_MASK_QP_SIZE
= (u64
)1 << 0,
1153 MLX5_PROF_MASK_MR_CACHE
= (u64
)1 << 1,
1157 MR_CACHE_LAST_STD_ENTRY
= 20,
1158 MLX5_IMR_MTT_CACHE_ENTRY
,
1159 MLX5_IMR_KSM_CACHE_ENTRY
,
1160 MAX_MR_CACHE_ENTRIES
1164 MLX5_INTERFACE_PROTOCOL_IB
= 0,
1165 MLX5_INTERFACE_PROTOCOL_ETH
= 1,
1168 struct mlx5_interface
{
1169 void * (*add
)(struct mlx5_core_dev
*dev
);
1170 void (*remove
)(struct mlx5_core_dev
*dev
, void *context
);
1171 int (*attach
)(struct mlx5_core_dev
*dev
, void *context
);
1172 void (*detach
)(struct mlx5_core_dev
*dev
, void *context
);
1173 void (*event
)(struct mlx5_core_dev
*dev
, void *context
,
1174 enum mlx5_dev_event event
, unsigned long param
);
1175 void (*pfault
)(struct mlx5_core_dev
*dev
,
1177 struct mlx5_pagefault
*pfault
);
1178 void * (*get_dev
)(void *context
);
1180 struct list_head list
;
1183 void *mlx5_get_protocol_dev(struct mlx5_core_dev
*mdev
, int protocol
);
1184 int mlx5_register_interface(struct mlx5_interface
*intf
);
1185 void mlx5_unregister_interface(struct mlx5_interface
*intf
);
1186 int mlx5_core_query_vendor_id(struct mlx5_core_dev
*mdev
, u32
*vendor_id
);
1188 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev
*dev
);
1189 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev
*dev
);
1190 bool mlx5_lag_is_active(struct mlx5_core_dev
*dev
);
1191 struct net_device
*mlx5_lag_get_roce_netdev(struct mlx5_core_dev
*dev
);
1192 int mlx5_lag_query_cong_counters(struct mlx5_core_dev
*dev
,
1196 struct mlx5_uars_page
*mlx5_get_uars_page(struct mlx5_core_dev
*mdev
);
1197 void mlx5_put_uars_page(struct mlx5_core_dev
*mdev
, struct mlx5_uars_page
*up
);
1199 #ifndef CONFIG_MLX5_CORE_IPOIB
1201 struct net_device
*mlx5_rdma_netdev_alloc(struct mlx5_core_dev
*mdev
,
1202 struct ib_device
*ibdev
,
1204 void (*setup
)(struct net_device
*))
1206 return ERR_PTR(-EOPNOTSUPP
);
1209 static inline void mlx5_rdma_netdev_free(struct net_device
*netdev
) {}
1211 struct net_device
*mlx5_rdma_netdev_alloc(struct mlx5_core_dev
*mdev
,
1212 struct ib_device
*ibdev
,
1214 void (*setup
)(struct net_device
*));
1215 void mlx5_rdma_netdev_free(struct net_device
*netdev
);
1216 #endif /* CONFIG_MLX5_CORE_IPOIB */
1218 struct mlx5_profile
{
1224 } mr_cache
[MAX_MR_CACHE_ENTRIES
];
1228 MLX5_PCI_DEV_IS_VF
= 1 << 0,
1231 static inline int mlx5_core_is_pf(struct mlx5_core_dev
*dev
)
1233 return !(dev
->priv
.pci_dev_data
& MLX5_PCI_DEV_IS_VF
);
1236 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1237 #define MLX5_VPORT_MANAGER(mdev) \
1238 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
1239 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1240 mlx5_core_is_pf(mdev))
1242 static inline int mlx5_get_gid_table_len(u16 param
)
1245 pr_warn("gid table length is zero\n");
1249 return 8 * (1 << param
);
1252 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev
*dev
)
1254 return !!(dev
->priv
.rl_table
.max_size
);
1257 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev
*dev
)
1259 return MLX5_CAP_GEN(dev
, affiliate_nic_vport_criteria
) &&
1260 MLX5_CAP_GEN(dev
, num_vhca_ports
) <= 1;
1263 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev
*dev
)
1265 return MLX5_CAP_GEN(dev
, num_vhca_ports
) > 1;
1268 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev
*dev
)
1270 return mlx5_core_is_mp_slave(dev
) ||
1271 mlx5_core_is_mp_master(dev
);
1274 static inline int mlx5_core_native_port_num(struct mlx5_core_dev
*dev
)
1276 if (!mlx5_core_mp_enabled(dev
))
1279 return MLX5_CAP_GEN(dev
, native_port_num
);
1283 MLX5_TRIGGERED_CMD_COMP
= (u64
)1 << 32,
1286 static inline const struct cpumask
*
1287 mlx5_get_vector_affinity(struct mlx5_core_dev
*dev
, int vector
)
1289 const struct cpumask
*mask
;
1290 struct irq_desc
*desc
;
1295 err
= mlx5_vector2eqn(dev
, MLX5_EQ_VEC_COMP_BASE
+ vector
, &eqn
, &irq
);
1299 desc
= irq_to_desc(irq
);
1300 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
1301 mask
= irq_data_get_effective_affinity_mask(&desc
->irq_data
);
1303 mask
= desc
->irq_common_data
.affinity
;
1308 #endif /* MLX5_DRIVER_H */