include/linux/mlx5/driver.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DRIVER_H
  34 #define MLX5_DRIVER_H
  35
  36 #include <linux/kernel.h>
  37 #include <linux/completion.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock_types.h>
  40 #include <linux/semaphore.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/radix-tree.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/mempool.h>
  46 #include <linux/interrupt.h>
  47
  48 #include <linux/mlx5/device.h>
  49 #include <linux/mlx5/doorbell.h>
  50 #include <linux/mlx5/srq.h>
  51
  52 enum {
  53         MLX5_BOARD_ID_LEN = 64,
  54         MLX5_MAX_NAME_LEN = 16,
  55 };
  56
  57 enum {
  58         /* one minute for the sake of bringup. Generally, commands must always
  59          * complete and we may need to increase this timeout value
  60          */
  61         MLX5_CMD_TIMEOUT_MSEC   = 60 * 1000,
  62         MLX5_CMD_WQ_MAX_NAME    = 32,
  63 };
  64
  65 enum {
  66         CMD_OWNER_SW            = 0x0,
  67         CMD_OWNER_HW            = 0x1,
  68         CMD_STATUS_SUCCESS      = 0,
  69 };
  70
  71 enum mlx5_sqp_t {
  72         MLX5_SQP_SMI            = 0,
  73         MLX5_SQP_GSI            = 1,
  74         MLX5_SQP_IEEE_1588      = 2,
  75         MLX5_SQP_SNIFFER        = 3,
  76         MLX5_SQP_SYNC_UMR       = 4,
  77 };
  78
  79 enum {
  80         MLX5_MAX_PORTS  = 2,
  81 };
  82
  83 enum {
  84         MLX5_EQ_VEC_PAGES        = 0,
  85         MLX5_EQ_VEC_CMD          = 1,
  86         MLX5_EQ_VEC_ASYNC        = 2,
  87         MLX5_EQ_VEC_PFAULT       = 3,
  88         MLX5_EQ_VEC_COMP_BASE,
  89 };
  90
  91 enum {
  92         MLX5_MAX_IRQ_NAME       = 32
  93 };
  94
  95 enum {
  96         MLX5_ATOMIC_MODE_IB_COMP        = 1 << 16,
  97         MLX5_ATOMIC_MODE_CX             = 2 << 16,
  98         MLX5_ATOMIC_MODE_8B             = 3 << 16,
  99         MLX5_ATOMIC_MODE_16B            = 4 << 16,
 100         MLX5_ATOMIC_MODE_32B            = 5 << 16,
 101         MLX5_ATOMIC_MODE_64B            = 6 << 16,
 102         MLX5_ATOMIC_MODE_128B           = 7 << 16,
 103         MLX5_ATOMIC_MODE_256B           = 8 << 16,
 104 };
 105
 106 enum {
 107         MLX5_REG_QETCR           = 0x4005,
 108         MLX5_REG_QTCT            = 0x400a,
 109         MLX5_REG_DCBX_PARAM      = 0x4020,
 110         MLX5_REG_DCBX_APP        = 0x4021,
 111         MLX5_REG_PCAP            = 0x5001,
 112         MLX5_REG_PMTU            = 0x5003,
 113         MLX5_REG_PTYS            = 0x5004,
 114         MLX5_REG_PAOS            = 0x5006,
 115         MLX5_REG_PFCC            = 0x5007,
 116         MLX5_REG_PPCNT           = 0x5008,
 117         MLX5_REG_PMAOS           = 0x5012,
 118         MLX5_REG_PUDE            = 0x5009,
 119         MLX5_REG_PMPE            = 0x5010,
 120         MLX5_REG_PELC            = 0x500e,
 121         MLX5_REG_PVLC            = 0x500f,
 122         MLX5_REG_PCMR            = 0x5041,
 123         MLX5_REG_PMLP            = 0x5002,
 124         MLX5_REG_NODE_DESC       = 0x6001,
 125         MLX5_REG_HOST_ENDIANNESS = 0x7004,
 126         MLX5_REG_MCIA            = 0x9014,
 127         MLX5_REG_MLCR            = 0x902b,
 128 };
 129
 130 enum mlx5_dcbx_oper_mode {
 131         MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
 132         MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
 133 };
 134
 135 enum {
 136         MLX5_ATOMIC_OPS_CMP_SWAP        = 1 << 0,
 137         MLX5_ATOMIC_OPS_FETCH_ADD       = 1 << 1,
 138 };
 139
 140 enum mlx5_page_fault_resume_flags {
 141         MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
 142         MLX5_PAGE_FAULT_RESUME_WRITE     = 1 << 1,
 143         MLX5_PAGE_FAULT_RESUME_RDMA      = 1 << 2,
 144         MLX5_PAGE_FAULT_RESUME_ERROR     = 1 << 7,
 145 };
 146
 147 enum dbg_rsc_type {
 148         MLX5_DBG_RSC_QP,
 149         MLX5_DBG_RSC_EQ,
 150         MLX5_DBG_RSC_CQ,
 151 };
 152
 153 struct mlx5_field_desc {
 154         struct dentry          *dent;
 155         int                     i;
 156 };
 157
 158 struct mlx5_rsc_debug {
 159         struct mlx5_core_dev   *dev;
 160         void                   *object;
 161         enum dbg_rsc_type       type;
 162         struct dentry          *root;
 163         struct mlx5_field_desc  fields[0];
 164 };
 165
 166 enum mlx5_dev_event {
 167         MLX5_DEV_EVENT_SYS_ERROR,
 168         MLX5_DEV_EVENT_PORT_UP,
 169         MLX5_DEV_EVENT_PORT_DOWN,
 170         MLX5_DEV_EVENT_PORT_INITIALIZED,
 171         MLX5_DEV_EVENT_LID_CHANGE,
 172         MLX5_DEV_EVENT_PKEY_CHANGE,
 173         MLX5_DEV_EVENT_GUID_CHANGE,
 174         MLX5_DEV_EVENT_CLIENT_REREG,
 175 };
 176
 177 enum mlx5_port_status {
 178         MLX5_PORT_UP        = 1,
 179         MLX5_PORT_DOWN      = 2,
 180 };
 181
 182 enum mlx5_eq_type {
 183         MLX5_EQ_TYPE_COMP,
 184         MLX5_EQ_TYPE_ASYNC,
 185 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 186         MLX5_EQ_TYPE_PF,
 187 #endif
 188 };
 189
 190 struct mlx5_bfreg_info {
 191         u32                    *sys_pages;
 192         int                     num_low_latency_bfregs;
 193         unsigned int           *count;
 194
 195         /*
 196          * protect bfreg allocation data structs
 197          */
 198         struct mutex            lock;
 199         u32                     ver;
 200         bool                    lib_uar_4k;
 201         u32                     num_sys_pages;
 202 };
 203
 204 struct mlx5_cmd_first {
 205         __be32          data[4];
 206 };
 207
 208 struct mlx5_cmd_msg {
 209         struct list_head                list;
 210         struct cmd_msg_cache           *parent;
 211         u32                             len;
 212         struct mlx5_cmd_first           first;
 213         struct mlx5_cmd_mailbox        *next;
 214 };
 215
 216 struct mlx5_cmd_debug {
 217         struct dentry          *dbg_root;
 218         struct dentry          *dbg_in;
 219         struct dentry          *dbg_out;
 220         struct dentry          *dbg_outlen;
 221         struct dentry          *dbg_status;
 222         struct dentry          *dbg_run;
 223         void                   *in_msg;
 224         void                   *out_msg;
 225         u8                      status;
 226         u16                     inlen;
 227         u16                     outlen;
 228 };
 229
 230 struct cmd_msg_cache {
 231         /* protect block chain allocations
 232          */
 233         spinlock_t              lock;
 234         struct list_head        head;
 235         unsigned int            max_inbox_size;
 236         unsigned int            num_ent;
 237 };
 238
 239 enum {
 240         MLX5_NUM_COMMAND_CACHES = 5,
 241 };
 242
 243 struct mlx5_cmd_stats {
 244         u64             sum;
 245         u64             n;
 246         struct dentry  *root;
 247         struct dentry  *avg;
 248         struct dentry  *count;
 249         /* protect command average calculations */
 250         spinlock_t      lock;
 251 };
 252
 253 struct mlx5_cmd {
 254         void           *cmd_alloc_buf;
 255         dma_addr_t      alloc_dma;
 256         int             alloc_size;
 257         void           *cmd_buf;
 258         dma_addr_t      dma;
 259         u16             cmdif_rev;
 260         u8              log_sz;
 261         u8              log_stride;
 262         int             max_reg_cmds;
 263         int             events;
 264         u32 __iomem    *vector;
 265
 266         /* protect command queue allocations
 267          */
 268         spinlock_t      alloc_lock;
 269
 270         /* protect token allocations
 271          */
 272         spinlock_t      token_lock;
 273         u8              token;
 274         unsigned long   bitmask;
 275         char            wq_name[MLX5_CMD_WQ_MAX_NAME];
 276         struct workqueue_struct *wq;
 277         struct semaphore sem;
 278         struct semaphore pages_sem;
 279         int     mode;
 280         struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
 281         struct pci_pool *pool;
 282         struct mlx5_cmd_debug dbg;
 283         struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
 284         int checksum_disabled;
 285         struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
 286 };
 287
 288 struct mlx5_port_caps {
 289         int     gid_table_len;
 290         int     pkey_table_len;
 291         u8      ext_port_cap;
 292         bool    has_smi;
 293 };
 294
 295 struct mlx5_cmd_mailbox {
 296         void           *buf;
 297         dma_addr_t      dma;
 298         struct mlx5_cmd_mailbox *next;
 299 };
 300
 301 struct mlx5_buf_list {
 302         void                   *buf;
 303         dma_addr_t              map;
 304 };
 305
 306 struct mlx5_buf {
 307         struct mlx5_buf_list    direct;
 308         int                     npages;
 309         int                     size;
 310         u8                      page_shift;
 311 };
 312
 313 struct mlx5_frag_buf {
 314         struct mlx5_buf_list    *frags;
 315         int                     npages;
 316         int                     size;
 317         u8                      page_shift;
 318 };
 319
 320 struct mlx5_eq_tasklet {
 321         struct list_head list;
 322         struct list_head process_list;
 323         struct tasklet_struct task;
 324         /* lock on completion tasklet list */
 325         spinlock_t lock;
 326 };
 327
 328 struct mlx5_eq_pagefault {
 329         struct work_struct       work;
 330         /* Pagefaults lock */
 331         spinlock_t               lock;
 332         struct workqueue_struct *wq;
 333         mempool_t               *pool;
 334 };
 335
 336 struct mlx5_eq {
 337         struct mlx5_core_dev   *dev;
 338         __be32 __iomem         *doorbell;
 339         u32                     cons_index;
 340         struct mlx5_buf         buf;
 341         int                     size;
 342         unsigned int            irqn;
 343         u8                      eqn;
 344         int                     nent;
 345         u64                     mask;
 346         struct list_head        list;
 347         int                     index;
 348         struct mlx5_rsc_debug   *dbg;
 349         enum mlx5_eq_type       type;
 350         union {
 351                 struct mlx5_eq_tasklet   tasklet_ctx;
 352 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 353                 struct mlx5_eq_pagefault pf_ctx;
 354 #endif
 355         };
 356 };
 357
 358 struct mlx5_core_psv {
 359         u32     psv_idx;
 360         struct psv_layout {
 361                 u32     pd;
 362                 u16     syndrome;
 363                 u16     reserved;
 364                 u16     bg;
 365                 u16     app_tag;
 366                 u32     ref_tag;
 367         } psv;
 368 };
 369
 370 struct mlx5_core_sig_ctx {
 371         struct mlx5_core_psv    psv_memory;
 372         struct mlx5_core_psv    psv_wire;
 373         struct ib_sig_err       err_item;
 374         bool                    sig_status_checked;
 375         bool                    sig_err_exists;
 376         u32                     sigerr_count;
 377 };
 378
 379 enum {
 380         MLX5_MKEY_MR = 1,
 381         MLX5_MKEY_MW,
 382 };
 383
 384 struct mlx5_core_mkey {
 385         u64                     iova;
 386         u64                     size;
 387         u32                     key;
 388         u32                     pd;
 389         u32                     type;
 390 };
 391
 392 #define MLX5_24BIT_MASK         ((1 << 24) - 1)
 393
 394 enum mlx5_res_type {
 395         MLX5_RES_QP     = MLX5_EVENT_QUEUE_TYPE_QP,
 396         MLX5_RES_RQ     = MLX5_EVENT_QUEUE_TYPE_RQ,
 397         MLX5_RES_SQ     = MLX5_EVENT_QUEUE_TYPE_SQ,
 398         MLX5_RES_SRQ    = 3,
 399         MLX5_RES_XSRQ   = 4,
 400 };
 401
 402 struct mlx5_core_rsc_common {
 403         enum mlx5_res_type      res;
 404         atomic_t                refcount;
 405         struct completion       free;
 406 };
 407
 408 struct mlx5_core_srq {
 409         struct mlx5_core_rsc_common     common; /* must be first */
 410         u32             srqn;
 411         int             max;
 412         int             max_gs;
 413         int             max_avail_gather;
 414         int             wqe_shift;
 415         void (*event)   (struct mlx5_core_srq *, enum mlx5_event);
 416
 417         atomic_t                refcount;
 418         struct completion       free;
 419 };
 420
 421 struct mlx5_eq_table {
 422         void __iomem           *update_ci;
 423         void __iomem           *update_arm_ci;
 424         struct list_head        comp_eqs_list;
 425         struct mlx5_eq          pages_eq;
 426         struct mlx5_eq          async_eq;
 427         struct mlx5_eq          cmd_eq;
 428 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 429         struct mlx5_eq          pfault_eq;
 430 #endif
 431         int                     num_comp_vectors;
 432         /* protect EQs list
 433          */
 434         spinlock_t              lock;
 435 };
 436
 437 struct mlx5_uars_page {
 438         void __iomem           *map;
 439         bool                    wc;
 440         u32                     index;
 441         struct list_head        list;
 442         unsigned int            bfregs;
 443         unsigned long          *reg_bitmap; /* for non fast path bf regs */
 444         unsigned long          *fp_bitmap;
 445         unsigned int            reg_avail;
 446         unsigned int            fp_avail;
 447         struct kref             ref_count;
 448         struct mlx5_core_dev   *mdev;
 449 };
 450
 451 struct mlx5_bfreg_head {
 452         /* protect blue flame registers allocations */
 453         struct mutex            lock;
 454         struct list_head        list;
 455 };
 456
 457 struct mlx5_bfreg_data {
 458         struct mlx5_bfreg_head  reg_head;
 459         struct mlx5_bfreg_head  wc_head;
 460 };
 461
 462 struct mlx5_sq_bfreg {
 463         void __iomem           *map;
 464         struct mlx5_uars_page  *up;
 465         bool                    wc;
 466         u32                     index;
 467         unsigned int            offset;
 468 };
 469
 470 struct mlx5_core_health {
 471         struct health_buffer __iomem   *health;
 472         __be32 __iomem                 *health_counter;
 473         struct timer_list               timer;
 474         u32                             prev;
 475         int                             miss_counter;
 476         bool                            sick;
 477         /* wq spinlock to synchronize draining */
 478         spinlock_t                      wq_lock;
 479         struct workqueue_struct        *wq;
 480         unsigned long                   flags;
 481         struct work_struct              work;
 482         struct delayed_work             recover_work;
 483 };
 484
 485 struct mlx5_cq_table {
 486         /* protect radix tree
 487          */
 488         spinlock_t              lock;
 489         struct radix_tree_root  tree;
 490 };
 491
 492 struct mlx5_qp_table {
 493         /* protect radix tree
 494          */
 495         spinlock_t              lock;
 496         struct radix_tree_root  tree;
 497 };
 498
 499 struct mlx5_srq_table {
 500         /* protect radix tree
 501          */
 502         spinlock_t              lock;
 503         struct radix_tree_root  tree;
 504 };
 505
 506 struct mlx5_mkey_table {
 507         /* protect radix tree
 508          */
 509         rwlock_t                lock;
 510         struct radix_tree_root  tree;
 511 };
 512
 513 struct mlx5_vf_context {
 514         int     enabled;
 515 };
 516
 517 struct mlx5_core_sriov {
 518         struct mlx5_vf_context  *vfs_ctx;
 519         int                     num_vfs;
 520         int                     enabled_vfs;
 521 };
 522
 523 struct mlx5_irq_info {
 524         cpumask_var_t mask;
 525         char name[MLX5_MAX_IRQ_NAME];
 526 };
 527
 528 struct mlx5_fc_stats {
 529         struct rb_root counters;
 530         struct list_head addlist;
 531         /* protect addlist add/splice operations */
 532         spinlock_t addlist_lock;
 533
 534         struct workqueue_struct *wq;
 535         struct delayed_work work;
 536         unsigned long next_query;
 537 };
 538
 539 struct mlx5_eswitch;
 540 struct mlx5_lag;
 541 struct mlx5_pagefault;
 542
 543 struct mlx5_rl_entry {
 544         u32                     rate;
 545         u16                     index;
 546         u16                     refcount;
 547 };
 548
 549 struct mlx5_rl_table {
 550         /* protect rate limit table */
 551         struct mutex            rl_lock;
 552         u16                     max_size;
 553         u32                     max_rate;
 554         u32                     min_rate;
 555         struct mlx5_rl_entry   *rl_entry;
 556 };
 557
 558 enum port_module_event_status_type {
 559         MLX5_MODULE_STATUS_PLUGGED   = 0x1,
 560         MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
 561         MLX5_MODULE_STATUS_ERROR     = 0x3,
 562         MLX5_MODULE_STATUS_NUM       = 0x3,
 563 };
 564
 565 enum  port_module_event_error_type {
 566         MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
 567         MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
 568         MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
 569         MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
 570         MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
 571         MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
 572         MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
 573         MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
 574         MLX5_MODULE_EVENT_ERROR_UNKNOWN,
 575         MLX5_MODULE_EVENT_ERROR_NUM,
 576 };
 577
 578 struct mlx5_port_module_event_stats {
 579         u64 status_counters[MLX5_MODULE_STATUS_NUM];
 580         u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
 581 };
 582
 583 struct mlx5_priv {
 584         char                    name[MLX5_MAX_NAME_LEN];
 585         struct mlx5_eq_table    eq_table;
 586         struct msix_entry       *msix_arr;
 587         struct mlx5_irq_info    *irq_info;
 588
 589         /* pages stuff */
 590         struct workqueue_struct *pg_wq;
 591         struct rb_root          page_root;
 592         int                     fw_pages;
 593         atomic_t                reg_pages;
 594         struct list_head        free_list;
 595         int                     vfs_pages;
 596
 597         struct mlx5_core_health health;
 598
 599         struct mlx5_srq_table   srq_table;
 600
 601         /* start: qp staff */
 602         struct mlx5_qp_table    qp_table;
 603         struct dentry          *qp_debugfs;
 604         struct dentry          *eq_debugfs;
 605         struct dentry          *cq_debugfs;
 606         struct dentry          *cmdif_debugfs;
 607         /* end: qp staff */
 608
 609         /* start: cq staff */
 610         struct mlx5_cq_table    cq_table;
 611         /* end: cq staff */
 612
 613         /* start: mkey staff */
 614         struct mlx5_mkey_table  mkey_table;
 615         /* end: mkey staff */
 616
 617         /* start: alloc staff */
 618         /* protect buffer alocation according to numa node */
 619         struct mutex            alloc_mutex;
 620         int                     numa_node;
 621
 622         struct mutex            pgdir_mutex;
 623         struct list_head        pgdir_list;
 624         /* end: alloc staff */
 625         struct dentry          *dbg_root;
 626
 627         /* protect mkey key part */
 628         spinlock_t              mkey_lock;
 629         u8                      mkey_key;
 630
 631         struct list_head        dev_list;
 632         struct list_head        ctx_list;
 633         spinlock_t              ctx_lock;
 634
 635         struct mlx5_flow_steering *steering;
 636         struct mlx5_eswitch     *eswitch;
 637         struct mlx5_core_sriov  sriov;
 638         struct mlx5_lag         *lag;
 639         unsigned long           pci_dev_data;
 640         struct mlx5_fc_stats            fc_stats;
 641         struct mlx5_rl_table            rl_table;
 642
 643         struct mlx5_port_module_event_stats  pme_stats;
 644
 645 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 646         void                  (*pfault)(struct mlx5_core_dev *dev,
 647                                         void *context,
 648                                         struct mlx5_pagefault *pfault);
 649         void                   *pfault_ctx;
 650         struct srcu_struct      pfault_srcu;
 651 #endif
 652         struct mlx5_bfreg_data          bfregs;
 653         struct mlx5_uars_page          *uar;
 654 };
 655
 656 enum mlx5_device_state {
 657         MLX5_DEVICE_STATE_UP,
 658         MLX5_DEVICE_STATE_INTERNAL_ERROR,
 659 };
 660
 661 enum mlx5_interface_state {
 662         MLX5_INTERFACE_STATE_DOWN = BIT(0),
 663         MLX5_INTERFACE_STATE_UP = BIT(1),
 664         MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
 665 };
 666
 667 enum mlx5_pci_status {
 668         MLX5_PCI_STATUS_DISABLED,
 669         MLX5_PCI_STATUS_ENABLED,
 670 };
 671
 672 enum mlx5_pagefault_type_flags {
 673         MLX5_PFAULT_REQUESTOR = 1 << 0,
 674         MLX5_PFAULT_WRITE     = 1 << 1,
 675         MLX5_PFAULT_RDMA      = 1 << 2,
 676 };
 677
 678 /* Contains the details of a pagefault. */
 679 struct mlx5_pagefault {
 680         u32                     bytes_committed;
 681         u32                     token;
 682         u8                      event_subtype;
 683         u8                      type;
 684         union {
 685                 /* Initiator or send message responder pagefault details. */
 686                 struct {
 687                         /* Received packet size, only valid for responders. */
 688                         u32     packet_size;
 689                         /*
 690                          * Number of resource holding WQE, depends on type.
 691                          */
 692                         u32     wq_num;
 693                         /*
 694                          * WQE index. Refers to either the send queue or
 695                          * receive queue, according to event_subtype.
 696                          */
 697                         u16     wqe_index;
 698                 } wqe;
 699                 /* RDMA responder pagefault details */
 700                 struct {
 701                         u32     r_key;
 702                         /*
 703                          * Received packet size, minimal size page fault
 704                          * resolution required for forward progress.
 705                          */
 706                         u32     packet_size;
 707                         u32     rdma_op_len;
 708                         u64     rdma_va;
 709                 } rdma;
 710         };
 711
 712         struct mlx5_eq         *eq;
 713         struct work_struct      work;
 714 };
 715
 716 struct mlx5_td {
 717         struct list_head tirs_list;
 718         u32              tdn;
 719 };
 720
 721 struct mlx5e_resources {
 722         u32                        pdn;
 723         struct mlx5_td             td;
 724         struct mlx5_core_mkey      mkey;
 725 };
 726
 727 struct mlx5_core_dev {
 728         struct pci_dev         *pdev;
 729         /* sync pci state */
 730         struct mutex            pci_status_mutex;
 731         enum mlx5_pci_status    pci_status;
 732         u8                      rev_id;
 733         char                    board_id[MLX5_BOARD_ID_LEN];
 734         struct mlx5_cmd         cmd;
 735         struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
 736         u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 737         u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 738         phys_addr_t             iseg_base;
 739         struct mlx5_init_seg __iomem *iseg;
 740         enum mlx5_device_state  state;
 741         /* sync interface state */
 742         struct mutex            intf_state_mutex;
 743         unsigned long           intf_state;
 744         void                    (*event) (struct mlx5_core_dev *dev,
 745                                           enum mlx5_dev_event event,
 746                                           unsigned long param);
 747         struct mlx5_priv        priv;
 748         struct mlx5_profile     *profile;
 749         atomic_t                num_qps;
 750         u32                     issi;
 751         struct mlx5e_resources  mlx5e_res;
 752 #ifdef CONFIG_RFS_ACCEL
 753         struct cpu_rmap         *rmap;
 754 #endif
 755 };
 756
 757 struct mlx5_db {
 758         __be32                  *db;
 759         union {
 760                 struct mlx5_db_pgdir            *pgdir;
 761                 struct mlx5_ib_user_db_page     *user_page;
 762         }                       u;
 763         dma_addr_t              dma;
 764         int                     index;
 765 };
 766
 767 enum {
 768         MLX5_COMP_EQ_SIZE = 1024,
 769 };
 770
 771 enum {
 772         MLX5_PTYS_IB = 1 << 0,
 773         MLX5_PTYS_EN = 1 << 2,
 774 };
 775
 776 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
 777
 778 struct mlx5_cmd_work_ent {
 779         struct mlx5_cmd_msg    *in;
 780         struct mlx5_cmd_msg    *out;
 781         void                   *uout;
 782         int                     uout_size;
 783         mlx5_cmd_cbk_t          callback;
 784         struct delayed_work     cb_timeout_work;
 785         void                   *context;
 786         int                     idx;
 787         struct completion       done;
 788         struct mlx5_cmd        *cmd;
 789         struct work_struct      work;
 790         struct mlx5_cmd_layout *lay;
 791         int                     ret;
 792         int                     page_queue;
 793         u8                      status;
 794         u8                      token;
 795         u64                     ts1;
 796         u64                     ts2;
 797         u16                     op;
 798 };
 799
 800 struct mlx5_pas {
 801         u64     pa;
 802         u8      log_sz;
 803 };
 804
 805 enum port_state_policy {
 806         MLX5_POLICY_DOWN        = 0,
 807         MLX5_POLICY_UP          = 1,
 808         MLX5_POLICY_FOLLOW      = 2,
 809         MLX5_POLICY_INVALID     = 0xffffffff
 810 };
 811
 812 enum phy_port_state {
 813         MLX5_AAA_111
 814 };
 815
 816 struct mlx5_hca_vport_context {
 817         u32                     field_select;
 818         bool                    sm_virt_aware;
 819         bool                    has_smi;
 820         bool                    has_raw;
 821         enum port_state_policy  policy;
 822         enum phy_port_state     phys_state;
 823         enum ib_port_state      vport_state;
 824         u8                      port_physical_state;
 825         u64                     sys_image_guid;
 826         u64                     port_guid;
 827         u64                     node_guid;
 828         u32                     cap_mask1;
 829         u32                     cap_mask1_perm;
 830         u32                     cap_mask2;
 831         u32                     cap_mask2_perm;
 832         u16                     lid;
 833         u8                      init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
 834         u8                      lmc;
 835         u8                      subnet_timeout;
 836         u16                     sm_lid;
 837         u8                      sm_sl;
 838         u16                     qkey_violation_counter;
 839         u16                     pkey_violation_counter;
 840         bool                    grh_required;
 841 };
 842
 843 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 844 {
 845                 return buf->direct.buf + offset;
 846 }
 847
 848 extern struct workqueue_struct *mlx5_core_wq;
 849
 850 #define STRUCT_FIELD(header, field) \
 851         .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
 852         .struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
 853
 854 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
 855 {
 856         return pci_get_drvdata(pdev);
 857 }
 858
 859 extern struct dentry *mlx5_debugfs_root;
 860
 861 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
 862 {
 863         return ioread32be(&dev->iseg->fw_rev) & 0xffff;
 864 }
 865
 866 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
 867 {
 868         return ioread32be(&dev->iseg->fw_rev) >> 16;
 869 }
 870
 871 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
 872 {
 873         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
 874 }
 875
 876 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
 877 {
 878         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 879 }
 880
 881 static inline void *mlx5_vzalloc(unsigned long size)
 882 {
 883         void *rtn;
 884
 885         rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
 886         if (!rtn)
 887                 rtn = vzalloc(size);
 888         return rtn;
 889 }
 890
 891 static inline u32 mlx5_base_mkey(const u32 key)
 892 {
 893         return key & 0xffffff00u;
 894 }
 895
 896 int mlx5_cmd_init(struct mlx5_core_dev *dev);
 897 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 898 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 899 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 900
 901 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 902                   int out_size);
 903 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
 904                      void *out, int out_size, mlx5_cmd_cbk_t callback,
 905                      void *context);
 906 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
 907
 908 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 909 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 910 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 911 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
 912 int mlx5_health_init(struct mlx5_core_dev *dev);
 913 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 914 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
 915 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
 916 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 917                         struct mlx5_buf *buf, int node);
 918 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
 919 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 920 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 921                              struct mlx5_frag_buf *buf, int node);
 922 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
 923 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 924                                                       gfp_t flags, int npages);
 925 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 926                                  struct mlx5_cmd_mailbox *head);
 927 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 928                          struct mlx5_srq_attr *in);
 929 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
 930 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 931                         struct mlx5_srq_attr *out);
 932 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 933                       u16 lwm, int is_srq);
 934 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
 935 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
 936 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
 937                              struct mlx5_core_mkey *mkey,
 938                              u32 *in, int inlen,
 939                              u32 *out, int outlen,
 940                              mlx5_cmd_cbk_t callback, void *context);
 941 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
 942                           struct mlx5_core_mkey *mkey,
 943                           u32 *in, int inlen);
 944 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
 945                            struct mlx5_core_mkey *mkey);
 946 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
 947                          u32 *out, int outlen);
 948 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
 949                              u32 *mkey);
 950 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
 951 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
 952 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
 953                       u16 opmod, u8 port);
 954 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
 955 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
 956 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
 957 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
 958 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
 959                                  s32 npages);
 960 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
 961 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
 962 void mlx5_register_debugfs(void);
 963 void mlx5_unregister_debugfs(void);
 964 int mlx5_eq_init(struct mlx5_core_dev *dev);
 965 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
 966 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
 967 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
 968 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
 969 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
 970 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
 971 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
 972 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
 973 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
 974 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 975                        int nent, u64 mask, const char *name,
 976                        enum mlx5_eq_type type);
 977 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 978 int mlx5_start_eqs(struct mlx5_core_dev *dev);
 979 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
 980 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
 981                     unsigned int *irqn);
 982 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 983 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 984
 985 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
 986 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
 987 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
 988                          int size_in, void *data_out, int size_out,
 989                          u16 reg_num, int arg, int write);
 990
 991 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 992 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 993 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 994                        u32 *out, int outlen);
 995 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
 996 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
 997 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
 998 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
 999 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1000 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1001                        int node);
1002 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1003
1004 const char *mlx5_command_str(int command);
1005 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1006 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1007 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1008                          int npsvs, u32 *sig_index);
1009 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1010 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1011 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1012                         struct mlx5_odp_caps *odp_caps);
1013 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1014                              u8 port_num, void *out, size_t sz);
1015 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1016 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1017                                 u32 wq_num, u8 type, int error);
1018 #endif
1019
1020 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1021 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1022 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1023 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1024 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1025 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1026                      bool map_wc, bool fast_path);
1027 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1028
1029 static inline int fw_initializing(struct mlx5_core_dev *dev)
1030 {
1031         return ioread32be(&dev->iseg->initializing) >> 31;
1032 }
1033
1034 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1035 {
1036         return mkey >> 8;
1037 }
1038
1039 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1040 {
1041         return mkey_idx << 8;
1042 }
1043
1044 static inline u8 mlx5_mkey_variant(u32 mkey)
1045 {
1046         return mkey & 0xff;
1047 }
1048
1049 enum {
1050         MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
1051         MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
1052 };
1053
1054 enum {
1055         MAX_UMR_CACHE_ENTRY = 20,
1056         MLX5_IMR_MTT_CACHE_ENTRY,
1057         MLX5_IMR_KSM_CACHE_ENTRY,
1058         MAX_MR_CACHE_ENTRIES
1059 };
1060
1061 enum {
1062         MLX5_INTERFACE_PROTOCOL_IB  = 0,
1063         MLX5_INTERFACE_PROTOCOL_ETH = 1,
1064 };
1065
1066 struct mlx5_interface {
1067         void *                  (*add)(struct mlx5_core_dev *dev);
1068         void                    (*remove)(struct mlx5_core_dev *dev, void *context);
1069         int                     (*attach)(struct mlx5_core_dev *dev, void *context);
1070         void                    (*detach)(struct mlx5_core_dev *dev, void *context);
1071         void                    (*event)(struct mlx5_core_dev *dev, void *context,
1072                                          enum mlx5_dev_event event, unsigned long param);
1073         void                    (*pfault)(struct mlx5_core_dev *dev,
1074                                           void *context,
1075                                           struct mlx5_pagefault *pfault);
1076         void *                  (*get_dev)(void *context);
1077         int                     protocol;
1078         struct list_head        list;
1079 };
1080
1081 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1082 int mlx5_register_interface(struct mlx5_interface *intf);
1083 void mlx5_unregister_interface(struct mlx5_interface *intf);
1084 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1085
1086 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1087 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1088 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1089 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1090 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1091 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1092
1093 struct mlx5_profile {
1094         u64     mask;
1095         u8      log_max_qp;
1096         struct {
1097                 int     size;
1098                 int     limit;
1099         } mr_cache[MAX_MR_CACHE_ENTRIES];
1100 };
1101
1102 enum {
1103         MLX5_PCI_DEV_IS_VF              = 1 << 0,
1104 };
1105
1106 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1107 {
1108         return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1109 }
1110
1111 static inline int mlx5_get_gid_table_len(u16 param)
1112 {
1113         if (param > 4) {
1114                 pr_warn("gid table length is zero\n");
1115                 return 0;
1116         }
1117
1118         return 8 * (1 << param);
1119 }
1120
1121 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1122 {
1123         return !!(dev->priv.rl_table.max_size);
1124 }
1125
1126 enum {
1127         MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1128 };
1129
1130 #endif /* MLX5_DRIVER_H */